CN110071067A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN110071067A CN110071067A CN201810065316.7A CN201810065316A CN110071067A CN 110071067 A CN110071067 A CN 110071067A CN 201810065316 A CN201810065316 A CN 201810065316A CN 110071067 A CN110071067 A CN 110071067A
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
A kind of semiconductor structure and forming method thereof, wherein method includes: offer substrate, and the substrate includes the firstth area, the secondth area and the third area between the firstth area and the secondth area, has nanometer terminal in third area substrate；The substrate for removing the nanometer terminal and nano wire column bottom part forms isolation opening in third area substrate；Separation layer is formed in the isolation is open.The performance of semiconductor device that the method is formed is preferable.
Description
Technical field
The present invention relates to field of semiconductor manufacture more particularly to a kind of semiconductor structure and forming method thereof.
Background technique
Metal-oxide semiconductor fieldeffect transistor (MOSFET) be in modern integrated circuits most important element it
One.With the development of semiconductor technology, the MOSFET of traditional plane formula dies down to the control ability of channel current, causes serious
Leakage current.Fin formula field effect transistor (Fin FET) is a kind of emerging multi-gate device, it, which is generally comprised, protrudes from semiconductor
The fin of substrate surface covers atop part surface and the grid of side wall of the fin, in the fin of grid two sides
Source and drain doping area.Compared with the MOSFET of plane formula, fin formula field effect transistor has stronger short channel rejection ability, has
Stronger operating current.
However, the integrated level of either planar transistor or fin formula field effect transistor is still lower.In order to further
The integrated level for improving semiconductor structure, proposes a kind of vertical all-around-gate structure (Veticalgate all around, GAA)
MOSFET.
However, the performance of the MOSFET of vertical all-around-gate structure in the prior art is to be improved.
Summary of the invention
The technical problem to be solved by the present invention is to provide a kind of semiconductor structures and forming method thereof, to improve vertical full encirclement
The performance of grid structure.
In order to solve the above technical problems, the embodiment of the present invention provides a kind of forming method of semiconductor structure, comprising: provide
Substrate, the substrate include the firstth area, the secondth area and the third area between the firstth area and the secondth area, third area base
There is nanometer terminal on bottom；The substrate for removing the nanometer terminal and nano wire column bottom part, in third area substrate
Interior formation isolation opening；Separation layer is formed in the isolation is open.
Optionally, the size keeping apart opening's edge and being parallel on substrate surface direction are as follows: 20 nanometers~60 nanometers.
Optionally, the depth of the isolation opening are as follows: 60 nanometers~120 nanometers.
Optionally, the forming step of the separation layer include: the base top surface and isolation opening in formed every
From material layer；Part spacer material layer is removed, until exposing substrate surface, forms the isolation in the isolation is open
Layer.
Optionally, the material of the spacer material layer includes: that silica, silicon oxynitride or low-K dielectric material, K are less than
3.9；The formation process of the spacer material layer includes: fluid chemistry gas-phase deposition, high-density plasma reinforced chemical
Depositing operation, high-aspect-ratio depositing operation or physical gas-phase deposition.
Optionally, the forming step of the isolation opening includes: to form light in firstth area and second area's base top
Photoresist；Using the photoresist as exposure mask, the nanometer terminal is removed, forms initial isolation opening；It removes and described initially keeps apart
The part of substrate of mouth bottom forms isolation opening.
Optionally, firstth area and second area's substrate surface are respectively provided with fin；Along substrate surface to fin and top
On the direction on surface, the fin includes the 4th area, the 5th area at the top of the 4th area and at the top of the 5th area
6th area；The first doped region is formed in the 4th area's fin, and there are Doped ions in first doped region；In the base
The side wall of bottom surface and the first doped region forms the first conductive structure；It is formed on first conductive structure around the 5th area's fin
The gate structure in portion；It is formed after the gate structure, forms the second doped region in the fin in the 6th area, described second
There are the Doped ions in doped region；The second conductive knot is formed in the side wall of the gate structure surface and the second doped region
Structure.
Optionally, firstth area is used to form the vertical all-around-gate structure of N-type, and secondth area is used to form p-type and hangs down
Straight all-around-gate structure；Doped ions in first doped region and the second doped region in firstth area are N-type ion；Described
Doped ions in first doped region and the second doped region in 2 area are P-type ion.
Optionally, minimum range of the fin side wall to nanometer terminal side wall are as follows: 10 nanometers~60 nanometers.
The present invention also provides a kind of semiconductor structures, comprising: substrate, the substrate include the firstth area, the secondth area and position
Third area between the firstth area and the secondth area；Positioned at the intrabasement isolation opening in the third area；It is open positioned at the isolation
Interior separation layer.
Optionally, the size keeping apart opening's edge and being parallel on substrate surface direction are as follows: 20 nanometers~60 nanometers.
Optionally, the depth of the isolation opening are as follows: 60 nanometers~120 nanometers.
Optionally, the material of the separation layer includes: silica, silicon oxynitride or low-K dielectric material, and K is less than 3.9.
Optionally, firstth area and second area's substrate surface are respectively provided with fin；The table at the top of substrate surface to fin
On the direction in face, the fin includes the 4th area, the 5th area at the top of the 4th area and the at the top of the 5th area the 6th
Area；The first doped region in the fin in the 4th area, first doped region is interior to have Doped ions；Positioned at the base
First conductive structure of bottom surface and doped region side wall；Positioned at first conductive structure surfaces around the grid of the fin in the 5th area
Pole structure；The second doped region in the fin in the 6th area, second doped region is interior to have the Doped ions；Position
In the gate structure surface and the second conductive structure of the side wall of the second doped region.
Optionally, firstth area is used to form the vertical all-around-gate structure of N-type, and secondth area is used to form p-type and hangs down
Straight all-around-gate structure；Doped ions in first doped region and the second doped region in firstth area are N-type ion；Described
Doped ions in first doped region and the second doped region in 2 area are P-type ion.
Optionally, minimum range of the fin side wall to separation layer side wall are as follows: 10 nanometers~60 nanometers.
Compared with prior art, the technical solution of the embodiment of the present invention has the advantages that
In the forming method for the semiconductor structure that technical solution of the present invention provides, the third area nanometer terminal is for defining
The position for the isolation opening being subsequently formed, so that the substrate of the subsequent removal nanometer terminal and nano wire column bottom, is formed
Isolation opening position it is more accurate, and be easy to control.For accommodating separation layer, the separation layer is used for the isolation opening
It realizes the electric isolution in subsequent firstth area fin in the first doped region and second area's fin between the second doped region, reduces the firstth area
And second the interfering with each other between area's device, be conducive to the performance for improving the firstth area and second area's device.
Detailed description of the invention
Fig. 1 is a kind of structural schematic diagram of vertical all-around-gate structure；
Fig. 2 to Figure 14 is the structural schematic diagram of each step of the forming method of the semiconductor structure of one embodiment of the invention.
Specific embodiment
The performance of vertical all-around-gate structure is poor as described in background.
Fig. 1 is a kind of structural schematic diagram of vertical all-around-gate structure.
Referring to FIG. 1, substrate 100, the substrate 100 includes the area N and the area P, and 100 surface of substrate has several fins
101, several fins 101 are located at the area N and the area P；The first doped region 102 is formed in 101 bottom of fin in the area N, it is described
First doped region 102 has the first Doped ions；The second doped region 103 is formed in 101 bottom of fin in the area P, described the
Two doped regions 103 have the second Doped ions, and the conduction of the conduction type of second Doped ions and the first Doped ions
Type is opposite.
In above-mentioned vertical all-around-gate structure, the area N is used to form the vertical all-around-gate structure of N-type, therefore, described
First Doped ions are N-type ion in one doped region 102, and the area P is used to form the vertical all-around-gate structure of p-type, therefore,
The second Doped ions in second doped region 103 are P-type ion.However, with the raising of semiconductor devices integrated level, N
Spacing between area and the area P constantly reduces, so that the performance interference between the first doped region 102 and the second doped region 103 is tighter
Weight, then the performance of the vertical all-around-gate structure of N-type and the vertical all-around-gate structure of p-type is poor.
To solve the technical problem, the present invention provides a kind of forming methods of semiconductor structure, comprising: the substrate
Including the firstth area, the secondth area and the third area between the firstth area and the secondth area, there is nanometer in third area substrate
Terminal；The substrate for removing the nanometer terminal and nano wire column bottom part forms in third area substrate and keeps apart
Mouthful；Separation layer is formed in the isolation is open.The device performance that the method is formed is preferable.
It is understandable to enable above-mentioned purpose of the invention, feature and beneficial effect to become apparent, with reference to the accompanying drawing to this
The specific embodiment of invention is described in detail.
Fig. 2 to Figure 14 is the structural schematic diagram of each step of the forming method of the semiconductor structure of one embodiment of the invention.
Referring to FIG. 2, provide substrate 200, the substrate 200 include the first area A, the second area B and be located at the first area A and
Third area C between second area B has several fins 201 in the firstth area A substrate 200, and several fins 201 distinguish position
In 200 surface the first area A and second area's B substrate, there is nanometer terminal 203 in the third area C substrate 200.
The forming step of the substrate 200, fin 201 and nanometer terminal 203 includes: offer initial substrate, described initial
There is the first mask layer (not marking in figure) in substrate, the third mask layer exposes the first area A, the second area B and third area C
The top surface of part initial substrate；Using first mask layer as exposure mask, the initial substrate is etched, forms substrate 200, position
In the fin 201 on 200 surface the first area A and second area's B substrate and nanometer terminal positioned at 200 surface of third area C substrate
203。
In the present embodiment, the material of the initial substrate is silicon, correspondingly, the substrate 200, fin 201 and nanometer
The material of terminal 203 is silicon.
In other embodiments, the material of the initial substrate includes: germanium, SiGe, silicon-on-insulator or germanium on insulator,
Correspondingly, the material of the substrate, fin and nanometer terminal includes: germanium, SiGe, silicon-on-insulator or germanium on insulator.
The material of first mask layer includes: the nitrogen oxides of the nitride of silicon, the oxide of silicon or silicon.Described
One mask layer is as the exposure mask for forming substrate 200, fin 201 and nanometer terminal 203.
The nanometer terminal 203 is used to define the position for the isolation opening being subsequently formed, so that being formed by isolation opening
Position it is more accurate, and be easy to control.
In the present embodiment, it is 1 with the number of firstth area fin 201 and second area's fin 201 to be illustrated.
In other embodiments, the number of firstth area fin can be two or more, secondth area fin
Number is two or more.
Minimum range of 201 side wall of fin to 203 side wall of nanometer terminal are as follows: 10 nanometers~60 nanometers.
Using first mask layer as exposure mask, the technique for etching the initial substrate includes: dry etch process and wet process
One of etching technics or two kinds of combinations.
In the present embodiment, have adhesion layer (in figure between first mask layer and fin 201 and nanometer terminal 203
It does not mark).
In other embodiments, first mask layer is located at the top surface of fin and nanometer terminal, it may be assumed that described first
Do not have adhesion layer between mask layer and fin and nanometer terminal.
In the present embodiment, the material of the adhesion layer includes: silica.The adhesion layer is for increasing by the first mask layer
With the adhesion strength between fin and nanometer terminal.
In the present embodiment, include the 4th area D on 200 surface of substrate to the direction on 201 surface of fin, be located at the 4th area D
On the 5th area E and the 6th area F on the 5th area E.
The 4th area D is for being subsequently formed the first conductive structure, the firstth area A and the 5th area E for being subsequently formed
Around the first grid floor of first area's A fin 201, the secondth area B and the 5th area E are for being subsequently formed around second area's B fin
The second grid layer in portion 201, the 6th area F is for being subsequently formed the second conductive structure.
Referring to FIG. 3, in the side wall and top surface of the firstth area A and second area's B substrate surface and fin 201
Form photoresist 204；It is exposure mask with the photoresist 204, removes the nanometer terminal 203.
The photoresist 204 is used to protect side wall and the top in the first area I and II substrate 200 of the secondth area and fin 201
Surface.
In the present embodiment, when removing the nanometer terminal 203,203 bottom part substrate 200 of nanometer terminal is also removed,
Initial isolation opening 205 is formed in the substrate 200.
In other embodiments, part nanometer terminal is removed, remaining nanometer terminal is when being subsequently formed isolation opening one
It rises and is removed.
The technique for removing nanometer terminal portion 203 includes: one of dry etch process or wet-etching technology
Or two kinds of combinations.
The initial isolation opening 205 is for being subsequently formed isolation opening.
The 205 bottom part substrates 200 referring to FIG. 4, the removal initial isolation is open, are open in the initial isolation
Isolation opening 206 is formed on 205 bottoms.
The technique for removing 205 bottom part substrates 200 of the initial isolation opening includes: that dry etch process and wet process are carved
One of etching technique or two kinds of combinations.
The isolation opening 206 is used for subsequent receiving separation layer.
206 edge of isolation opening is parallel to the size in 200 surface direction of substrate are as follows: 20 nanometers~60 nanometers.
The depth of the isolation opening 206 are as follows: 60 nanometers~120 nanometers.
The position of the isolation opening 206 is defined by nanometer terminal 203, so that the position of the isolation opening 206 is more
Add accurately, and is easy to control.
Referring to FIG. 5, being open in the isolation, 206 (see Fig. 4) are interior to form separation layer 207, and the separation layer 207 is full of
Opening 206.
It is formed before the separation layer 207, the forming method further include: remove the photoresist 204.
Remove the photoresist 204 technique include: in dry etch process, wet-etching technology and cineration technics one
Kind or multiple combinations.
The forming step of the separation layer 207 includes: side wall and the top at 200 top of substrate and fin 201
Surface forms spacer material layer；Part spacer material layer is removed, until exposing the surface of substrate 200, is open in the isolation
Separation layer 207 is formed in 206.
The material of the spacer material layer includes: silica or silicon oxynitride.The formation process of the spacer material layer
It include: fluid chemistry gas-phase deposition.The step of fluid chemistry gas-phase deposition include: in the substrate 200 and
The side wall and top surface of fin 201 form presoma；Curing process is carried out to the presoma, solidifies the presoma,
Form isolated material film.The presoma is that fluid can be sufficient filling with the gap between adjacent fin 201, to form isolation
The spacer material layer of better performances.
In other embodiments, the technique for forming the spacer material layer includes high-density plasma reinforced chemical deposition
Technique, high-aspect-ratio depositing operation or physical gas-phase deposition.
The separation layer 207 for realizing between first area's A semiconductor devices and second area's B semiconductor devices electricity every
From.
Referring to FIG. 6, the side wall and top surface at 200 top of substrate and fin 201 form gate dielectric film
208。
The material of the gate dielectric film 208 is high K dielectric material,
In the present embodiment, the material of the gate dielectric film 208 is HfO2.In other embodiments, the gate dielectric film
Material include: La2O3、HfSiON、HfAlO2、ZrO2、Al2O3Or HfSiO4。
In the present embodiment, the formation process of the gate dielectric film 208 includes: atom layer deposition process.
The part gate dielectric film 208 of the firstth area A is for being subsequently formed the first gate dielectric layer；The portion of the secondth area B
Gate dielectric film 208 is divided to be used as the second gate dielectric layer for subsequent.
Referring to FIG. 7, forming oxide layer 209 and the side wall positioned at 209 top of oxide layer at the top of the gate dielectric film 208
Film 210.
The material of the oxide layer 209 includes silica, and the formation process of the oxide layer 209 includes: chemical vapor deposition
Product technique or atom layer deposition process.The oxide layer 209 is used to be subsequently formed the stop-layer of initial side wall.
The material of the side wall film 210 includes: silicon nitride, and the material of the material of the side wall film 210 and oxide layer 209 is not
Together, so that when the sidewall film 210 on subsequent removal 200 surface of substrate, there is different etchings to select for side wall film 210 and oxide layer 209
Ratio is selected, so that etching technics rests on the surface of oxide layer 209, and the oxide layer 209 is located in substrate 200, therefore, described
Oxide layer 209 can prevent 200 surface of substrate to be damaged, and be conducive to the performance for improving semiconductor devices.
The formation process of the side wall film 210 includes: chemical vapor deposition process or atom layer deposition process.The side
Wall film 210 is for being subsequently formed side wall.
Referring to FIG. 8, the side wall film 210 (see Fig. 7) of removal substrate 200,201 top of fin, in the side of the fin 201
Wall forms initial side wall 211.
Remove substrate 200, the technique of side wall film 210 (see Fig. 7) at the top of fin 201 includes: dry etch process and wet
One of method etching technics or two kinds of combinations.
The material of the initial side wall 211 includes silicon nitride.
The effect of the initial side wall 211 include: on the one hand, the initial side wall 211 for subsequent removal substrate 200,
The oxidation film 209 of 201 top surface of fin and the exposure mask of gate dielectric film 209；On the other hand, after the initial side wall 211 is used for
It is continuous to form side wall.
Referring to FIG. 9, being exposure mask with the initial side wall 211, the oxidation of substrate 200 and 201 top surface of fin is removed
Film 209 exposes the first gate dielectric film 209；After the oxidation film 209 for removing substrate 200 and 201 top surface of fin, removal
The gate dielectric film 208 of substrate 200,201 bottom sidewall of the 4th area's D fin, exposes the side wall of 201 bottom of the 4th area's D fin；Cruelly
After the side wall for exposing 201 bottom of the 4th area's D fin, the first doped region 280 is formed in the fin 201 of the 4th area D, described
There are Doped ions in one doped region 280.
It is exposure mask with the initial side wall 211, the technique for removing the oxidation film 209 of substrate 200 and 201 top surface of fin
It include: one of dry etch process and wet-etching technology or two kinds of combinations.
The technique for removing the gate dielectric film 208 of substrate 200 and 201 bottom sidewall of fin includes: dry etch process and wet
One of method etching technics or two kinds of combinations.
The oxidation film 209 and gate dielectric film 208 for removing substrate 200 and 201 bottom sidewall of fin, are conducive to expose
The side wall of 4th area's D fin, 201 bottom is conducive to subsequent form the first doped region in the 4th area's D fin 201.
The first doped region 280 of the firstth area A is used for source region or drain region as the first formed transistor of area A；
The first doped region 280 of the secondth area B is used for source region or drain region as the second formed transistor of area B.
In the present embodiment, the forming method of first doped region 280 includes: by the first ion implantation technology
Doped ions are injected in the fin 201 of four area D, form first doped region 280.
In the present embodiment, the first area A is used to form the vertical all-around-gate structure of N-type, therefore, in the firstth area A
Doped ions are N-type ion in first doped region 280, such as: phosphonium ion or arsenic ion.It is vertically complete that second area B is used to form p-type
Surround grid structure, therefore, in the first doped region 280 in the secondth area B Doped ions be P-type ion, such as: boron ion or
BF2 +Ion.
It is subsequent (not marked in figure in the side wall of 200 surface of substrate and the first doped region 280 the first conductive structure of formation
Out).First conductive structure includes: the first metal silicide layer and inserts positioned at the first of the first metal silicide layer surface
Plug.The forming step of first conductive structure specifically please refers to Figure 10 to Figure 11.
Referring to FIG. 10, the side wall of the first doped region 280 and the second doped region 281, initial side wall 211 side wall, with
And 200 surface of substrate forms the first metal layer 212；The first plug film 213 is formed in 212 top surface of the first metal layer.
The material of the first metal layer 212 includes: titanium or nickel platinum.
It is formed after the first metal layer 212, is formed before the first plug film 213, the forming method is also wrapped
It includes: being made annealing treatment, react part the first metal layer 212 with the first doped region 280 and form the first metal silicide layer (figure
In be not shown).
The material of first metal silicide layer includes: titanium-silicon compound or nickel platinum silicon compound.
First metal silicide layer for reducing the first doped region 280 and subsequent first plug contact resistance.
In the present embodiment, it is formed after first metal silicide layer, does not remove unreacted the first metal layer, not
The subsequent some materials as the first plug of the first metal layer of reaction.
In other embodiments, it is formed after the first metal silicide layer, removes unreacted the first metal layer.
The forming step of the first plug film 213 includes: to form the first plug material on the first metal layer surface
Layer；The first plug material layer and the first metal layer are planarized, until exposing the top surface of fin 201, forms first
Plug film 213.
In the present embodiment, the material of the first plug material layer is tungsten, correspondingly, the material of the first plug film 213
For tungsten.In other embodiments, the material of the first plug material layer includes: aluminium, copper, titanium, silver, gold, lead or nickel, accordingly
, the material of the first plug film includes: aluminium, copper, titanium, silver, gold, lead or nickel.
The technique for planarizing the first plug material layer and the first metal layer includes: chemical mechanical milling tech.
Figure 11 is please referred to, the first plug film 213 (see Figure 10) of initial 211 side wall of side wall is removed, the described 4th
D substrate 200 surface in area's forms the first initial plug (not marking in figure)；The III first initial plug of part of third area is removed,
The first plug 215 is formed, there is opening 216 in first plug 215.
The technique for removing the first plug film 213 of 211 side wall of initial side wall includes: that wet-etching technology and dry method are carved
One of etching technique or two kinds of combinations.
The technique for removing the III first initial plug of part of third area includes: wet-etching technology and dry etch process
One of or two kinds combination.
In the present embodiment, the material of first plug 215 is tungsten.In other embodiments, first plug
Material includes: aluminium, copper, titanium, silver, gold, lead or nickel.
First conductive structure include: the first metal layer 212, the first metal silicide layer and be located at the first metal layer
212 and first metal silicide layer surface the first plug 215.
First opening 216 is electrically isolated for realizing the first area A and second area's B semiconductor devices.
Figure 12 is please referred to, forms first medium layer 217 at the top of first plug 215, the first medium layer 217 covers
The partial sidewall of the initial side wall 211 of the 5th area E of lid；The initial side wall 211 of the 6th area F is removed, forms side wall in the 5th area E
218, the side wall 218 exposes the top surface of first medium layer 217；It is formed after the side wall 218, removes the 6th area F
Oxidation film 209 forms oxide layer 239 until exposing the top surface of side wall 218 and first medium layer 217.
The material of the first medium layer 217 includes: silica or silicon oxynitride, and silica has good isolation
Energy.In other embodiments, the material of first separation layer can also be silicon nitride, silicon oxynitride or low k (k is less than 3.9)
Dielectric material, the low k dielectric materials are porous material.
The formation process of the first medium layer 217 includes: fluid chemistry gas-phase deposition.The first medium layer
217 with isolation the first plug 25 and the second plug being subsequently formed between electric isolution.
Remove the initial side wall 211 of the 6th area F technique include: one of dry etch process and wet-etching technology or
Two kinds of person combinations.
Remove the 6th area's F oxidation film 209 technique include: one of dry etch process and wet-etching technology or
Two kinds of combinations.
The material of the oxide layer 239 includes: silica.
Figure 13 is please referred to, in the first medium layer 217, side wall 218 and 239 top of oxide layer and the first gate medium of part
The surface of film 208 forms the grid layer 219 around the 5th area's E fin 201；It is formed after the gate structure 219, removes part
Gate dielectric film 208 (see Figure 12), forms gate dielectric layer 248, and the gate dielectric layer 248 exposes the side of the 6th area's F fin 201
Wall.
The material of the second metal layer includes: titanium or nickel platinum.
The material of the grid layer 219 is metal.In the present embodiment, the material of grid layer 219 is tungsten.In other implementations
In example, the material of the grid layer includes: copper, silver, gold, nickel or titanium.
The grid layer 219 and gate dielectric layer 248 constitute gate structure
Removal part gate dielectric film 208 technique include: one of dry etch process and wet-etching technology or
Two kinds of combinations.
The gate dielectric layer 248 exposes the side wall of the 6th area's F fin 201, is conducive to subsequent in the 6th area's F fin 201
The second doped region of interior formation.
Figure 14 is please referred to, forms second dielectric layer 250 on the gate structure surface, the second dielectric layer 250 covers
The side wall of part fin 201；The second conductive structure (not marking in figure) is formed at the top of the second dielectric layer 250.
The material of the second dielectric layer 250 includes: silica, and the formation process of the second dielectric layer 250 includes: stream
Body chemical vapor phase growing technique.
The second dielectric layer 250 is for realizing between first grid structure and second grid structure and the second conductive structure
Electric isolution.
It is formed after the second dielectric layer 250, is formed before second conductive structure, the forming method is also wrapped
It includes: forming the second doped region in the 6th area's F fin 201, there are the Doped ions in second doped region.
The forming step of the third doped region is identical as the forming step of the first doped region, and this will not be repeated here.
The forming step of 4th doped region is identical as the forming step of the second doped region, and therefore not to repeat here.
The first doped region 280 of the firstth area A is used as the source region of first area's A transistor, then first the second doped region of area A
Drain region as first area's A transistor；Alternatively, first doped region of the firstth area A 280 is used as the drain region of first area's A transistor,
Then first the second doped region of area A is used as the source region of first area's A transistor.
Secondth area B, first doped region 280 is used as the source region of second area's B transistor, then second the second doped region of area B is used
Make the drain region of second area's B transistor；Alternatively, first doped region of the secondth area B 280 is used as the drain region of second area's B transistor, then
Second the second doped region of area B is used as the source region of second area's B transistor.
Second conductive structure includes: third metal layer (not marking in figure) and positioned at the second of third layer on surface of metal
Plug 221.
The material of the third metal layer includes: titanium or nickel platinum.
It is formed after the third metal layer, is formed before second plug 221, the forming method includes: to carry out
Annealing, so that third metal layer reacts to form the second gold medal with third doped region and third metal layer with the 4th doped region
Belong to silicide layer.
The material of second metal silicide layer includes: titanium-silicon compound or nickel platinum silicon compound.
Second metal silicide layer for reducing the second plug 221 and third doped region and the second plug 221 with
Contact resistance between 4th doped region.
In the present embodiment, it is formed after second metal silicide layer, is formed before the second plug 221, the shape
It does not include: the unreacted third metal layer of removal at method.
In other embodiments, it is formed after second metal silicide layer, is formed before the second plug, the formation
Method includes: the unreacted third metal layer of removal.
The material of second plug 221 is metal.In the present embodiment, the material of second plug 221 is tungsten.
Correspondingly, the embodiment of the present invention also provides one kind is formed by semiconductor structure in aforementioned manners, Figure 14 is please referred to,
Include:
Substrate 200, the substrate 200 is including the first area A, the second area B and between the first area A and the second area B
Third area C；
204 (see Fig. 4) of isolation opening in the third area C substrate 200；
Separation layer 207 in the isolation opening 204.
The isolation opening 204 is 20 nanometers~60 nanometers along the size being parallel in 200 surface direction of substrate.
The depth of the isolation opening 204 are as follows: 60 nanometers~120 nanometers.
The material of the separation layer 207 includes: silica, silicon oxynitride or low-K dielectric material, and K is less than 3.9.
The firstth area A and second area's B substrate, 200 surface are respectively provided with fin 201；Along 200 surface of substrate to fin 201
On the direction of top surface, the fin 201 is including the 4th area D, the 5th area E at the top of the 4th area D and positioned at the 5th
The 6th area F at the top of area E；The first doped region 280 in the fin 201 of the 4th area D, in first doped region
280 have Doped ions；The first conductive structure positioned at 200 surface of substrate and 280 side wall of the first doped region；Positioned at described
Gate structure of first conductive structure surfaces around the fin 201 of the 5th area E；In the fin 201 of the 6th area F
Two doped region (not shown)s, second doped region is interior to have the Doped ions；Positioned at the gate structure surface and
Second conductive structure of the second doped region side wall.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (16)
1. a kind of forming method of semiconductor structure characterized by comprising
Substrate is provided, the substrate includes the firstth area, the secondth area and the third area between the firstth area and the secondth area, described
There is nanometer terminal in third area substrate；
The part of substrate for removing the nanometer terminal and nano wire column bottom forms in third area substrate and keeps apart
Mouthful；
Separation layer is formed in the isolation is open.
2. the forming method of semiconductor structure as described in claim 1, which is characterized in that the opening's edge of keeping apart is parallel to base
Size on bottom surface direction are as follows: 20 nanometers~60 nanometers.
3. the forming method of semiconductor structure as described in claim 1, which is characterized in that the depth of the isolation opening are as follows:
60 nanometers~120 nanometers.
4. the forming method of semiconductor structure as described in claim 1, which is characterized in that the forming step packet of the separation layer
It includes: forming spacer material layer in the base top surface and isolation opening；Part spacer material layer is removed, until exposing
Substrate surface forms the separation layer in the isolation is open.
5. the forming method of semiconductor structure as claimed in claim 4, which is characterized in that the material packet of the spacer material layer
Include: silica, silicon oxynitride or low-K dielectric material, K is less than 3.9；The formation process of the spacer material layer includes: fluid
Chemical vapor deposition process, high-density plasma reinforced chemical depositing operation, high-aspect-ratio depositing operation or physical vapor are heavy
Product technique.
6. the forming method of semiconductor structure as described in claim 1, which is characterized in that the forming step of the isolation opening
It include: to form photoresist in firstth area and second area's base top；Using the photoresist as exposure mask, the nano wire is removed
Column forms initial isolation opening；The part of substrate for removing the initial isolation open bottom, forms isolation opening.
7. the forming method of semiconductor structure as described in claim 1, which is characterized in that firstth area and second area's substrate
Surface is respectively provided with fin；Along substrate surface to the direction of fin top surface, the fin includes the 4th area, is located at the 4th
The 5th area at the top of area and the 6th area at the top of the 5th area；The first doped region is formed in the 4th area's fin, institute
Stating has Doped ions in the first doped region；The first conductive structure is formed in the substrate surface and the first doped region side wall；?
First conductive structure surfaces form the gate structure around the 5th area's fin；It is formed after the gate structure,
The second doped region is formed in the fin in the 6th area, and there are the Doped ions in second doped region；Institute
The side wall for stating gate structure surface and the second doped region forms the second conductive structure.
8. the forming method of semiconductor structure as claimed in claim 7, which is characterized in that firstth area is used to form N-type
Vertical all-around-gate structure, secondth area is used to form the vertical all-around-gate structure of p-type；First doped region in firstth area
It is N-type ion with the Doped ions in the second doped region；Doping in first doped region and the second doped region in secondth area
Ion is P-type ion.
9. the forming method of semiconductor structure as claimed in claim 7, which is characterized in that fin side wall to nanometer terminal side wall
Minimum range are as follows: 10 nanometers~60 nanometers.
10. a kind of semiconductor structure characterized by comprising
Substrate, the substrate include the firstth area, the secondth area and the third area between the firstth area and the secondth area；
Positioned at the intrabasement isolation opening in the third area；
Separation layer in the isolation opening.
11. semiconductor structure as claimed in claim 10, which is characterized in that the opening's edge of keeping apart is parallel to substrate surface side
Upward size are as follows: 20 nanometers~60 nanometers.
12. semiconductor structure as claimed in claim 10, which is characterized in that the depth of the isolation opening are as follows:
60 nanometers~120 nanometers.
13. semiconductor structure as claimed in claim 10, which is characterized in that the material of the separation layer includes:
Silica, silicon oxynitride or low-K dielectric material, K is less than 3.9.
14. semiconductor structure as claimed in claim 10, which is characterized in that firstth area and second area's substrate surface difference
With fin；Along substrate surface to the direction of fin top surface, the fin includes the 4th area, at the top of the 4th area
5th area and the 6th area at the top of the 5th area；The first doped region positioned at the 4th area fin bottom, described first
There are Doped ions in doped region；Positioned at the first conductive structure of the substrate surface and the first doped region side wall；Positioned at described
Gate structure of first conductive structure surfaces around the 5th area's fin；The second doped region in the 6th area's fin, institute
Stating has the Doped ions in the second doped region；Second positioned at the gate structure surface and the side wall of the second doped region leads
Electric structure.
15. semiconductor structure as claimed in claim 14, which is characterized in that firstth area is used to form N-type and vertically wraps entirely
Enclosing structure, secondth area are used to form the vertical all-around-gate structure of p-type；First doped region in firstth area and second is mixed
Doped ions in miscellaneous area are N-type ion；Doped ions in first doped region and the second doped region in secondth area are p-type
Ion.
16. semiconductor structure as claimed in claim 14, which is characterized in that the minimum of the fin side wall to separation layer side wall
Distance are as follows: 10 nanometers~60 nanometers.
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