US20170301776A1 - Methods of forming a gate structure on a vertical transistor device - Google Patents
Methods of forming a gate structure on a vertical transistor device Download PDFInfo
- Publication number
- US20170301776A1 US20170301776A1 US15/132,383 US201615132383A US2017301776A1 US 20170301776 A1 US20170301776 A1 US 20170301776A1 US 201615132383 A US201615132383 A US 201615132383A US 2017301776 A1 US2017301776 A1 US 2017301776A1
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- spacer
- sacrificial
- forming
- gate electrode
- innermost
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- 238000000034 method Methods 0.000 title claims abstract description 145
- 125000006850 spacer group Chemical group 0.000 claims abstract description 271
- 239000000463 material Substances 0.000 claims abstract description 81
- 239000004065 semiconductor Substances 0.000 claims abstract description 67
- 229910052751 metal Inorganic materials 0.000 claims abstract description 31
- 239000002184 metal Substances 0.000 claims abstract description 31
- 239000011810 insulating material Substances 0.000 claims abstract description 21
- 230000008569 process Effects 0.000 claims description 87
- 238000005530 etching Methods 0.000 claims description 53
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- 238000000151 deposition Methods 0.000 claims description 12
- 238000005137 deposition process Methods 0.000 claims description 11
- 239000004020 conductor Substances 0.000 claims description 9
- 238000005468 ion implantation Methods 0.000 claims description 7
- 239000000377 silicon dioxide Substances 0.000 claims description 6
- 235000012239 silicon dioxide Nutrition 0.000 claims description 6
- 230000008021 deposition Effects 0.000 claims description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 5
- 229920005591 polysilicon Polymers 0.000 claims description 5
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 5
- 229910052721 tungsten Inorganic materials 0.000 claims description 5
- 239000010937 tungsten Substances 0.000 claims description 5
- 229910000420 cerium oxide Inorganic materials 0.000 claims description 4
- 229910001092 metal group alloy Inorganic materials 0.000 claims description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 4
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 4
- BMMGVYCKOGBVEV-UHFFFAOYSA-N oxo(oxoceriooxy)cerium Chemical compound [Ce]=O.O=[Ce]=O BMMGVYCKOGBVEV-UHFFFAOYSA-N 0.000 claims description 4
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 claims description 4
- 229910001928 zirconium oxide Inorganic materials 0.000 claims description 4
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 3
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 2
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 claims description 2
- CSLZEOQUCAWYDO-UHFFFAOYSA-N [O-2].[Ti+4].[Ta+5] Chemical compound [O-2].[Ti+4].[Ta+5] CSLZEOQUCAWYDO-UHFFFAOYSA-N 0.000 claims description 2
- 229910052782 aluminium Inorganic materials 0.000 claims description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 2
- KQHQLIAOAVMAOW-UHFFFAOYSA-N hafnium(4+) oxygen(2-) zirconium(4+) Chemical compound [O--].[O--].[O--].[O--].[Zr+4].[Hf+4] KQHQLIAOAVMAOW-UHFFFAOYSA-N 0.000 claims description 2
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(iv) oxide Chemical compound O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 claims description 2
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 claims description 2
- 229910052759 nickel Inorganic materials 0.000 claims description 2
- -1 nickel nitride Chemical class 0.000 claims description 2
- 229910000480 nickel oxide Inorganic materials 0.000 claims description 2
- 239000010955 niobium Substances 0.000 claims description 2
- 229910000484 niobium oxide Inorganic materials 0.000 claims description 2
- URLJKFSTXLNXLG-UHFFFAOYSA-N niobium(5+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Nb+5].[Nb+5] URLJKFSTXLNXLG-UHFFFAOYSA-N 0.000 claims description 2
- 150000004767 nitrides Chemical class 0.000 claims description 2
- GNRSAWUEBMWBQH-UHFFFAOYSA-N oxonickel Chemical compound [Ni]=O GNRSAWUEBMWBQH-UHFFFAOYSA-N 0.000 claims description 2
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 claims description 2
- VEALVRVVWBQVSL-UHFFFAOYSA-N strontium titanate Chemical compound [Sr+2].[O-][Ti]([O-])=O VEALVRVVWBQVSL-UHFFFAOYSA-N 0.000 claims description 2
- 238000011112 process operation Methods 0.000 description 11
- 239000000758 substrate Substances 0.000 description 10
- 230000000873 masking effect Effects 0.000 description 7
- 238000012545 processing Methods 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 239000002019 doping agent Substances 0.000 description 6
- 238000009413 insulation Methods 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 5
- 125000004429 atom Chemical group 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000010276 construction Methods 0.000 description 3
- 239000007943 implant Substances 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 239000002210 silicon-based material Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 125000005843 halogen group Chemical group 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 239000002070 nanowire Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229920003209 poly(hydridosilsesquioxane) Polymers 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66666—Vertical transistors
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
-
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28079—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
-
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28088—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a composite, e.g. TiN
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823487—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66553—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using inside spacers, permanent or not
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823885—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
Definitions
- the present disclosure relates to the manufacture of semiconductor devices, and, more specifically, to various novel methods of forming a gate structure on a vertical transistor device.
- Transistors come in a variety of shapes and forms, e.g., planar transistors, FinFET transistors, nanowire devices, vertical transistors, etc.
- the transistors are typically either NMOS (NFET) or PMOS (PFET) type devices wherein the “N” and “P” designation is based upon the type of dopants used to create the source/drain regions of the devices.
- CMOS Complementary Metal Oxide Semiconductor
- CMOS Complementary Metal Oxide Semiconductor
- each device comprises drain and source regions and a gate electrode structure positioned above and between the source/drain regions.
- a gate electrode structure positioned above and between the source/drain regions.
- a conductive channel region forms between the drain region and the source region.
- FIG. 1A is a simplistic depiction of an illustrative prior art vertical transistor device 10 .
- the vertical transistor 10 comprises a generally vertically oriented channel semiconductor structure 12 A that extends upward from a front surface 12 S of a semiconductor substrate 12 .
- the semiconductor structure 12 A may have a variety of different configurations when viewed from above, e.g., circular, rectangular, square, etc.
- the device 10 further comprise a channel region 13 , a gate-all-around (GAA) gate structure 14 , a bottom source/drain (S/D) region 16 , a top S/D region 18 , a bottom spacer 15 B and a top spacer 15 T.
- GAA gate-all-around
- the gate structure 14 comprises a gate insulation layer 14 A and a conductive gate electrode 14 B.
- the materials of construction for the components of the device 10 may vary depending upon the particular application.
- the gate electrode structures of most transistor elements have comprised a plurality of silicon-based materials, such as a silicon dioxide and/or silicon oxynitride gate insulation layer, in combination with a polysilicon gate electrode.
- silicon-based materials such as a silicon dioxide and/or silicon oxynitride gate insulation layer
- many newer generation devices employ gate electrode stacks comprising alternative materials in an effort to avoid the short-channel effects which may be associated with the use of traditional silicon-based materials in reduced channel length transistors.
- gate electrode stacks comprising a so-called high-k dielectric/metal gate (HK/MG) configuration have been shown to provide significantly enhanced operational characteristics over the heretofore more commonly used silicon dioxide/polysilicon (SiO/poly) configurations.
- HK/MG high-k dielectric/metal gate
- gate last a so-called “dummy” or sacrificial gate structure is initially formed and remains in place as many process operations are performed to form the device, e.g., the formation of doped source/drain regions, performing an anneal process to repair damage to the substrate caused by the ion implantation processes and to activate the implanted dopant materials.
- the sacrificial gate structure is removed to define a gate cavity where the final HK/MG gate structure for the device is formed.
- FIGS. 1B-1F simplistically depict one illustrative prior art process flow that is employed to form replacement gate structures on vertical transistor devices.
- FIG. 1B depicts the device 10 after several process operations were performed. First, a plurality of the above-described vertically oriented channel semiconductor structures 12 A are formed above the substrate 12 . Thereafter, several layers of material were sequentially deposited above the substrate: a layer of spacer material for the bottom spacer 15 B, a sacrificial layer of material 21 (e.g., silicon dioxide) and a layer of spacer material for the top spacer 15 T. Also depicted in FIG. 1B is a patterned etch mask layer 23 .
- the patterned etch mask 23 may be made of a variety of different materials, e.g., photoresist, a combination of layers, etc.
- FIG. 1C depicts the device 10 after an etching process was performed through the patterned etch mask 23 to remove the exposed portions of the top spacer layer 15 T. The etching process stops on the sacrificial layer 21 .
- FIG. 1C depicts the device after the patterned etch mask 23 was removed.
- FIG. 1D depicts the device after a wet etching process was performed to remove the sacrificial layer 21 relative to the surrounding materials so as to define a plurality of replacement gate cavities 25 .
- FIG. 1E depicts the device 10 after simplistically depicted materials 14 for the replacement gate structure were formed so as to overfill the replacement gate cavities 25 .
- the materials 14 for the replacement gate structure would normally include a high-k gate insulation layer (not separately shown), one or more additional metal-containing layers (e.g., work function adjusting metal layers), such as titanium nitride, and a bulk conductive fill material, such as tungsten or polysilicon.
- the high-k insulation layer and the additional metal-containing layers are typically formed by performing a conformal deposition process.
- FIG. 1F depicts the device 10 after several process operations were performed.
- a chemical mechanical planarization (CMP) process was performed to planarize the upper surface of the gate materials 14 with the upper surface 15 S of the patterned top spacer layer 15 T.
- CMP chemical mechanical planarization
- anisotropic etching processes were performed to remove exposed portions of the gate materials 14 , wherein the etching process ultimately stops on the layer of bottom spacer material 15 B. As depicted, these operations result in the formation of separate GAA gate structures 14 that wrap around the channel portion 13 of the devices.
- the gate structures 14 are not self-aligned in that the lateral width 14 L of the gate structure 14 is approximately defined by the lateral width 15 L of the patterned features of the top spacer layer 15 T. Since these features are defined by a patterning process, e.g., masking and etching, the control of the exact size and exact positioning of these patterned features is subject to the problems generally encountered when defining features using patterning processes such as, for example, positional accuracy relative to other structures (like the structures 12 A), pattern transfer variations, etc. These types of issues are only expected to be more problematic as device dimensions continue to decrease with advancing technology.
- a patterning process e.g., masking and etching
- the present disclosure is directed to methods of forming a gate structure on a vertical transistor device that may solve or reduce one or more of the problems identified above.
- One illustrative method disclosed herein includes, among other things, forming a multi-layered sidewall spacer around a vertically oriented channel semiconductor structure, wherein the multi-layered sidewall spacer comprises a non-sacrificial innermost first spacer (a high-k insulating material), a sacrificial outermost spacer and at least one non-sacrificial second spacer (a metal-containing material) positioned between the innermost spacer and the outermost spacer, removing at least a portion of the sacrificial outermost spacer from the multi-layered sidewall spacer while leaving the at least one non-sacrificial second spacer and the non-sacrificial innermost first spacer in position, and forming a final conductive gate electrode in place of the removed sacrificial outermost spacer.
- Another illustrative method disclosed herein includes, among other things, forming a vertically oriented channel semiconductor structure, forming an initial multi-layered sidewall spacer around an entire perimeter of the vertically oriented channel semiconductor structure, wherein the initial multi-layered sidewall spacer has an initial height and comprises a non-sacrificial innermost first spacer comprised of a high-k insulating material, a sacrificial outermost spacer and at least one non-sacrificial second spacer comprised of a metal-containing material positioned between the non-sacrificial innermost first spacer and the sacrificial outermost spacer, and performing at least one recess etching process on the initial multi-layered sidewall spacer to thereby define a recessed multi-layered sidewall spacer having a recessed height that is less than the initial height of the initial multi-layered sidewall spacer.
- the method further includes performing at least one etching process to remove at least a portion of the sacrificial outermost spacer from the recessed multi-layered sidewall spacer while leaving the at least one non-sacrificial second spacer and the non-sacrificial innermost first spacer in position and thereby define a replacement gate electrode cavity and forming a final conductive gate electrode in the replacement gate electrode cavity.
- FIGS. 1A-1F simplistically depict an illustrative prior art vertical transistor device and a prior art method of forming a replacement gate structure on such a device
- FIGS. 2A-2S depict various illustrative novel methods disclosed herein for forming a gate structure on a vertical transistor device.
- the methods disclosed herein may be employed in manufacturing a variety of different devices, including, but not limited to, logic devices, memory devices, etc., and the devices may be may be either NMOS or PMOS devices.
- FIG. 2A depicts one illustrative embodiment of an integrated circuit product 100 disclosed herein at an early stage of fabrication wherein several process operations have already been performed.
- the product 100 will be formed in and above a substrate 102 .
- the substrate 102 may have a variety of configurations, such as the depicted bulk silicon configuration.
- the substrate 102 may also have a semiconductor-on-insulator (SOI) or a silicon-on-insulator configuration that includes a bulk silicon layer, a buried insulation layer (silicon dioxide) and an active layer (silicon), wherein semiconductor devices are formed in and above the active layer.
- SOI semiconductor-on-insulator
- the substrate 102 may be made of silicon or it may be made of materials other than silicon.
- the terms “substrate” or “semiconductor substrate” should be understood to cover all semiconducting materials and all forms of such materials.
- the product 100 is generally comprised of an N-type vertical transistor device 106 N and a P-type vertical transistor device 106 P.
- An illustrative isolation region 104 separates the two devices 106 N, 106 P.
- a vertically oriented channel semiconductor structure 108 has been formed for each of the devices 106 N, 106 P.
- the vertically oriented channel semiconductor structures 108 may have a variety of different configurations 108 C when viewed from above, e.g., circular, square, rectangular, etc., as indicated in FIG. 2A .
- the vertically oriented channel semiconductor structures 108 are defined by performing one or more etching processes through a patterned etch mask 109 .
- the vertically oriented channel semiconductor structures 108 are all of a uniform size and shape. However, such uniformity in the size and shape of the vertically oriented channel semiconductor structures 108 is not required to practice at least some aspects of the inventions disclosed herein.
- the vertically oriented channel semiconductor structures 108 are depicted as having been formed by performing an anisotropic etching process. In other cases, the vertically oriented channel semiconductor structures 108 may be formed in such a manner that they have a tapered cross-sectional configuration (wider at the bottom than at the top at this point in the process flow). Thus, the size and configuration of the vertically oriented channel semiconductor structures 108 and the manner in which they are made should not be considered a limitation of the present invention.
- bottom source/drain (S/D) regions 110 N, 110 P also depicted in FIG. 2A.
- a conductive liner 112 e.g., tungsten silicide
- a conductive metal layer 114 e.g., tungsten
- a bottom spacer layer 116 e.g., silicon nitride. All of the layers of material 112 , 114 and 116 are formed around the entire outer perimeter of the vertically oriented channel semiconductor structures 108 .
- the conductive liner 112 and the conductive metal layer 114 collectively constitute a bottom electrode for the devices 106 N, 106 P that may be used to conductively contact their respective bottom S/D regions 110 N, 110 P.
- the bottom S/D region 110 N comprises N-type dopant atoms
- the bottom S/D region 110 P comprises P-type dopant atoms
- they may be formed by performing one or more ion implantation processes through patterned implant masks (not shown).
- the implantation processes that are performed to form the bottom S/D regions 110 N, 110 P may be performed before or after the formation of the vertically oriented channel semiconductor structures 108 .
- the conductive liner 112 may be formed by performing a conformal deposition process and its thickness may vary depending upon the particular application.
- a recess etching process may be performed to remove portions of the conductive liner 112 from the sides of the vertically oriented channel semiconductor structures 108 and to recess the conductive metal layer 114 such that it has a recessed upper surface 114 S as depicted in FIG. 2A .
- the bottom spacer layer 116 was deposited and recessed such that it has a recessed upper surface 116 S as depicted in FIG. 2A .
- the height 108 H of the vertically oriented channel semiconductor structures 108 (above the upper surface 116 S of the bottom spacer layer 116 ) may vary depending upon the particular application.
- FIG. 2B depicts the product 100 after a non-sacrificial first sidewall spacer 161 was formed around the entire perimeter of each of the vertically oriented channel semiconductor structures 108 above the surface 116 S of the bottom spacer layer 116 .
- the spacers 161 are formed on and in contact with the outer surface or sidewall 108 X (which may have only a single sidewall if the vertically oriented channel semiconductor structures 108 have a generally circular configuration when viewed from above) of the vertically oriented channel semiconductor structures 108 .
- the spacers 161 are comprised of a high-k insulating material (k value of 10 or greater), such as zirconium oxide (ZrO 2 ), hafnium oxide (HfO 2 ), hafnium zirconium oxide (HfZrO x ), HfSiO x N y , niobium oxide (Nb x O y ), cerium oxide (CeO 2 ), tantalum oxide (Ta 2 O 5 ), titanium tantalum oxide (TiTa x O y ), strontium titanate (SrTiO 3 ) aluminum oxide (Al 2 O 3 ), lanthanum oxide (La 2 O 3 ), nickel oxide (Ni x O y ), titanium oxide (TiO 2 ), zinc oxide (ZnO), etc., and combinations of such materials.
- k value of 10 or greater such as zirconium oxide (ZrO 2 ), hafnium oxide (HfO 2 ), hafnium zircon
- the spacers 161 were formed by performing a first conformal deposition process to deposit a layer of spacer material and thereafter performing a first anisotropic etching process.
- the spacers 161 may be formed to any desired thickness.
- the spacer 161 may have a lateral width at the base of the spacer 161 (at the point where it contacts the upper surface 116 S of the bottom spacer layer 116 ) that falls within the range of about 2-8 nm.
- a portion of the spacer 161 will become the gate insulation layer for the final gate structure of the vertical device when the processing described herein is completed.
- FIG. 2C depicts the product 100 after a non-sacrificial second sidewall spacer 163 was formed adjacent the first sidewall spacer 161 above the surface 116 S of the bottom spacer layer 116 .
- the second sidewall spacer 163 was also formed around the entire perimeter of the vertically oriented channel semiconductor structures 108 .
- the spacers 163 are formed on and in contact with the outer surface of the first spacers 161 .
- the spacers 163 may be comprised of any of a variety of different metal-containing materials, e.g., a work function adjusting material, a substantially pure metal, a metal alloy, such as titanium nitride, nickel nitride, or a combination of electrically conductive metal nitrides, etc.
- the spacers 163 were formed by performing a second conformal deposition process to deposit a layer of spacer material and thereafter performing a second anisotropic etching process.
- the spacers 163 may be formed to any desired thickness.
- the spacer 163 may have a lateral width at the base of the spacer 163 (at the point where it contacts the upper surface 116 S of the bottom spacer layer 116 ) that falls within the range of about 2-8 nm.
- the materials of the spacers 163 need not be the same for both of the devices 106 N, 106 P in all applications, although such a situation may arise in some applications.
- Spacers 163 comprised of different materials may be formed on the devices 106 N, 106 P by use of appropriate masking layers to cover one of the devices while forming the spacer 163 on the exposed device. The use of such masking layers to allow processing of one device while masking another device is well known to those skilled in the art.
- spacer 163 will become part of the final gate structure of the vertical device when the processing described herein is completed.
- one or more additional non-sacrificial spacers may be formed adjacent the spacer 163 , i.e., an additional metal-containing spacer, depending upon the desired composition of the final gate structures for the devices 106 N, 106 P, which may be different.
- additional metal-containing spacers if present, need not be formed on both of the devices 106 N, 106 P, i.e., such additional metal-containing spacers may only be formed on one of the devices by using appropriate masking layers.
- FIG. 2D depicts the product 100 after a third sacrificial sidewall spacer 165 was formed adjacent the second sidewall spacer 163 above the surface 116 S of the bottom spacer layer 116 .
- the third sacrificial sidewall spacer 165 was also formed around the entire perimeter of the vertically oriented channel semiconductor structures 108 .
- the sacrificial spacers 165 are formed on and in contact with the outer surface of the second spacers 163 .
- one or more additional spacers may be formed between the second spacer 163 and the third sacrificial spacer 165 on at least one (and perhaps both) of the devices 106 N, 106 P.
- the spacers 165 are sacrificial in nature and will eventually be removed and replaced with a conductive material that will serve as part of the gate electrode for the final gate structures of the devices 106 N, 106 P.
- the sacrificial spacers 165 may be comprised of a variety of different materials, e.g., amorphous silicon, polysilicon, etc.
- the sacrificial spacers 165 were formed by performing a third conformal deposition process to deposit a layer of spacer material and thereafter performing a third anisotropic etching process.
- the sacrificial spacers 165 may be formed to any desired thickness.
- the sacrificial spacer 165 may have a lateral width at the base of the spacer 165 (at the point where it contacts the upper surface 116 S of the bottom spacer layer 116 ) that falls within the range of about 4-20 nm.
- the above-described steps were performed to define an initial multi-layered spacer 167 adjacent and around the entire perimeter of the vertically oriented channel semiconductor structures 108 wherein the initial multi-layered spacer 167 comprises an innermost non-sacrificial high-k insulating material (the first spacer 161 ), at least one non-sacrificial metal-containing layer (the second spacer 163 ) and an outermost sacrificial layer (the third spacer 165 ).
- the initial multi-layered spacer 167 was formed by performing a plurality, e.g., three, conformal deposition/anisotropic etching process sequences to form the initial multi-layered sidewall spacer 167 .
- the initial multi-layered spacer 167 has an initial height 167 H that is greater than the height 108 H (see FIG. 2A ) of the vertically oriented channel semiconductor structures 108 .
- the composition of the initial multi-layered spacer 167 is the same for both of the devices 106 N, 106 P, although, as noted above, that may not be the case in all applications.
- FIG. 2E depicts the product 100 after several process operations were performed.
- a layer of insulating material 169 e.g., a flowable oxide, silicon dioxide, etc.
- CMP chemical mechanical polishing
- the next major process operation involves removing portions of the spacers 161 , 163 and 165 , i.e., removing portions of the initial multi-layered spacer 167 , and removing the masking layer 109 .
- a variety of different process flows may be performed to remove the desired portions of the initial multi-layered spacer 167 , i.e., different layers may be removed in a different sequence than the illustrative example depicted herein.
- FIG. 2F depicts the product 100 after a recess etching process was performed to remove a portion of the sacrificial spacer 165 relative to surrounding materials and thereby define a recessed sacrificial spacer 165 R.
- the amount of the sacrificial spacer 165 that is removed may vary depending upon the particular application. In the depicted example, the recess etching process is performed until such time as an upper surface 165 S of the recessed sacrificial spacer 165 R is substantially co-planar with an upper surface 108 S of the vertically oriented channel semiconductor structures 108 .
- FIG. 2G depicts the product 100 after an etching process was performed to remove the entirety of the mask layer 109 relative to surrounding materials. This process operation results in the exposure of the upper surface 108 S of the vertically oriented channel semiconductor structures 108 .
- FIG. 2H depicts the product 100 after a recess etching process was performed to remove a portion of the second spacer 163 relative to surrounding materials and thereby define a recessed second spacer 163 R.
- the amount of the second spacer 163 that is removed may vary depending upon the particular application.
- the recess etching process is performed until such time as an upper surface 163 S of the recessed second spacer 163 R is substantially co-planar with the upper surface 108 S of the vertically oriented channel semiconductor structures 108 .
- FIG. 2I depicts the product 100 after a recess etching process was performed to remove a portion of the first spacer 161 relative to surrounding materials and thereby define a recessed first spacer 161 R.
- the amount of the first spacer 161 that is removed may vary depending upon the particular application.
- the recess etching process is performed until such time as an upper surface 161 S of the recessed first spacer 161 R is substantially co-planar with the upper surface 108 S of the vertically oriented channel semiconductor structures 108 .
- the removal of the masking layer 109 and the recessing of the spacers 161 , 163 and 165 may be performed in any desired order.
- the spacers 161 , 163 and 165 are all recessed to approximately the same height level, but such a situation is not required to practice at least some aspects of the presently disclosed inventions, i.e., the spacers 161 , 163 and 165 may be recessed to different height levels.
- the removal of the mask layer 109 and the recessing of the spacers 161 , 163 and 165 results in the definition of a recessed multi-layered spacer 167 R and the definition of a cavity 171 above the upper surface of the recessed multi-layered spacer 167 R and the upper surface 108 S of the vertically oriented channel semiconductor structure 108 that is surrounded by the insulating material 169 .
- the recessed multi-layered spacer 167 R has a recessed height 167 HR that is less than the initial height 167 H (see FIG. 2D ) of the initial multi-layered spacer 167 .
- the recessed height 167 HR may be about 30-80 nm less than the initial height 167 H.
- FIG. 2J depicts the product 100 after a sacrificial sidewall spacer 173 was formed within the cavities 171 above the recessed multi-layered spacer 167 R while leaving at least a portion of the upper surfaces 108 S of the vertically oriented channel semiconductor structures 108 exposed for further processing.
- the sacrificial sidewall spacer 173 may be sized such that substantially the entire upper surfaces 108 S of the vertically oriented channel semiconductor structures 108 will be exposed for further processing.
- the sacrificial sidewall spacer 173 was formed by depositing a layer of spacer material (e.g., silicon nitride, etc.) and thereafter performing an anisotropic etching process.
- spacer material e.g., silicon nitride, etc.
- the sacrificial sidewall spacer 173 may have a lateral width at the base of the sacrificial sidewall spacer 173 that is approximately equal to a lateral width of the upper surface of the recessed multi-layered spacer 167 R.
- FIG. 2K depicts the product 100 after several process operations were performed.
- an optional region of epi semiconductor material 142 was formed on the exposed upper surface 108 S of the vertically oriented channel semiconductor structures 108 by performing an epitaxial growth process.
- FIG. 2L depicts the product after a sacrificial plug material 175 was formed above the vertically oriented channel semiconductor structures 108 between the sacrificial sidewall spacers 173 .
- the purpose of the sacrificial plug material 175 is to protect the underlying vertically oriented channel semiconductor structures 108 during subsequent processing operations.
- the sacrificial plug material 175 should be made of a material that will remain in place when the sacrificial spacer 173 is removed as described more fully below.
- the sacrificial plug material 175 may be, for example, a spin-on glass material, OPL, etc.
- the sacrificial plug material 175 may be deposited so as to overfill the remaining un-filled portions of the cavities 171 and a CMP process may be performed so as to remove excess materials positioned above the upper surface of the insulating material 169 .
- FIG. 2M depicts the product 100 after an etching process was performed to remove the entirety of the sacrificial sidewall spacer 173 relative to surrounding materials. This process operation results in the exposure of perhaps the entirety of the upper surface 167 S (and at least the outermost spacer 165 R) of the recessed multi-layered spacer 167 R that was previously covered by the sacrificial spacer 173 .
- FIG. 2N depicts the product 100 after an etching process was performed to remove the entirety of the recessed sacrificial spacer 165 R relative to surrounding materials.
- this process operation results in the exposure of the non-sacrificial recessed second spacer 163 R, the bottom spacer layer 116 and in the definition of a replacement gate electrode cavity 177 between the insulating material 169 and the non-sacrificial second sidewall spacer 163 R.
- FIG. 2O depicts the product 100 after a conductive gate electrode 179 was formed in the replacement gate electrode cavity 177 .
- the gate electrode 179 was formed by depositing an appropriate conductive material, such as a metal, a metal alloy, tungsten, aluminum, etc., so as to overfill the replacement gate electrode cavity 177 and thereafter performing a CMP process to remove excess materials positioned above the upper surface of the layer of insulating material 169 .
- FIG. 2P depicts the product 100 after a recess etching process was performed to remove a portion of the conductive gate electrode 179 relative to surrounding materials and thereby define a final conductive gate electrode 179 F for both of the devices 106 N, 106 P.
- the amount of the conductive gate electrode 179 that is removed may vary depending upon the particular application.
- the recess etching process is performed until such time as an upper surface 179 R of the final conductive gate electrode 179 F is positioned slightly below (e.g., 4-20 nm) below the upper surface 108 S of the vertically oriented channel semiconductor structures 108 .
- the final conductive gate electrode 179 F (a conductive material), the non-sacrificial recessed second spacer 163 R (a metal-containing material), and the non-sacrificial recessed first spacer 161 R (a high-k insulating material) constitute the final gate structure 180 for each of the devices 106 N, 106 P.
- the final gate structures 180 for each of the devices 106 N, 106 P may be comprised of different materials.
- the final gate structures 180 for the devices 106 N, 106 P will include the same material for the high-k insulating material (the spacer 161 ) and the same material for the final conductive gate electrode 179 F.
- FIG. 2Q depicts the product after a gate cap 181 was formed above each of the final conductive gate electrodes 179 F in the remaining un-filled portions of the cavities 171 .
- the gate cap 181 may be made of a variety of different materials, e.g., a low-k material (k value of less than 5.5) and it should be made of a material that will remain in place when the sacrificial material 175 is removed as described more fully below.
- the gate cap 181 may be, for example, SiOCN, SiBCN, etc.
- the gate caps 181 may be formed by depositing a layer of gate cap material so as to overfill the remaining un-filled portions of the cavities 171 and thereafter performing a CMP process so as to remove excess materials positioned above the upper surface of the insulating material 169 .
- FIG. 2R depicts the product 100 after an etching process was performed to remove the entirety of the sacrificial material 175 relative to surrounding materials. In one embodiment, this process operation results in the exposure of the epi semiconductor materials 142 (in the depicted example).
- FIG. 2S depicts the product 100 after self-aligned upper S/D conductive contacts 144 N, 144 P were formed in the portion of the cavities 171 that are not occupied by the gate caps 181 .
- the self-aligned upper S/D conductive contacts 144 N, 144 P are conductively coupled to the top S/D regions 140 N, 140 P, respectively. Note that the self-aligned upper S/D conductive contacts 144 N, 144 P are self-aligned in that their configuration is defined by the remaining unfilled portion of the cavities 171 at the time the upper S/D conductive contacts 144 N, 144 P are formed.
- the self-aligned upper S/D contacts 144 N, 144 P physically contact the gate cap 181 within its associated cavity 171 .
- the upper S/D contacts 144 N, 144 P were formed by depositing an appropriate contact metal, such as tungsten, so as to overfill the cavities 171 above the epi semiconductor materials 142 (in the depicted example) and thereafter performing a CMP process to remove excess materials positioned above the upper surface of the layer of insulating material 169 .
- a metal silicide layer may be formed on the epi semiconductor materials 142 prior to depositing the contact metal.
- conductive contacts may be formed through the insulating material 169 so as to establish electrical contact to the bottom electrodes for the devices 106 N, 106 P (i.e., the conductive liner 112 and the conductive metal layer 114 ) that conductively contact their respective bottom S/D regions 110 N, 110 P.
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Abstract
Description
- Generally, the present disclosure relates to the manufacture of semiconductor devices, and, more specifically, to various novel methods of forming a gate structure on a vertical transistor device.
- In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially transistors, are provided on a restricted chip area. Transistors come in a variety of shapes and forms, e.g., planar transistors, FinFET transistors, nanowire devices, vertical transistors, etc. The transistors are typically either NMOS (NFET) or PMOS (PFET) type devices wherein the “N” and “P” designation is based upon the type of dopants used to create the source/drain regions of the devices. So-called CMOS (Complementary Metal Oxide Semiconductor) technology or products refers to integrated circuit products that are manufactured using both NMOS and PMOS transistor devices. Irrespective of the physical configuration of the transistor device, each device comprises drain and source regions and a gate electrode structure positioned above and between the source/drain regions. Upon application of an appropriate control voltage to the gate electrode, a conductive channel region forms between the drain region and the source region.
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FIG. 1A is a simplistic depiction of an illustrative prior artvertical transistor device 10. In general, thevertical transistor 10 comprises a generally vertically orientedchannel semiconductor structure 12A that extends upward from afront surface 12S of asemiconductor substrate 12. Thesemiconductor structure 12A may have a variety of different configurations when viewed from above, e.g., circular, rectangular, square, etc. Thedevice 10 further comprise achannel region 13, a gate-all-around (GAA)gate structure 14, a bottom source/drain (S/D)region 16, a top S/D region 18, abottom spacer 15B and atop spacer 15T. Also depicted is anillustrative bottom contact 20 that is conductively coupled to the bottom S/D region 16 and atop contact 22 that is conductively coupled to the top S/D region 18. In the depicted example, thegate structure 14 comprises agate insulation layer 14A and aconductive gate electrode 14B. The materials of construction for the components of thedevice 10 may vary depending upon the particular application. - For many early device technology generations, the gate electrode structures of most transistor elements have comprised a plurality of silicon-based materials, such as a silicon dioxide and/or silicon oxynitride gate insulation layer, in combination with a polysilicon gate electrode. However, as the channel length of aggressively scaled transistor elements has become increasingly smaller, many newer generation devices employ gate electrode stacks comprising alternative materials in an effort to avoid the short-channel effects which may be associated with the use of traditional silicon-based materials in reduced channel length transistors. For example, in some aggressively scaled transistor elements, gate electrode stacks comprising a so-called high-k dielectric/metal gate (HK/MG) configuration have been shown to provide significantly enhanced operational characteristics over the heretofore more commonly used silicon dioxide/polysilicon (SiO/poly) configurations.
- One well-known processing method that has been used for forming a transistor with a high-k/metal gate structure is the so-called “gate last” or “replacement gate” technique. In the replacement gate technique, a so-called “dummy” or sacrificial gate structure is initially formed and remains in place as many process operations are performed to form the device, e.g., the formation of doped source/drain regions, performing an anneal process to repair damage to the substrate caused by the ion implantation processes and to activate the implanted dopant materials. At some point in the process flow, the sacrificial gate structure is removed to define a gate cavity where the final HK/MG gate structure for the device is formed.
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FIGS. 1B-1F simplistically depict one illustrative prior art process flow that is employed to form replacement gate structures on vertical transistor devices.FIG. 1B depicts thedevice 10 after several process operations were performed. First, a plurality of the above-described vertically orientedchannel semiconductor structures 12A are formed above thesubstrate 12. Thereafter, several layers of material were sequentially deposited above the substrate: a layer of spacer material for thebottom spacer 15B, a sacrificial layer of material 21 (e.g., silicon dioxide) and a layer of spacer material for thetop spacer 15T. Also depicted inFIG. 1B is a patternedetch mask layer 23. The patternedetch mask 23 may be made of a variety of different materials, e.g., photoresist, a combination of layers, etc. -
FIG. 1C depicts thedevice 10 after an etching process was performed through the patternedetch mask 23 to remove the exposed portions of thetop spacer layer 15T. The etching process stops on thesacrificial layer 21.FIG. 1C depicts the device after the patternedetch mask 23 was removed. -
FIG. 1D depicts the device after a wet etching process was performed to remove thesacrificial layer 21 relative to the surrounding materials so as to define a plurality ofreplacement gate cavities 25. -
FIG. 1E depicts thedevice 10 after simplistically depictedmaterials 14 for the replacement gate structure were formed so as to overfill thereplacement gate cavities 25. Thematerials 14 for the replacement gate structure would normally include a high-k gate insulation layer (not separately shown), one or more additional metal-containing layers (e.g., work function adjusting metal layers), such as titanium nitride, and a bulk conductive fill material, such as tungsten or polysilicon. The high-k insulation layer and the additional metal-containing layers are typically formed by performing a conformal deposition process. -
FIG. 1F depicts thedevice 10 after several process operations were performed. First, a chemical mechanical planarization (CMP) process was performed to planarize the upper surface of thegate materials 14 with theupper surface 15S of the patternedtop spacer layer 15T. Thereafter, one or more anisotropic etching processes were performed to remove exposed portions of thegate materials 14, wherein the etching process ultimately stops on the layer ofbottom spacer material 15B. As depicted, these operations result in the formation of separateGAA gate structures 14 that wrap around thechannel portion 13 of the devices. Importantly, using this prior art process flow, thegate structures 14 are not self-aligned in that thelateral width 14L of thegate structure 14 is approximately defined by thelateral width 15L of the patterned features of thetop spacer layer 15T. Since these features are defined by a patterning process, e.g., masking and etching, the control of the exact size and exact positioning of these patterned features is subject to the problems generally encountered when defining features using patterning processes such as, for example, positional accuracy relative to other structures (like thestructures 12A), pattern transfer variations, etc. These types of issues are only expected to be more problematic as device dimensions continue to decrease with advancing technology. - The present disclosure is directed to methods of forming a gate structure on a vertical transistor device that may solve or reduce one or more of the problems identified above.
- The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an exhaustive overview of the invention. It is not intended to identify key or critical elements of the invention or to delineate the scope of the invention. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is discussed later.
- Generally, the present disclosure is directed to various novel methods of forming a gate structure on a vertical transistor device. One illustrative method disclosed herein includes, among other things, forming a multi-layered sidewall spacer around a vertically oriented channel semiconductor structure, wherein the multi-layered sidewall spacer comprises a non-sacrificial innermost first spacer (a high-k insulating material), a sacrificial outermost spacer and at least one non-sacrificial second spacer (a metal-containing material) positioned between the innermost spacer and the outermost spacer, removing at least a portion of the sacrificial outermost spacer from the multi-layered sidewall spacer while leaving the at least one non-sacrificial second spacer and the non-sacrificial innermost first spacer in position, and forming a final conductive gate electrode in place of the removed sacrificial outermost spacer.
- Another illustrative method disclosed herein includes, among other things, forming a vertically oriented channel semiconductor structure, forming an initial multi-layered sidewall spacer around an entire perimeter of the vertically oriented channel semiconductor structure, wherein the initial multi-layered sidewall spacer has an initial height and comprises a non-sacrificial innermost first spacer comprised of a high-k insulating material, a sacrificial outermost spacer and at least one non-sacrificial second spacer comprised of a metal-containing material positioned between the non-sacrificial innermost first spacer and the sacrificial outermost spacer, and performing at least one recess etching process on the initial multi-layered sidewall spacer to thereby define a recessed multi-layered sidewall spacer having a recessed height that is less than the initial height of the initial multi-layered sidewall spacer. In this example, the method further includes performing at least one etching process to remove at least a portion of the sacrificial outermost spacer from the recessed multi-layered sidewall spacer while leaving the at least one non-sacrificial second spacer and the non-sacrificial innermost first spacer in position and thereby define a replacement gate electrode cavity and forming a final conductive gate electrode in the replacement gate electrode cavity.
- The disclosure may be understood by reference to the following description taken in conjunction with the accompanying drawings, in which like reference numerals identify like elements, and in which:
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FIGS. 1A-1F simplistically depict an illustrative prior art vertical transistor device and a prior art method of forming a replacement gate structure on such a device; and -
FIGS. 2A-2S depict various illustrative novel methods disclosed herein for forming a gate structure on a vertical transistor device. - While the subject matter disclosed herein is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the invention to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.
- Various illustrative embodiments of the invention are described below. In the interest of clarity, not all features of an actual implementation are described in this specification. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure.
- The present subject matter will now be described with reference to the attached figures. Various structures, systems and devices are schematically depicted in the drawings for purposes of explanation only and so as to not obscure the present disclosure with details that are well known to those skilled in the art. Nevertheless, the attached drawings are included to describe and explain illustrative examples of the present disclosure. The words and phrases used herein should be understood and interpreted to have a meaning consistent with the understanding of those words and phrases by those skilled in the relevant art. No special definition of a term or phrase, i.e., a definition that is different from the ordinary and customary meaning as understood by those skilled in the art, is intended to be implied by consistent usage of the term or phrase herein. To the extent that a term or phrase is intended to have a special meaning, i.e., a meaning other than that understood by skilled artisans, such a special definition will be expressly set forth in the specification in a definitional manner that directly and unequivocally provides the special definition for the term or phrase. To the extent the term “adjacent” is used herein and in the attached claims to described a positional relationship between two components or structures, that term should be understood and construed so as to cover situations where there is actual physical contact between the two components and to cover situations where such components are positioned near one another but there is no physical contact between the two components. Physical contact between two components will be specified within the specification and claims by use of the phrase “on and in contact with” or other similar language. As will be readily apparent to those skilled in the art upon a complete reading of the present application, the methods disclosed herein may be employed in manufacturing a variety of different devices, including, but not limited to, logic devices, memory devices, etc., and the devices may be may be either NMOS or PMOS devices.
- As will be appreciated by those skilled in the art after a complete reading of the present application, various doped regions, e.g., halo implant regions, well regions and the like, are not depicted in the attached drawings. Of course, the inventions disclosed herein should not be considered to be limited to the illustrative examples depicted and described herein. The various components and structures of the
integrated circuit product 100 disclosed herein may be formed using a variety of different materials and by performing a variety of known techniques, e.g., a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, a thermal growth process, spin-coating techniques, etc. The thicknesses of these various layers of material may also vary depending upon the particular application. With reference to the attached figures, various illustrative embodiments of the methods and devices disclosed herein will now be described in more detail. -
FIG. 2A depicts one illustrative embodiment of anintegrated circuit product 100 disclosed herein at an early stage of fabrication wherein several process operations have already been performed. In general, theproduct 100 will be formed in and above asubstrate 102. Thesubstrate 102 may have a variety of configurations, such as the depicted bulk silicon configuration. Thesubstrate 102 may also have a semiconductor-on-insulator (SOI) or a silicon-on-insulator configuration that includes a bulk silicon layer, a buried insulation layer (silicon dioxide) and an active layer (silicon), wherein semiconductor devices are formed in and above the active layer. Thesubstrate 102 may be made of silicon or it may be made of materials other than silicon. Thus, the terms “substrate” or “semiconductor substrate” should be understood to cover all semiconducting materials and all forms of such materials. - With continuing reference to
FIG. 2A , theproduct 100 is generally comprised of an N-typevertical transistor device 106N and a P-typevertical transistor device 106P. Anillustrative isolation region 104 separates the twodevices channel semiconductor structure 108 has been formed for each of thedevices channel semiconductor structures 108 may have a variety ofdifferent configurations 108C when viewed from above, e.g., circular, square, rectangular, etc., as indicated inFIG. 2A . In the depicted example, the vertically orientedchannel semiconductor structures 108 are defined by performing one or more etching processes through a patternedetch mask 109. In the illustrative example depicted in the attached figures, the vertically orientedchannel semiconductor structures 108 are all of a uniform size and shape. However, such uniformity in the size and shape of the vertically orientedchannel semiconductor structures 108 is not required to practice at least some aspects of the inventions disclosed herein. In the example depicted herein, the vertically orientedchannel semiconductor structures 108 are depicted as having been formed by performing an anisotropic etching process. In other cases, the vertically orientedchannel semiconductor structures 108 may be formed in such a manner that they have a tapered cross-sectional configuration (wider at the bottom than at the top at this point in the process flow). Thus, the size and configuration of the vertically orientedchannel semiconductor structures 108 and the manner in which they are made should not be considered a limitation of the present invention. - Also depicted in
FIG. 2A are bottom source/drain (S/D)regions material channel semiconductor structures 108. Theconductive liner 112 and theconductive metal layer 114 collectively constitute a bottom electrode for thedevices D regions D region 110N comprises N-type dopant atoms, while the bottom S/D region 110P comprises P-type dopant atoms, and they may be formed by performing one or more ion implantation processes through patterned implant masks (not shown). The implantation processes that are performed to form the bottom S/D regions channel semiconductor structures 108. Theconductive liner 112 may be formed by performing a conformal deposition process and its thickness may vary depending upon the particular application. After the formation of themetal layer 114, a recess etching process may be performed to remove portions of theconductive liner 112 from the sides of the vertically orientedchannel semiconductor structures 108 and to recess theconductive metal layer 114 such that it has a recessedupper surface 114S as depicted inFIG. 2A . Thereafter, thebottom spacer layer 116 was deposited and recessed such that it has a recessedupper surface 116S as depicted inFIG. 2A . Theheight 108H of the vertically oriented channel semiconductor structures 108 (above theupper surface 116S of the bottom spacer layer 116) may vary depending upon the particular application. -
FIG. 2B depicts theproduct 100 after a non-sacrificialfirst sidewall spacer 161 was formed around the entire perimeter of each of the vertically orientedchannel semiconductor structures 108 above thesurface 116S of thebottom spacer layer 116. In the depicted example, thespacers 161 are formed on and in contact with the outer surface orsidewall 108X (which may have only a single sidewall if the vertically orientedchannel semiconductor structures 108 have a generally circular configuration when viewed from above) of the vertically orientedchannel semiconductor structures 108. Thespacers 161 are comprised of a high-k insulating material (k value of 10 or greater), such as zirconium oxide (ZrO2), hafnium oxide (HfO2), hafnium zirconium oxide (HfZrOx), HfSiOxNy, niobium oxide (NbxOy), cerium oxide (CeO2), tantalum oxide (Ta2O5), titanium tantalum oxide (TiTaxOy), strontium titanate (SrTiO3) aluminum oxide (Al2O3), lanthanum oxide (La2O3), nickel oxide (NixOy), titanium oxide (TiO2), zinc oxide (ZnO), etc., and combinations of such materials. Thespacers 161 were formed by performing a first conformal deposition process to deposit a layer of spacer material and thereafter performing a first anisotropic etching process. Thespacers 161 may be formed to any desired thickness. In one illustrative embodiment, thespacer 161 may have a lateral width at the base of the spacer 161 (at the point where it contacts theupper surface 116S of the bottom spacer layer 116) that falls within the range of about 2-8 nm. As will be appreciated by those skilled in the art after a complete reading of the present application, a portion of thespacer 161 will become the gate insulation layer for the final gate structure of the vertical device when the processing described herein is completed. -
FIG. 2C depicts theproduct 100 after a non-sacrificialsecond sidewall spacer 163 was formed adjacent thefirst sidewall spacer 161 above thesurface 116S of thebottom spacer layer 116. Thesecond sidewall spacer 163 was also formed around the entire perimeter of the vertically orientedchannel semiconductor structures 108. In the depicted example, thespacers 163 are formed on and in contact with the outer surface of thefirst spacers 161. Thespacers 163 may be comprised of any of a variety of different metal-containing materials, e.g., a work function adjusting material, a substantially pure metal, a metal alloy, such as titanium nitride, nickel nitride, or a combination of electrically conductive metal nitrides, etc. Thespacers 163 were formed by performing a second conformal deposition process to deposit a layer of spacer material and thereafter performing a second anisotropic etching process. Thespacers 163 may be formed to any desired thickness. In one illustrative embodiment, thespacer 163 may have a lateral width at the base of the spacer 163 (at the point where it contacts theupper surface 116S of the bottom spacer layer 116) that falls within the range of about 2-8 nm. The materials of thespacers 163 need not be the same for both of thedevices Spacers 163 comprised of different materials may be formed on thedevices spacer 163 on the exposed device. The use of such masking layers to allow processing of one device while masking another device is well known to those skilled in the art. As will be appreciated by those skilled in the art after a complete reading of the present application, a portion of thespacer 163 will become part of the final gate structure of the vertical device when the processing described herein is completed. Although not depicted, at this point, one or more additional non-sacrificial spacers may be formed adjacent thespacer 163, i.e., an additional metal-containing spacer, depending upon the desired composition of the final gate structures for thedevices devices -
FIG. 2D depicts theproduct 100 after a thirdsacrificial sidewall spacer 165 was formed adjacent thesecond sidewall spacer 163 above thesurface 116S of thebottom spacer layer 116. The thirdsacrificial sidewall spacer 165 was also formed around the entire perimeter of the vertically orientedchannel semiconductor structures 108. In the depicted example, thesacrificial spacers 165 are formed on and in contact with the outer surface of thesecond spacers 163. However, as noted above, in at least some applications, one or more additional spacers (not shown) may be formed between thesecond spacer 163 and the thirdsacrificial spacer 165 on at least one (and perhaps both) of thedevices spacers 165 are sacrificial in nature and will eventually be removed and replaced with a conductive material that will serve as part of the gate electrode for the final gate structures of thedevices sacrificial spacers 165 may be comprised of a variety of different materials, e.g., amorphous silicon, polysilicon, etc. Thesacrificial spacers 165 were formed by performing a third conformal deposition process to deposit a layer of spacer material and thereafter performing a third anisotropic etching process. Thesacrificial spacers 165 may be formed to any desired thickness. In one illustrative embodiment, thesacrificial spacer 165 may have a lateral width at the base of the spacer 165 (at the point where it contacts theupper surface 116S of the bottom spacer layer 116) that falls within the range of about 4-20 nm. - As will be appreciated by those skilled in the art after a complete reading of the present application, at this point in the process flow, the above-described steps were performed to define an initial
multi-layered spacer 167 adjacent and around the entire perimeter of the vertically orientedchannel semiconductor structures 108 wherein the initialmulti-layered spacer 167 comprises an innermost non-sacrificial high-k insulating material (the first spacer 161), at least one non-sacrificial metal-containing layer (the second spacer 163) and an outermost sacrificial layer (the third spacer 165). That is, the initialmulti-layered spacer 167 was formed by performing a plurality, e.g., three, conformal deposition/anisotropic etching process sequences to form the initialmulti-layered sidewall spacer 167. At this point in the process flow, the initialmulti-layered spacer 167 has aninitial height 167H that is greater than theheight 108H (seeFIG. 2A ) of the vertically orientedchannel semiconductor structures 108. In the depicted example, the composition of the initialmulti-layered spacer 167 is the same for both of thedevices -
FIG. 2E depicts theproduct 100 after several process operations were performed. First, a layer of insulatingmaterial 169, e.g., a flowable oxide, silicon dioxide, etc., was formed above theproduct 100. Thereafter, at least one chemical mechanical polishing (CMP) process was performed to planarize the upper surface of the insulatingmaterial 169 with theupper surface 109S of the patternedhard mask layer 109. - The next major process operation involves removing portions of the
spacers multi-layered spacer 167, and removing themasking layer 109. A variety of different process flows may be performed to remove the desired portions of the initialmulti-layered spacer 167, i.e., different layers may be removed in a different sequence than the illustrative example depicted herein.FIG. 2F depicts theproduct 100 after a recess etching process was performed to remove a portion of thesacrificial spacer 165 relative to surrounding materials and thereby define a recessedsacrificial spacer 165R. The amount of thesacrificial spacer 165 that is removed may vary depending upon the particular application. In the depicted example, the recess etching process is performed until such time as anupper surface 165S of the recessedsacrificial spacer 165R is substantially co-planar with anupper surface 108S of the vertically orientedchannel semiconductor structures 108. -
FIG. 2G depicts theproduct 100 after an etching process was performed to remove the entirety of themask layer 109 relative to surrounding materials. This process operation results in the exposure of theupper surface 108S of the vertically orientedchannel semiconductor structures 108. -
FIG. 2H depicts theproduct 100 after a recess etching process was performed to remove a portion of thesecond spacer 163 relative to surrounding materials and thereby define a recessedsecond spacer 163R. The amount of thesecond spacer 163 that is removed may vary depending upon the particular application. In the depicted example, the recess etching process is performed until such time as anupper surface 163S of the recessedsecond spacer 163R is substantially co-planar with theupper surface 108S of the vertically orientedchannel semiconductor structures 108. -
FIG. 2I depicts theproduct 100 after a recess etching process was performed to remove a portion of thefirst spacer 161 relative to surrounding materials and thereby define a recessedfirst spacer 161R. The amount of thefirst spacer 161 that is removed may vary depending upon the particular application. In the depicted example, the recess etching process is performed until such time as anupper surface 161S of the recessedfirst spacer 161R is substantially co-planar with theupper surface 108S of the vertically orientedchannel semiconductor structures 108. Depending upon the materials of construction, the removal of themasking layer 109 and the recessing of thespacers spacers spacers mask layer 109 and the recessing of thespacers multi-layered spacer 167R and the definition of acavity 171 above the upper surface of the recessedmulti-layered spacer 167R and theupper surface 108S of the vertically orientedchannel semiconductor structure 108 that is surrounded by the insulatingmaterial 169. The recessedmulti-layered spacer 167R has a recessed height 167HR that is less than theinitial height 167H (seeFIG. 2D ) of the initialmulti-layered spacer 167. In one illustrative embodiment, the recessed height 167HR may be about 30-80 nm less than theinitial height 167H. -
FIG. 2J depicts theproduct 100 after asacrificial sidewall spacer 173 was formed within thecavities 171 above the recessedmulti-layered spacer 167R while leaving at least a portion of theupper surfaces 108S of the vertically orientedchannel semiconductor structures 108 exposed for further processing. In some applications, thesacrificial sidewall spacer 173 may be sized such that substantially the entireupper surfaces 108S of the vertically orientedchannel semiconductor structures 108 will be exposed for further processing. Thesacrificial sidewall spacer 173 was formed by depositing a layer of spacer material (e.g., silicon nitride, etc.) and thereafter performing an anisotropic etching process. In one illustrative embodiment, thesacrificial sidewall spacer 173 may have a lateral width at the base of thesacrificial sidewall spacer 173 that is approximately equal to a lateral width of the upper surface of the recessedmulti-layered spacer 167R. -
FIG. 2K depicts theproduct 100 after several process operations were performed. First, a top S/D region 140N (comprising N-type dopant atoms) and a top S/D region 140P (comprising P-type dopant atoms) were formed in the vertically orientedchannel semiconductor structures 108 by performing one or more ion implantation processes through patterned implant masks (not shown) and through an opening defined by thesacrificial sidewall spacer 173. Then, an optional region ofepi semiconductor material 142 was formed on the exposedupper surface 108S of the vertically orientedchannel semiconductor structures 108 by performing an epitaxial growth process. -
FIG. 2L depicts the product after asacrificial plug material 175 was formed above the vertically orientedchannel semiconductor structures 108 between thesacrificial sidewall spacers 173. The purpose of thesacrificial plug material 175 is to protect the underlying vertically orientedchannel semiconductor structures 108 during subsequent processing operations. Thesacrificial plug material 175 should be made of a material that will remain in place when thesacrificial spacer 173 is removed as described more fully below. In one illustrative embodiment, thesacrificial plug material 175 may be, for example, a spin-on glass material, OPL, etc. Thesacrificial plug material 175 may be deposited so as to overfill the remaining un-filled portions of thecavities 171 and a CMP process may be performed so as to remove excess materials positioned above the upper surface of the insulatingmaterial 169. -
FIG. 2M depicts theproduct 100 after an etching process was performed to remove the entirety of thesacrificial sidewall spacer 173 relative to surrounding materials. This process operation results in the exposure of perhaps the entirety of theupper surface 167S (and at least theoutermost spacer 165R) of the recessedmulti-layered spacer 167R that was previously covered by thesacrificial spacer 173. -
FIG. 2N depicts theproduct 100 after an etching process was performed to remove the entirety of the recessedsacrificial spacer 165R relative to surrounding materials. In one embodiment, this process operation results in the exposure of the non-sacrificial recessedsecond spacer 163R, thebottom spacer layer 116 and in the definition of a replacementgate electrode cavity 177 between the insulatingmaterial 169 and the non-sacrificialsecond sidewall spacer 163R. In some applications, it may not be necessary to remove the entirety of the recessedsacrificial spacer 165R and expose thebottom spacer layer 116, i.e., a small portion of the recessedsacrificial spacer 165R may remain in the bottom of the replacementgate electrode cavity 177. -
FIG. 2O depicts theproduct 100 after aconductive gate electrode 179 was formed in the replacementgate electrode cavity 177. Thegate electrode 179 was formed by depositing an appropriate conductive material, such as a metal, a metal alloy, tungsten, aluminum, etc., so as to overfill the replacementgate electrode cavity 177 and thereafter performing a CMP process to remove excess materials positioned above the upper surface of the layer of insulatingmaterial 169. -
FIG. 2P depicts theproduct 100 after a recess etching process was performed to remove a portion of theconductive gate electrode 179 relative to surrounding materials and thereby define a finalconductive gate electrode 179F for both of thedevices conductive gate electrode 179 that is removed may vary depending upon the particular application. In the depicted example, the recess etching process is performed until such time as anupper surface 179R of the finalconductive gate electrode 179F is positioned slightly below (e.g., 4-20 nm) below theupper surface 108S of the vertically orientedchannel semiconductor structures 108. Collectively, in the example depicted herein, the finalconductive gate electrode 179F (a conductive material), the non-sacrificial recessedsecond spacer 163R (a metal-containing material), and the non-sacrificial recessedfirst spacer 161R (a high-k insulating material) constitute thefinal gate structure 180 for each of thedevices final gate structures 180 for each of thedevices final gate structures 180 for thedevices conductive gate electrode 179F. -
FIG. 2Q depicts the product after agate cap 181 was formed above each of the finalconductive gate electrodes 179F in the remaining un-filled portions of thecavities 171. Thegate cap 181 may be made of a variety of different materials, e.g., a low-k material (k value of less than 5.5) and it should be made of a material that will remain in place when thesacrificial material 175 is removed as described more fully below. In one illustrative embodiment, thegate cap 181 may be, for example, SiOCN, SiBCN, etc. The gate caps 181 may be formed by depositing a layer of gate cap material so as to overfill the remaining un-filled portions of thecavities 171 and thereafter performing a CMP process so as to remove excess materials positioned above the upper surface of the insulatingmaterial 169. -
FIG. 2R depicts theproduct 100 after an etching process was performed to remove the entirety of thesacrificial material 175 relative to surrounding materials. In one embodiment, this process operation results in the exposure of the epi semiconductor materials 142 (in the depicted example). -
FIG. 2S depicts theproduct 100 after self-aligned upper S/Dconductive contacts cavities 171 that are not occupied by the gate caps 181. The self-aligned upper S/Dconductive contacts D regions conductive contacts cavities 171 at the time the upper S/Dconductive contacts D contacts gate cap 181 within its associatedcavity 171. The upper S/D contacts cavities 171 above the epi semiconductor materials 142 (in the depicted example) and thereafter performing a CMP process to remove excess materials positioned above the upper surface of the layer of insulatingmaterial 169. Additionally, although not separately depicted, a metal silicide layer (not shown) may be formed on theepi semiconductor materials 142 prior to depositing the contact metal. - At the point of processing depicted in
FIG. 2S , additional manufacturing processes may be performed to complete the fabrication of the device. For example, conductive contacts (not shown) may be formed through the insulatingmaterial 169 so as to establish electrical contact to the bottom electrodes for thedevices conductive liner 112 and the conductive metal layer 114) that conductively contact their respective bottom S/D regions - The particular embodiments disclosed above are illustrative only, as the invention may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein. For example, the process steps set forth above may be performed in a different order. Furthermore, no limitations are intended to the details of construction or design herein shown, other than as described in the claims below. It is therefore evident that the particular embodiments disclosed above may be altered or modified and all such variations are considered within the scope and spirit of the invention. Note that the use of terms, such as “first,” “second,” “third” or “fourth” to describe various processes or structures in this specification and in the attached claims is only used as a shorthand reference to such steps/structures and does not necessarily imply that such steps/structures are performed/formed in that ordered sequence. Of course, depending upon the exact claim language, an ordered sequence of such processes may or may not be required. Accordingly, the protection sought herein is as set forth in the claims below.
Claims (30)
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CN110610864A (en) * | 2018-06-15 | 2019-12-24 | 三星电子株式会社 | Method of forming vertical field effect transistor device |
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