CN110120418B

CN110120418B - Vertical nanowire transistor and method of forming the same

Info

Publication number: CN110120418B
Application number: CN201910375145.2A
Authority: CN
Inventors: 周华
Original assignee: ICLeague Technology Co Ltd
Current assignee: ICLeague Technology Co Ltd
Priority date: 2019-05-07
Filing date: 2019-05-07
Publication date: 2023-03-24
Anticipated expiration: 2039-05-07
Also published as: CN110120418A

Abstract

A vertical nanowire transistor and a method of forming the same. The forming method comprises the following steps: providing a substrate, wherein the surface of the substrate is provided with a plurality of channel columns, the channel columns are perpendicular to the surface of the substrate, the channel columns are provided with a plurality of first channel columns and a plurality of second channel columns, the first channel columns and the second channel columns are used for forming transistors of a first conduction type, the first channel columns are provided with first channel regions, and the second channel columns are provided with second channel regions; forming a first gate dielectric layer on the surface of the side wall of the first channel region of the first channel column; forming a second gate dielectric layer on the surface of the side wall of the second channel region of the second channel column; forming a first work function structure on the surface of the first gate dielectric layer; and forming a second work function structure on the surface of the second gate dielectric layer, wherein the work function of the second work function structure is different from that of the first work function structure. The vertical nanowire transistor formed has multiple threshold voltages.

Description

Vertical nanowire transistor and method of forming the same

Technical Field

The invention relates to the technical field of semiconductor manufacturing, in particular to a vertical nanowire transistor and a forming method thereof.

Background

With the rapid development of semiconductor manufacturing technology, semiconductor devices are being developed toward higher element density and higher integration. As the transistor is currently widely used as the most basic semiconductor device, as the element density and the integration degree of the semiconductor device are improved, the gate size of the planar transistor is shorter and shorter, and the conventional planar transistor has weak control capability on channel current, generates a short channel effect, generates leakage current, and finally affects the electrical performance of the semiconductor device.

In order to overcome the short channel effect of the transistor and suppress the leakage current, the prior art proposes a vertical nanowire transistor, such as a fully-wrapped-gate vertical nanowire transistor. The fully-surrounding gate nanowire transistor can well inhibit short-channel effects, has higher integration level compared with a two-dimensional planar transistor, and can effectively inhibit corner effects due to the fully-surrounding gate structure, so that the gate has better control capability, and the gate electrode can better form electrostatic control on a channel region from multiple directions.

However, for vertical nanowire transistors, the difficulty of forming multi-threshold voltage transistors increases.

Disclosure of Invention

The invention solves the problem of providing a vertical nanowire transistor and a forming method thereof, which are used for forming the vertical nanowire transistor with multiple threshold voltages.

To solve the above problems, the present invention provides a method for forming a vertical nanowire transistor, comprising: providing a substrate, wherein the surface of the substrate is provided with a plurality of channel columns, the channel columns are perpendicular to the surface of the substrate, the channel columns are provided with a plurality of first channel columns and a plurality of second channel columns, the first channel columns and the second channel columns are used for forming transistors of a first conduction type, the first channel columns are provided with first channel regions, and the second channel columns are provided with second channel regions; forming a first gate dielectric layer on the surface of the side wall of the first channel region of the first channel column; forming a second gate dielectric layer on the surface of the side wall of the second channel region of the second channel column; forming a first work function structure on the surface of the first gate dielectric layer; forming a second work function structure on the surface of the second gate dielectric layer, wherein the work function of the second work function structure is different from that of the first work function structure; forming a first gate layer on the surface of the first work function structure; and forming a second gate layer on the surface of the second work function structure.

Optionally, the first conductive type transistor is a P-type transistor; the first channel column is used for forming a first P-type transistor; the second channel column is used for forming a second P-type transistor, and the threshold voltage of the second P-type transistor is larger than that of the first P-type transistor.

Optionally, the first work function structure includes: the first work function layer and the second work function layer are positioned on the surface of the first work function layer; the second work function structure comprises a first work function layer; the first work function layer is made of a P-type work function material; the material of the second work function layer is a P-type work function material.

Optionally, the material of the first work function layer is the same as or different from the material of the second work function layer; the first work function layer is made of TiN or TaN; the second work function layer is made of TiN or TaN.

Optionally, the thickness of the first work function layer is 8 angstroms to 12 angstroms; the thickness of the second work function layer is 13-18 angstroms.

Optionally, when the material of the second work function layer is TiN, the threshold voltage of the second P-type transistor is increased by 80 mv to 120 mv compared with the threshold voltage of the first P-type transistor every time the thickness of the second work function layer is increased by 10 angstroms.

Optionally, the first work function structure and the second work function structure are both single-layer structures, the first work function structure and the second work function structure are made of the same material, and the thickness of the first work function structure is greater than that of the second work function structure; the first work function structure and the second work function structure are made of TiN or TaN.

Optionally, when the material of the first work function structure and the material of the second work function structure are TiN, the threshold voltage of the second N-type transistor is reduced by 80 mv to 120 mv compared with the threshold voltage of the first N-type transistor when the thickness of the second work function structure is increased by 10 angstroms compared with the thickness of the first work function structure.

Optionally, the plurality of channel pillars further include a plurality of third channel pillars and a plurality of fourth channel pillars, where the third channel pillars and the fourth channel pillars are used to form a transistor of a second conductivity type, the third channel pillars have third channel regions therein, and the fourth channel pillars have fourth channel regions therein; the forming method further comprises: forming a third gate dielectric layer on the surface of the side wall of the third channel region of the third channel column; forming a fourth gate dielectric layer on the surface of the side wall of the fourth channel region of the fourth channel column; forming a third work function structure on the surface of the third gate dielectric layer; forming a fourth work function structure on the surface of the fourth gate dielectric layer, wherein the work function of the fourth work function structure is different from that of the third work function structure; forming a third gate layer on the surface of the third work function structure; and forming a fourth gate layer on the surface of the fourth work function structure.

Optionally, the second conductivity type transistor is an N-type transistor; the third channel column is used for forming a first N-type transistor; the fourth channel column is used for forming a second N-type transistor, and the threshold voltage of the second N-type transistor is larger than that of the first N-type transistor.

Optionally, the fourth work function structure includes: a third work function layer; the third work function layer is made of a P-type work function layer material.

Optionally, the first work function structure includes: the first work function layer, the second work function layer positioned on the surface of the first work function layer and the third work function layer positioned on the surface of the second work function layer; the second work function structure comprises a first work function layer and a third work function layer positioned on the surface of the first work function layer; the first work function layer is made of a P-type work function material; the material of the second work function layer is a P-type work function material.

Optionally, the third work function layer is made of TiN or TaN; the thickness of the third work function layer is 8-12 angstroms.

Optionally, when the material of the third work function layer is TiN, for each 10 angstroms increase in thickness of the third work function layer, the threshold voltage of the second N-type transistor is increased by 18 mv to 22 mv compared with the threshold voltage of the first N-type transistor.

Optionally, the third work function structure includes: a fourth work function layer; the fourth work function structure includes: a fourth work function layer located on a surface of the third work function layer; the fourth work function layer is made of an N-type work function material; the N-type work function material comprises TiAl.

Optionally, the first conductive type transistor is an N-type transistor; the first channel pillar is used for forming a first N-type transistor; the second channel pillar is used for forming a second N-type transistor, and the threshold voltage of the second N-type transistor is larger than that of the first N-type transistor.

Optionally, the first work function structure includes: the first work function layer and the second work function layer are positioned on the surface of the first work function layer; the second work function structure includes a first work function layer. The material of the first work function layer is an N-type work function material; the material of the second work function layer is an N-type work function material.

Optionally, the material of the first work function layer is TiAl; the material of the second work function layer is TiAl; the thickness of the first work function layer is 8-12 angstroms; the thickness of the second work function layer is 13-18 angstroms.

Optionally, when the material of the second work function layer is TiAl, the threshold voltage of the second N-type transistor is increased by 80 mv to 120 mv compared with the threshold voltage of the first N-type transistor for every 10 angstroms increase in the thickness of the second work function layer.

Optionally, the plurality of channel pillars further include a plurality of third channel pillars and a plurality of fourth channel pillars, where the third channel pillars and the fourth channel pillars are used to form a transistor of a second conductivity type, the third channel pillars have third channel regions therein, and the fourth channel pillars have fourth channel regions therein; the forming method further includes: forming a third gate dielectric layer on the surface of the side wall of the third channel region of the third channel column; forming a fourth gate dielectric layer on the surface of the side wall of the fourth channel region of the fourth channel column; forming a third work function structure on the surface of the third gate dielectric layer; forming a fourth work function structure on the surface of the fourth gate dielectric layer, wherein the work function of the fourth work function structure is different from that of the third work function structure; forming a third gate layer on the surface of the third work function structure; and forming a fourth gate layer on the surface of the fourth work function structure.

Optionally, the second conductivity type transistor is a P-type transistor; the third channel column is used for forming a first P-type transistor; the fourth channel column is used for forming a second P-type transistor, and the threshold voltage of the second P-type transistor is different from the threshold voltage of the first P-type transistor.

Optionally, before forming the third gate dielectric layer and the fourth gate dielectric layer, the method further includes: respectively forming third doped regions in the third channel column and the fourth channel column, wherein the third doped regions are respectively positioned at the bottom of the third channel region and the bottom of the fourth channel region; and forming fourth doped regions in the third channel column and the fourth channel column respectively, wherein the fourth doped regions are positioned at the top of the third channel region and the top of the fourth channel region respectively, and the conductivity types of the third doped region and the fourth doped region are the same.

Optionally, before forming the first gate dielectric layer and the second gate dielectric layer, the method further includes: respectively forming first doped regions in the first channel column and the second channel column, wherein the first doped regions are respectively positioned at the bottom of the first channel region and the bottom of the second channel region; and respectively forming second doped regions in the first channel column and the second channel column, wherein the second doped regions are respectively positioned at the top of the first channel region and the top of the second channel region, and the conductivity types of the first doped region and the second doped region are the same.

Optionally, the method for forming the first doped region includes: forming a first mask layer on the substrate and on the side wall surfaces of the channel columns, wherein the first mask layer exposes partial side wall surfaces of the bottoms of the first channel columns, and the first mask layer exposes partial side wall surfaces of the bottoms of the second channel columns; and doping in the first channel column and the second channel column by taking the first mask layer as a mask to form a first doped region.

Optionally, the forming method of the second doped region includes: forming a second mask layer on the substrate, wherein the second mask layer exposes the top surface of the first channel column and the top surface of the second channel column; and doping in the first channel column and the second channel column by taking the second mask layer as a mask to form a second doped region.

Optionally, before forming the first gate dielectric layer and the second gate dielectric layer, the method further includes: forming a first dielectric layer on the substrate, wherein the first dielectric layer surrounds the plurality of channel columns; the first conducting layer is arranged on the surface of the first dielectric layer, surrounds the plurality of channel columns and is positioned on the surface of the side wall of the first doped region; forming a second dielectric layer on the surface of the first conductive layer; the first gate dielectric layer is also positioned on the surface of the second dielectric layer; the second gate dielectric layer is also positioned on the surface of the second dielectric layer.

Optionally, before forming the first gate dielectric layer and the second gate dielectric layer, the method further includes: forming a sacrificial layer on the surface of the second dielectric layer, wherein the surface of the sacrificial layer is lower than the top surfaces of the channel columns, the sacrificial layer surrounds the channel columns, and the sacrificial layer is located on the side wall of the first channel region and the side wall of the second channel region; forming a third dielectric layer on the surface of the sacrificial layer, wherein the third dielectric layer surrounds the channel columns, is positioned on the exposed side wall surfaces of the channel columns, and is exposed out of part of the sacrificial layer; removing the sacrificial layer, and forming a gate opening exposed between the third dielectric layer and the second dielectric layer, wherein the gate opening exposes the side wall of the first channel region and the side wall of the second channel region; forming a first gate dielectric layer on the surface of the side wall of the first channel region exposed by the gate opening; and forming a second gate dielectric layer on the surface of the side wall of the second channel region exposed by the gate opening.

Optionally, the method further includes: and forming a fourth dielectric layer on the surface of the first grid layer and the surface of the second grid layer, wherein the fourth dielectric layer is also positioned on the surface of the side wall of the third dielectric layer.

Optionally, the method further includes: and forming a barrier layer on the surfaces of the first gate dielectric layer and the second gate dielectric layer before forming the first work function structure and the second work function structure.

Optionally, the method further includes: and forming a stop layer on the surface of the barrier layer.

Optionally, the material of the stop layer is different from the material of the contacted first work function structure surface, and the material of the stop layer is different from the material of the contacted second work function structure surface.

Optionally, the material of the stop layer is TaN.

Optionally, the barrier layer is made of TiN or TaN.

Optionally, before forming the first gate layer, forming a first capping layer on a surface of the first work function structure; and forming a second covering layer on the surface of the second work function structure before forming the second gate layer.

Optionally, the material of the first capping layer comprises TaN or TiN; the material of the second capping layer comprises TaN or TiN.

The method of forming a vertical nanowire transistor of claim 1, wherein the perimeter of the channel pillar is between 30 nanometers and 40 nanometers.

Optionally, the size of the first gate layer in a direction perpendicular to the substrate surface is 28 nm to 32 nm; the size of the second gate layer in the direction vertical to the surface of the substrate is 28-32 nm.

Optionally, the materials of the first gate dielectric layer and the second gate dielectric layer include high-K dielectric materials; the material of the first gate layer and the second gate layer comprises a metal.

Correspondingly, the invention also provides a vertical nanowire transistor formed by adopting the method, which comprises the following steps: the transistor array substrate comprises a substrate, a plurality of channel columns and a plurality of first and second control units, wherein the surface of the substrate is provided with the plurality of channel columns, the plurality of channel columns are perpendicular to the surface of the substrate, the plurality of channel columns are provided with a plurality of first channel columns and a plurality of second channel columns, the first channel columns and the second channel columns are used for forming transistors of a first conduction type, first channel regions are arranged in the first channel columns, and second channel regions are arranged in the second channel columns; the first gate dielectric layer is positioned on the surface of the side wall of the first channel region of the first channel column; the second gate dielectric layer is positioned on the surface of the side wall of the second channel region of the second channel column; the first work function structure is positioned on the surface of the first gate dielectric layer; the second work function structure is positioned on the surface of the second gate dielectric layer, and the work function of the second work function structure is different from that of the first work function structure; a first gate layer on a surface of the first work function structure; a second gate layer on a surface of the second work function structure.

Compared with the prior art, the technical scheme of the invention has the following advantages:

in the forming method of the technical scheme of the invention, the first channel column and the second channel column are used for forming the first conductive type transistor, the first work function structure formed on the side wall of the first channel column and the second work function structure formed on the side wall of the second channel column are used for forming the second work function structure, and the work functions of the first work function structure and the second work function structure are different, so that the threshold voltage of the first conductive type transistor formed by the first channel column is different from the threshold voltage of the first conductive type transistor formed by the second channel column. Thus, the threshold voltage of the first conductivity type transistor formed by the first channel pillar can be adjusted by adjusting the material or thickness of the first work function structure; accordingly, the threshold voltage of the first conductivity type transistor formed by the second channel pillar can be adjusted by adjusting the material or thickness of the second work function structure. Accordingly, the process difficulty of forming the multi-threshold voltage vertical nanowire transistor is reduced.

In the structure of the technical scheme of the invention, the work functions of the first work function structure and the second work function structure are different. Specifically, the threshold voltage of the first conductivity type transistor formed by the first channel column can be adjusted by adjusting the material or the thickness of the first work function structure; accordingly, the threshold voltage of the first conductivity type transistor formed by the second channel pillar can be adjusted by adjusting the material or thickness of the second work function structure. Accordingly, the threshold voltage of the first conductivity type transistor formed by the first channel column can be made different from the threshold voltage of the first conductivity type transistor formed by the second channel column.

Drawings

Fig. 1 to 13 are schematic cross-sectional views illustrating a process of forming a vertical nanowire transistor according to an embodiment of the present invention;

fig. 14 to 22 are schematic cross-sectional views illustrating a vertical nanowire transistor according to another embodiment of the present disclosure.

Detailed Description

As described in the background, the difficulty of forming vertical nanowire transistors with multiple threshold voltages is greater in the prior art.

Research shows that in the embodiment of a planar transistor or a fin field effect transistor, the threshold voltage of the transistor can be adjusted by ion implantation in the channel region of the transistor. However, for the vertical nanowire transistor, since the channel length direction in the transistor is perpendicular to the substrate surface, the difficulty of adjusting the threshold voltage by using the conventional ion implantation process is large, and it is difficult to perform ion implantation on the channel region of the vertical nanowire transistor in the direction parallel to the substrate surface.

In order to solve the above problems, the present invention provides a vertical nanowire transistor. The transistors of the first conductivity type having different threshold voltages are formed by forming a first work function layer on the sidewall of the first trench pillar, forming a second work function layer on the sidewall of the second trench pillar, and the work function of the second work function structure is different from that of the first work function structure.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

It should be noted that, in the embodiments of the present invention, the term "surface" is used to indicate a positional relationship between different structures, and does not limit that direct contact between the structures is required.

Fig. 1 to 13 are schematic cross-sectional views illustrating a process of forming a vertical nanowire transistor according to an embodiment of the present invention.

Referring to fig. 1 and 2, fig. 2 is a schematic cross-sectional view along the direction AA' of fig. 1, a substrate 100 is provided, a surface of the substrate 100 has a plurality of channel pillars 110, the channel pillars 110 are perpendicular to the surface of the substrate 100, the channel pillars 110 have a plurality of first channel pillars 111 and a plurality of second channel pillars 112, the first channel pillars 111 and the second channel pillars 112 are used for forming a transistor of a first conductivity type, the first channel pillars 111 have a first channel region 121 therein, and the second channel pillars 112 have a second channel region 122 therein.

The plurality of channel pillars 110 are used for vertical nanowire transistors having a channel length direction perpendicular to the surface of the substrate, thereby reducing a space area occupied by each transistor to thereby improve the integration of the transistor.

In this embodiment, the method for forming the substrate 110 and the channel pillar 111 includes: providing an initial substrate; forming a plurality of first patterning layers 101 which are separated from each other on the surface of the initial substrate, wherein the first patterning layers 101 define corresponding positions and shapes of the plurality of channel columns 110; and etching the initial substrate by taking the first patterning layer 101 as a mask to form the substrate 100 and a plurality of channel columns 110 positioned on the surface of the substrate 100.

The initial substrate is a planar base; the initial substrate is a silicon substrate, a silicon germanium substrate, a silicon carbide substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, a glass substrate, or a III-V compound substrate (e.g., silicon nitride or gallium arsenide, etc.).

And the process for etching the initial substrate is an anisotropic dry etching process.

In this embodiment, the first patterning layer 101 is a single-layer structure; the first patterning layer 101 is made of silicon nitride; in other embodiments, the material of the single-layer structured first patterned layer 101 can also be silicon oxide, silicon oxynitride, amorphous carbon, or silicon carbide.

In another embodiment, the first patterning layer 101 is a stacked structure, and the stacking direction of the stacked structure is perpendicular to the surface of the substrate 100; the material of the laminated structure comprises one or more of silicon oxide, silicon oxynitride, amorphous carbon and silicon carbide.

The method for forming the first patterned layer 101 includes: forming an initial first patterned layer 101 on the initial substrate surface; forming a patterned photoresist layer on the surface of the first patterned layer 101, wherein the patterned photoresist layer defines corresponding positions and shapes of the plurality of channel pillars; and etching the initial first patterning layer by taking the patterned photoresist layer as a mask until the surface of the initial substrate is exposed to form the first patterning layer.

The process of etching the initial first patterned layer is an anisotropic dry etching process.

In other embodiments, the first patterned layer can also be a patterned photoresist layer.

In this embodiment, the first conductive type transistor is a P-type transistor; the first channel pillar 111 is used for forming a first P-type transistor; the second channel pillar 112 is used to form a second P-type transistor having a threshold voltage greater than that of the first P-type transistor.

The number of the first channel pillars 111 is 1 or more; the number of the second channel pillars 112 is 1 or more.

In another embodiment, the first conductivity type transistor is an N-type transistor; the first channel pillar 111 is used to form a first N-type transistor; the second channel pillar 112 is used to form a second N-type transistor having a threshold voltage greater than that of the first N-type transistor.

The circumference of each channel pillar 110 is 30 nm to 40 nm. The perimeter of the channel pillar 110 determines the channel width (channel width) of the vertical nanowire transistor formed. And the channel width determines the channel current magnitude of the vertical nanowire transistor; on one hand, the perimeter is not suitable to be too large, otherwise, the area occupied by the channel column is too large, and microminiaturization and integration of the device are not easy to realize; on the other hand, if the circumference is not suitable to be too small, otherwise the channel width of the vertical nanowire transistor is too small, the channel current of the vertical nanowire transistor is too small, the performance of the device is easily reduced, and the formed transistor is easily subjected to short channel effect or electric leakage.

In this embodiment, the trench pillar 110 is a cylinder, and the top dimension of the trench pillar 110 is smaller than the bottom dimension; the perimeter range of the top of the channel column 111 is 30-35 nanometers, and the diameter range of the top of the channel column 111 is 10-12 nanometers; the perimeter of the bottom of the channel column 111 is 35-40 nanometers, and the diameter of the bottom of the channel column 111 is 11-14 nanometers.

In another embodiment, the size of the top of the channel pillar 110 is the same as the size of the bottom, the circumference of the channel pillar 111 is 35 nm to 40 nm, and the diameter of the channel pillar 111 is in a range of 11 nm to 14 nm.

In this embodiment, before the subsequent formation of the first dielectric layer, a well region (not shown) is further formed in the substrate 100 around the channel pillar 110 and in the substrate 100 at the bottom of the channel pillar 110. Since the first channel pillar 111 and the second channel pillar 112 in this embodiment are used to form a P-type transistor, the well regions located in the substrate 100 around the first channel pillar 111, the substrate 100 around the second channel pillar 112, and the substrate 100 at the bottom of the first channel pillar 111 and the second channel pillar 112 are N-type.

The forming process of the well region is an ion implantation process.

In an embodiment, before forming the well region, forming a protective layer on the substrate surface, the sidewalls of the channel pillar 110, and the top of the channel pillar. The protective layer serves to protect the substrate 100 and the channel pillars 110 during an ion implantation process for forming the well region. The protective layer is of a single-layer structure or a laminated structure; the protective layer is made of one or more of silicon oxide, silicon nitride and silicon oxynitride.

Referring to fig. 3, fig. 3 is a cross-sectional view of fig. 2, wherein a first dielectric layer 102 is formed on the substrate 100, and the first dielectric layer 102 surrounds the plurality of channel pillars 110; after the first dielectric layer 102 is formed, first doped regions 104 are respectively formed in the first channel column 111 and the second channel column 112, and the first doped regions 104 are respectively located at the bottom of the first channel region 121 and the bottom of the second channel region 122.

The first dielectric layer 102 is used for electrical isolation between a subsequently formed first conductive layer and the substrate 100. The material of the first dielectric layer 102 includes one or more of silicon oxide, silicon oxynitride, low-k dielectric material (dielectric constant less than 3.9) and ultra-low-k dielectric material (dielectric constant less than 2.5).

The first doped region 104 is used as a source or a drain of a transistor of the first conductivity type formed by the first channel pillar 111 and the second channel pillar 112. In this embodiment, the first doped region 104 is used as a drain.

In this embodiment, the first conductive type transistor is a P-type transistor, and the doped ions in the first doped region 104 are P-type ions; the P-type ions include boron ions or indium ions. In other embodiments, the first conductive type transistor is an N-type transistor, and the doped ions in the first doped region 104 are N-type ions, which include phosphorus ions or arsenic ions.

In this embodiment, the method for forming the first doped region 104 includes: forming a first mask layer 103 on the substrate 100 and on the sidewall surfaces of the plurality of channel pillars 110, where the first mask layer 103 exposes a portion of the sidewall surface of the bottom of the first channel pillar 111, and the first mask layer 103 exposes a portion of the sidewall surface of the bottom of the second channel pillar 112; forming a first mask layer 103 on the substrate 100 and on the sidewall surfaces of the plurality of channel pillars 110, where the first mask layer 103 exposes a portion of the sidewall surface of the bottom of the first channel pillar 111, and the first mask layer 103 exposes a portion of the sidewall surface of the bottom of the second channel pillar 112; and doping in the first channel column 111 and the second channel column 112 by using the first mask layer 103 as a mask to form a first doped region.

In this embodiment, the method for forming the first mask layer 103 includes: before forming the first dielectric layer 102, forming an initial first mask layer on the surface of the substrate 100 and on the sidewalls and the top of the trench pillar 110; forming an initial first dielectric layer on the surface of the initial first mask layer, wherein the surface of the initial first dielectric layer is lower than the top of the channel column 110; forming a second patterning layer on the side wall and the top of the channel column 110 on the initial first dielectric layer, wherein the second patterning layer is positioned on the surface of the initial first mask layer; thinning the initial first dielectric layer to form the first dielectric layer 102, and exposing a part of the initial first mask layer between the first dielectric layer 102 and the second patterning layer; etching the initial first mask layer until the surfaces of the side walls of the plurality of channel pillars 110 are exposed by using the second patterning layer and the first dielectric layer 102 as masks to form the first mask layer 103; after the first mask layer 103 is formed, the second patterning layer is removed.

The material of the first mask layer 103 includes: one or more combinations of silicon oxide, silicon nitride and silicon oxynitride. In this embodiment, the first mask layer 103 includes a silicon oxide layer on the surface of the trench pillar 110 and a silicon nitride layer on the surface of the silicon oxide layer. The formation process of the initial first mask layer 103 is a chemical vapor deposition process or an atomic layer deposition process.

The forming method of the initial first dielectric layer comprises the following steps: forming a first medium material film on the surface of the initial first mask layer, wherein the surface of the first medium material film is higher than the top of the channel column 110; and after the first medium material film is flattened, etching the first medium material film back to form the initial first medium layer.

And the process for thinning the initial first dielectric layer is an anisotropic dry etching process, an isotropic dry etching process or a wet etching process.

The process of doping the first doped region in the first channel column 111 and the second channel column 112 includes an ion implantation process or a solid source doping process.

In this embodiment, the first doped region 104 includes a first lightly doped region and a first source/drain doped region; the doping concentration in the first lightly doped region is less than that in the first source-drain doping region.

Referring to fig. 4, a first conductive layer 105 is formed on the surface of the first dielectric layer 102, the first conductive layer 102 surrounds the channel pillars 110, and the first conductive layer 105 is located on the sidewall surface of the first doped region 104.

The first conductive layer 105 is used to electrically connect with the first doped region 104. The material of the first conductive layer comprises a metal; the material of the first conductive layer comprises one or more of copper, tungsten, aluminum, titanium nitride or tantalum nitride.

In this embodiment, the first conductive layer 105 includes a first barrier layer located on the sidewall of the channel pillar 110 and the surface of the first dielectric layer 102, and a first conductive material layer located on the surface of the first barrier layer. The first barrier layer is made of one or two of titanium nitride and tantalum nitride; the material of the first conductive material layer is copper, tungsten or aluminum.

The method for forming the first conductive layer 105 includes: forming a first barrier material film on the surface of the first dielectric layer 102 and on the sidewalls and the top of the channel pillar 110; forming a first conductive material film on the surface of the first barrier material film; and etching to remove the first conductive material film and the first barrier material film on the side wall and the top of the channel column 110, and forming the first conductive material layer and the first barrier layer.

Referring to fig. 5, a second dielectric layer 106 is formed on the surface of the first conductive layer 105; forming a sacrificial layer 107 on the surface of the second dielectric layer 106, wherein the surface of the sacrificial layer 107 is lower than the top surfaces of the channel pillars 110, the sacrificial layer 107 surrounds the channel pillars 110 (as shown in fig. 1), and the sacrificial layer 107 is located on the sidewalls of the first channel region 121 and the second channel region 122; an initial third dielectric layer 108 is formed on the surface of the sacrificial layer 107, and the initial third dielectric layer 108 surrounds the plurality of channel pillars 110.

The second dielectric layer 106 is used for electrical isolation between a subsequently formed first gate layer and the first conductive layer 105. The material of the second dielectric layer 106 includes one or more of silicon oxide, silicon oxynitride, low-k dielectric material (dielectric constant less than 3.9) and ultra-low-k dielectric material (dielectric constant less than 2.5). The forming process of the second dielectric layer 106 includes a deposition process, a planarization process after the deposition process, and a back etching process after the planarization process.

The sacrificial layer 107 is used to occupy a spatial position for the first and second gate layers to be formed subsequently, and to define a position of the initial third dielectric layer 108 to be formed subsequently. The material of the sacrificial layer 107 is different from the material of the second dielectric layer 106 or the initial third dielectric layer 108 formed later. The material of the sacrificial layer 107 includes one or more of silicon oxide, silicon oxynitride, amorphous carbon, low-k dielectric material (dielectric constant less than 3.9) and ultra-low-k dielectric material (dielectric constant less than 2.5). The forming process of the sacrificial layer 107 includes a deposition process, a planarization process after the deposition process, and a back etching process after the planarization process.

The material of the initial third dielectric layer 108 includes one or more combinations of silicon oxide, silicon oxynitride, low-k dielectric materials (dielectric constant less than 3.9), and ultra-low-k dielectric materials (dielectric constant less than 2.5). The formation process of the initial third dielectric layer 108 includes a deposition process, a planarization process after the deposition process, and a back etching process after the planarization process.

In this embodiment, after the initial third dielectric layer 108 is formed, the first patterning layer 101 is etched away.

Referring to fig. 6, after the initial third dielectric layer 108 is formed, second doped regions 109 are respectively formed in the first channel pillar 111 and the second channel pillar 112, the second doped regions 109 are respectively located on the top of the first channel region 121 and the top of the second channel region 122, and the first doped region 104 and the second doped region 109 have the same conductivity type.

The second doped region 109 is used as a source or a drain of a transistor of the first conductivity type formed by the first channel pillar 111 and the second channel pillar 112. In this embodiment, the second doped region 109 is used as a source.

In this embodiment, the first conductive type transistor is a P-type transistor, and the doped ions in the second doped region 109 are P-type ions; the P-type ions include boron ions or indium ions. In other embodiments, the first conductive type transistor is an N-type transistor, and the doped ions in the second doped region 109 are N-type ions, which include phosphorus ions or arsenic ions.

The method for forming the second doped region 109 comprises the following steps: forming a second mask layer 113 on the substrate 100, wherein the second mask layer 113 exposes the top surface of the first channel pillar 111 and the top surface of the second channel pillar 112; and doping in the first channel column 121 and the second channel column 122 by using the second mask layer 113 as a mask to form a second doped region 109.

In this embodiment, the process of forming the second doped region 109 is an ion implantation process.

In this embodiment, the second doped region 109 includes a second lightly doped region and a second source/drain doped region; the doping concentration in the second lightly doped region is less than that in the second source-drain doping region.

In this embodiment, the second mask layer 113 is located on the surface of the initial third dielectric layer 108.

The method for forming the second mask layer 113 includes: forming an initial second mask layer on the surface of the initial third dielectric layer 108 and the top surface of the channel pillar 110; removing a portion of the initial second mask layer, and exposing the top surface of the first channel pillar 111 and the top surface of the second channel pillar 112 to form the second mask layer 113.

The material of the second mask layer 113 includes one or more of silicon oxide, silicon nitride, and silicon oxynitride.

After the second doped region 109 is formed, the second mask layer 113 is removed.

Referring to fig. 7, after the second doped region 109 is formed, a portion of the initial third dielectric layer 108 is removed and a portion of the sacrificial layer 107 is exposed, and a third dielectric layer 114 is formed on the exposed sidewall surfaces of the plurality of channel pillars 110.

The dimension of the third dielectric layer 114 perpendicular to the surface of the sidewall of the trench pillar determines the gate height (gate height) of the subsequently formed first gate layer and the second gate layer.

The forming method of the third dielectric layer 114 includes: forming a plurality of third patterned layers on the surface of the initial third dielectric layer 108 (as shown in fig. 6), where each third patterned layer is located on the top surface of one channel pillar 110 and a portion of the surface of the initial third dielectric layer 108 around the channel pillar 110; and etching the initial third dielectric layer 108 by using the patterning layer as a mask until the surface of the sacrificial layer 107 is exposed, so as to form the third dielectric layer 114.

The material of the third patterned layer comprises one or more of silicon oxide, silicon nitride and silicon oxynitride photoresist materials.

Referring to fig. 8, the sacrificial layer 107 is removed (as shown in fig. 7), a gate opening 115 is formed between the third dielectric layer 114 and the second dielectric layer 106, and the gate opening 115 exposes sidewalls of the first channel region 121 and sidewalls of the second channel region 122.

The process of removing the sacrificial layer 107 includes an isotropic dry etching process or a wet etching process.

The gate opening 115 is used to form a gate structure.

Referring to fig. 9, a first gate dielectric layer 116 is formed on the sidewall surface of the first channel region 121 of the first channel pillar 111; a second gate dielectric layer 117 is formed on a sidewall surface of the second channel region 122 of the second channel pillar 112.

In this embodiment, the first gate dielectric layer 116 and the second gate dielectric layer 117 are formed simultaneously. The first gate dielectric layer 116 is also located on the surface of the second dielectric layer 106; the second gate dielectric layer 117 is also positioned on the surface of the second dielectric layer 106; the first gate dielectric layer 116 and the second gate dielectric layer 117 are also located on the surface of the third dielectric layer 114.

Forming the first gate dielectric layer 116 on the sidewall surface of the first channel region 121 exposed by the gate opening 115; the second gate dielectric layer 117 is formed on the sidewall surface of the second channel region 122 exposed by the gate opening 115.

The first gate dielectric layer 116 is made of a high-k dielectric material (the dielectric constant is greater than 3.9); material of second gate dielectric layer 117Is a high k dielectric material. The high-k dielectric material comprises La ₂ O ₃ 、Al ₂ O ₃ 、BaZrO、HfZrO ₄ 、HfZrON、HfLaO、HfSiO、HfSiON、LaSiO、AlSiO、HfTaO、HfTiO、(Ba,Sr)TiO ₃ Or Si ₃ N ₄ . The thickness of the first gate dielectric layer 116 and the second gate dielectric layer 117 is

The forming process of the first gate dielectric layer 116 and the second gate dielectric layer 117 includes a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

In this embodiment, before forming the first gate dielectric layer 116 and the second gate dielectric layer 117, forming an oxide layer on the sidewall surface of the first channel region 121 and the sidewall surface of the second channel region 122 exposed by the gate opening 115; the first gate dielectric layer 116 and the second gate dielectric layer 117 are located on the surface of the oxide layer.

Referring to fig. 10 and 11, fig. 11 is an enlarged partial cross-sectional view of a region a and a region B in fig. 10, wherein a first work function structure 118 is formed on a surface of the first gate dielectric layer 116; a second work function structure 119 is formed on the surface of the second gate dielectric layer 117, and the work function of the second work function structure 119 is different from that of the first work function structure 118.

In this embodiment, the first type transistor is a P-type transistor. The first work function structure 118 includes: a first work function layer 131 and a second work function layer 132 on the surface of the first work function layer 131; the second work function structure 119 comprises a first work function layer 131; the first work function layer 131 is made of a P-type work function material; the material of the second work function layer 132 is a P-type work function material.

The material of the first work function layer 131 is the same as or different from that of the second work function layer 132; the first work function layer 131 is made of TiN or TaN; the material of the second work function layer 132 is TiN or TaN. The forming process of the first work function layer 131 and the second work function layer 132 includes an atomic layer deposition process; the ald process has good step coverage and is beneficial to forming the first work function layer 131 and the second work function layer 132 with uniform thickness in the gate opening 115.

In an embodiment, the forming process of the first work function layer 131 or the second work function layer 132 can further include a doping process; the doping process comprises an ion implantation process or a solid source doping process; the doping process is used to dope work function adjusting ions including P-type work function ions (e.g., ti ions or Ta ions) or N-type work function ions (e.g., al ions) into the first work function layer 131 or the second work function layer 132.

Since the TiN or TaN is a P-type work function material and the total thickness of the first work function structure 118 is greater than the total thickness of the second work function structure 119, the threshold voltage of the first P-type transistor is less than the threshold voltage of the second P-type transistor.

In this embodiment, the material of the first work function layer 131 and the second work function layer 132 is TiN, and the threshold voltage of the first P-type transistor and the second P-type transistor is adjusted by adjusting the thickness of the first work function layer 131 and the second work function layer 132. In other embodiments, the materials of the first work function layer 131 and the second work function layer 132 can also be different.

Since the first work function layer 131 and the second work function layer 132 are made of the same material, the first work function layer 131 and the second work function layer 132 can be formed by the same forming process. Under the condition that the size of the vertical nanowire transistor to be formed is reduced and the integration degree is improved, the thicknesses of the first work function layer 131 and the second work function layer 132 are easier to control, so that the method for adjusting the threshold voltages of the first P-type transistor and the second P-type transistor is simpler and the control of the threshold voltages is more precise.

Specifically, when the material of the second work function layer is TiN, the threshold voltage of the second P-type transistor is increased by 80 mv to 120 mv compared with the threshold voltage of the first P-type transistor every time the thickness of the second work function layer is increased by 10 angstroms. .

In this embodiment, the thickness of the first work function layer 131 ranges from 8 angstroms to 12 angstroms; the thickness of the second work function layer 132 ranges from 13 angstroms to 18 angstroms.

In this embodiment, the method for forming the first work function structure and the second work function structure includes: forming a first work function layer 131 on the surface of the first gate dielectric layer 116 and the surface of the second gate dielectric layer 117; forming an initial second work function layer on the surface of the first work function layer 131; forming a fourth patterning layer on the surface of the initial second work function layer, wherein the fourth patterning layer exposes the initial second work function layer on the top and the sidewall of the second channel pillar 112; and etching the initial second work function layer by using the fourth patterning layer as a mask until the first work function layer 131 is exposed, thereby forming the second work function layer 132.

In another embodiment, the first work function structure and the second work function structure are both single-layer structures, the first work function structure and the second work function structure are made of the same material, and the thickness of the first work function structure is larger than that of the second work function structure; the first work function structure and the second work function structure are made of TiN or TaN. The thickness range of the first work function structure is 8-28 angstroms; the second work function structure has a thickness in a range of 8 angstroms to 28 angstroms.

When the material of the first work function structure and the material of the second work function structure are TiN, the threshold voltage of the second N-type transistor is reduced by 18 mv to 22 mv, in an embodiment 20 mv, for every 10 angstroms of increase in the thickness of the second work function structure compared with the thickness of the first work function structure.

The forming process of the first work function structure and the second work function structure comprises an atomic layer deposition process; the atomic layer deposition process has good step coverage capability and is beneficial to forming a first work function structure and a second work function structure with uniform thickness in the gate opening 115.

The process of forming the first and second work function structures can further include a doping process; the doping process comprises an ion implantation process or a solid source doping process; the doping process is used for doping work function adjusting ions into the first work function structure and the second work function structure.

In other embodiments, the first and second work function structures are different materials, and the thickness of the first work function structure is the same as or different than the thickness of the second work function structure.

In another embodiment, the first type transistor is an N-type transistor. The first work function structure includes: the second work function layer is positioned on the surface of the first work function layer; the second work function structure includes a first work function layer. The material of the first work function layer is an N-type work function material; the material of the second work function layer is an N-type work function material.

In one embodiment, the material of the first work function layer is TiAl; the material of the second work function layer is TiAl; the thickness of the first work function layer is 8-12 angstroms; the thickness of the second work function layer is 13-18 angstroms.

When the material of the second work function layer is TiAl, the threshold voltage of the second N-type transistor is reduced by 80-120 millivolts compared with the threshold voltage of the first N-type transistor when the thickness of the second work function layer is increased by 10 angstroms.

The forming process of the first work function layer and the second work function layer comprises an atomic layer deposition process. The forming process of the first work function layer or the second work function layer can further include a doping process; the doping process comprises an ion implantation process or a solid source doping process; the doping process is used for doping work function adjusting ions into the first work function layer or the second work function layer.

In other embodiments, when the first type of transistor is an N-type transistor, the materials of both the first and second work function structures can also be different, and the thickness of the first work function structure is the same as or different from the thickness of the second work function structure.

In this embodiment, before forming the first and second

work function structures

118 and 119, a barrier layer 133 is further formed on the surfaces of the first and second gate dielectric layers; a stop layer 134 is formed on the surface of the barrier layer 133.

The stop layer 134 is of a different material than the contacted first work function structure 118 and the stop layer 134 is of a different material than the contacted second work function structure 119. The stop layer is made of TaN; the barrier layer is made of TiN or TaN. The formation process of the barrier layer 133 includes an atomic layer deposition process; the forming process of the stop layer comprises an atomic layer deposition process.

In other embodiments, the stop layer can also not be formed.

Referring to fig. 12, a first gate layer 123 is formed on the surface of the first work function structure 118; a second gate layer 124 is formed on the surface of the second work function structure 119.

In this embodiment, the first gate layer 123 and the second gate layer 124 are formed simultaneously; the materials of the first gate layer and the second gate layer comprise metal; the metal comprises one or more of copper, tungsten and aluminum.

In the present embodiment, the size of the first gate layer 123 in the direction perpendicular to the substrate surface is 28 nm to 32 nm; the second gate layer 124 has a size of 28 nm to 32 nm in a direction perpendicular to the substrate surface.

The dimension of the first gate layer 123 in the direction perpendicular to the surface of the substrate 100, in combination with the perimeter of the first channel pillar 111, determines the channel area of the first P-type transistor, and the channel area, in combination with the thickness of the first work function structure 118, determines the controllability of the first work function structure 118 for carriers in the channel, and thus determines the threshold voltage of the first P-type transistor. Therefore, in combination with adjusting the size of the first gate layer 123 in the direction perpendicular to the surface of the substrate 100, the perimeter of the first channel pillar 111, and the thickness of the first work function structure 118, the threshold voltage of the first P-type transistor can be accurately adjusted.

Specifically, on one hand, the size of the first gate layer 123 in the direction perpendicular to the surface of the substrate 100 is not suitable to be too large, otherwise, the channel resistance is increased, which is not favorable for improving the carrier mobility; on the other hand, the dimension of the first gate layer 123 in the direction perpendicular to the surface of the substrate 100 is not too small, otherwise short channel effects are easily caused.

Accordingly, in combination with adjusting the dimension of the second gate layer 124 in the direction perpendicular to the surface of the substrate 100, the perimeter of the second channel pillar 112, and the thickness of the second work function structure 119, the threshold voltage of the second P-type transistor can be accurately adjusted.

In this embodiment, before forming the first gate layer 123, a first capping layer (not shown) is also formed on the surface of the first work function structure; a second capping layer (not shown) is formed on the second workfunction structure surface before forming the second gate layer 124. The first capping layer is used for blocking the material of the first gate layer 123 from diffusing into the first gate dielectric layer 116; the second capping layer is used to block diffusion of the material of the second gate layer 124 into the second gate dielectric layer 117.

The material of the first covering layer comprises TaN or TiN; the material of the second capping layer comprises TaN or TiN. In this embodiment, the first cover layer and the second cover layer are made of the same material, and the first cover layer and the second cover layer are formed simultaneously; the forming process of the first covering layer and the second covering layer comprises an atomic layer deposition process.

Referring to fig. 13, a fourth dielectric layer 125 is formed on the surface of the first gate layer 123 and the surface of the second gate layer 124, and the fourth dielectric layer 125 is further located on the sidewall surface of the third dielectric layer 114.

The fourth dielectric layer 125 is used for electrical isolation between a subsequently formed second conductive layer (not shown) and the first gate layer 123, and between the second conductive layer and the second gate layer 124. The material of the fourth dielectric layer 125 includes one or more of silicon oxide, silicon oxynitride, low-k dielectric material (dielectric constant less than 3.9) and ultra-low-k dielectric material (dielectric constant less than 2.5).

The forming method of the fourth dielectric layer 125 includes: forming a fourth dielectric material film on the surface of the first gate layer 123, the second gate layer 124, the third dielectric layer 114 and the top of the channel column 111, wherein the surface of the fourth dielectric material film is higher than the top of the channel column 110; and after the fourth medium material film is flattened, etching the fourth medium material film back to form the initial fourth medium layer.

In this embodiment, the surface of the fourth dielectric layer 125 is lower than the top surface of the trench pillar 110; simultaneously with or after etching back the fourth dielectric material film, part of the third dielectric layer 114 is etched, and part of the sidewall and the top surface of the second doped region 109 are exposed.

In an embodiment, after forming the fourth dielectric layer, forming a second conductive layer on the surface of the fourth dielectric layer 125 and the exposed surface of the second doped region 109 is further included. The second conductive layer is used for electrically connecting with the second doped region 109. The material of the second conductive layer includes a metal or a metal compound.

Accordingly, an embodiment of the present invention further provides a vertical nanowire transistor formed by the above method, with reference to fig. 13, including:

a substrate 100, a surface of the substrate 100 having a plurality of channel pillars, the plurality of channel pillars being perpendicular to the surface of the substrate 100, the plurality of channel pillars having a plurality of first channel pillars 111 and a plurality of second channel pillars 112, the first channel pillars 111 and the second channel pillars 112 being used to form a transistor of a first conductivity type, the first channel pillars 111 having first channel regions 121 therein, and the second channel pillars 112 having second channel regions 122 therein;

a first gate dielectric layer 116 on a sidewall surface of the first channel region 121 of the first channel pillar 111;

a second gate dielectric layer 117 on a sidewall surface of the second channel region 122 of the second channel pillar 112;

a first work function structure 118 located on a surface of the first gate dielectric layer 116;

a second work function structure 119 located on a surface of the second gate dielectric layer 117, wherein a work function of the second work function structure 119 is different from a work function of the first work function structure 118;

a first gate layer 123 on a surface of the first work function structure 118;

a second gate layer 124 on a surface of the second work function structure 119.

Referring to fig. 14 and 15, fig. 15 is a schematic cross-sectional view taken along the direction BB' of fig. 14, providing a substrate, the surface of the substrate 200 has a plurality of channel pillars 240, the plurality of channel pillars 240 are perpendicular to the surface of the substrate 200, the plurality of channel pillars 240 have a plurality of first channel pillars 241 and a plurality of second channel pillars 242, the first channel pillars 241 and the second channel pillars 242 are used for forming a transistor of a first conductivity type, the first channel pillars 241 have first channel regions 221 therein, and the second channel pillars 242 have second channel regions 222 therein.

In this embodiment, the first conductive type transistor is a P-type transistor; the first channel pillar 241 is used to form a first P-type transistor; the second channel pillar 242 is used to form a second P-type transistor having a threshold voltage greater than that of the first P-type transistor.

In the present embodiment, the plurality of channel pillars 240 further includes a plurality of third channel pillars 243 and a plurality of fourth channel pillars 244, the third channel pillars 243 and the fourth channel pillars 244 are used to form a transistor of the second conductivity type, the third channel pillars 243 have a third channel region 223 therein, and the fourth channel pillars 244 have a fourth channel region 224 therein.

The second conductive type transistor is an N-type transistor; the third channel pillar 243 is used to form a first N-type transistor; the fourth channel pillar 244 is used to form a second N-type transistor having a threshold voltage greater than that of the first N-type transistor.

The number of the third channel columns 243 is one or more; the number of the fourth channel pillars 244 is one or more.

In another embodiment, the first conductivity type transistor is an N-type transistor; the first channel pillar is used for forming a first N-type transistor; the second channel pillar is used for forming a second N-type transistor, and the threshold voltage of the second N-type transistor is larger than that of the first N-type transistor.

In other embodiments, there are also fifth channel pillars in the plurality of channel pillars 240 for forming a transistor of the first conductivity type, the fifth channel pillars having a fifth channel region therein; also among the plurality of channel pillars 240 are sixth channel pillars for forming a transistor of the second conductivity type, having a sixth channel region therein.

In this embodiment, the fifth channel pillar is used to form a third P-type transistor, and the threshold voltage of the third P-type transistor is less than the threshold voltage of the first P-type transistor. The sixth channel column is used for forming a third N-type transistor, and the threshold voltage of the third N-type transistor is smaller than that of the first N-type transistor.

The description of the channel pillar 240 and the substrate 200 is as described in the previous embodiment, and is not repeated herein.

Referring to fig. 16, a first dielectric layer 202 is formed on the substrate, and the first dielectric layer 202 surrounds the plurality of channel pillars 240; after the first dielectric layer 202 is formed, first doped regions 204 are respectively formed in the first channel column 241 and the second channel column 242, and the first doped regions 204 are respectively located at the bottom of the first channel region 221 and the bottom of the second channel region 222.

The materials, processes and structures of the first dielectric layer 202 and the first doped region 204 are as described in the previous embodiments, and are not repeated herein.

In this embodiment, third doped regions 250 are further formed in the third channel column 243 and the fourth channel column 244, respectively, and the third doped regions 250 are located at the bottom of the third channel region 223 and the bottom of the fourth channel region 224, respectively.

In this embodiment, the first conductive type transistor is a P-type transistor, the doped ions in the first doped region 204 are P-type ions, and the doped ions in the third doped region 250 are N-type ions; the P-type ions comprise boron ions or indium ions; the N-type ions include phosphorous ions or arsenic ions.

In other embodiments, the first conductive type transistor is an N-type transistor, the doped ions in the first doped region are N-type ions, and the doped ions in the third doped region are P-type ions.

The method for forming the third doped region 250 includes: forming a third mask layer on the substrate 200 and on the sidewall surfaces of the plurality of channel pillars 240, where the third mask layer exposes the inner portions of the third channel pillars 243 and the bottom portions of the fourth channel pillars 244; and doping the third mask layer as a mask to form a third doped region 250 in the third channel pillar 243 and the fourth channel pillar 244.

The formation method, material and process of the third mask layer are the same as those of the first mask layer, and are not described herein again.

With reference to fig. 16, a first conductive layer 205 is formed on the surface of the first dielectric layer 202, the first conductive layer 205 surrounds the plurality of channel pillars 240, and the first conductive layer 205 is located on the sidewall surface of the first doped region 204; forming a second dielectric layer 206 on the surface of the first conductive layer 205; forming a sacrificial layer 207 on the surface of the second dielectric layer 206, wherein the surface of the sacrificial layer 207 is lower than the top surfaces of the channel pillars 204, the sacrificial layer 207 surrounds the channel pillars 240, and the sacrificial layer 207 is located on the sidewalls of the first channel region 221 and the second channel region 222; an initial third dielectric layer 208 is formed on the surface of the sacrificial layer 207, and the initial third dielectric layer 208 surrounds the plurality of channel pillars 240.

The materials, dimensions and formation processes of the first conductive layer 205, the second dielectric layer 207, the sacrificial layer 207 and the initial third dielectric layer 208 are as described in the foregoing embodiments, and are not described herein again.

Referring to fig. 17, after the initial third dielectric layer 208 is formed, second doped regions 209 are respectively formed in the first channel column 241 and the second channel column 242, the second doped regions 209 are respectively located at the top of the first channel region 221 and the top of the second channel region 222, and the first doped regions 204 and the second doped regions 209 have the same conductivity type.

The formation method, material and structure of the second doped region 209 are as described in the previous embodiments and will not be described herein.

In this embodiment, fourth doping regions 251 are further formed in the third channel column 243 and the fourth channel column 244, respectively, the fourth doping regions 251 are located at the top of the third channel region 223 and the top of the fourth channel region 224, respectively, and the conductivity types of the third doping region 250 and the fourth doping regions 251 are the same.

The method for forming the fourth doped region 251 includes: forming a fourth mask layer on the substrate 200, the fourth mask layer exposing a top surface of the third channel pillar 243 and a top surface of the fourth channel pillar 244; and doping in the third channel column 243 and the fourth channel column 244 by using the fourth mask layer as a mask to form a fourth doped region 251.

The fourth doping region 251 is used as a source or a drain of a transistor of the second conductive type formed by the third channel column 243 and the fourth channel column 244. In this embodiment, the fourth doping region 251 is used as a source.

In this embodiment, the second conductive type transistor is an N-type transistor, and the doped ions in the fourth doped region 251 are N-type ions. In other embodiments, the second conductive type transistor is a P-type transistor, and the doped ions in the fourth doped region 251 are P-type ions.

In this embodiment, the fourth mask layer is located on the surface of the initial third dielectric layer 208.

The formation method, material and structure of the fourth doped region 251 are similar to those of the second doped region 209, and are not repeated herein.

Referring to fig. 18, after forming the second doped region 251, a portion of the initial third dielectric layer 208 (shown in fig. 17) is removed and a portion of the sacrificial layer 207 (shown in fig. 17) is exposed, and a third dielectric layer 214 on the exposed sidewall surfaces of the plurality of channel pillars 240 is formed; the sacrificial layer 207 is removed, and a gate opening 215 is formed between the third dielectric layer 214 and the second dielectric layer 206, wherein the gate opening 215 exposes the sidewall of the first channel region 221 and the sidewall of the second channel region 222.

In the present embodiment, after removing the sacrificial layer 207, the gate opening 215 also exposes the sidewalls of the third channel region 223 and the fourth channel region 224.

The processes of forming the third dielectric layer and removing the sacrificial layer 207 are as described in the previous embodiments, and are not described herein again.

Referring to fig. 19, a first gate dielectric layer 216 is formed on the sidewall surface of the first channel region 221 of the first channel pillar 241; a second gate dielectric layer 217 is formed on the sidewall surface of the second channel region 222 of the second channel pillar 242.

In this embodiment, a third gate dielectric layer 252 is further formed on the sidewall surface of the third channel region 223 of the third channel pillar 243; a fourth gate dielectric layer 253 is formed on a sidewall surface of the fourth channel region 224 of the fourth channel pillar 244. The first gate dielectric layer 216, the second gate dielectric layer 217, the third gate dielectric layer 252 and the fourth gate dielectric layer 253 are also positioned on the surface of the second dielectric layer 206

The materials, thicknesses, structural positions and formation processes of the first gate dielectric layer 216, the second gate dielectric layer 217, the third gate dielectric layer 252 and the fourth gate dielectric layer 253 are the same as those of the first gate dielectric layer and the second gate dielectric layer in the previous embodiment, and are not described herein again.

Referring to fig. 20 and 21, which are partially enlarged cross-sectional views of a region C, a region D, a region E and a region F in fig. 20, a first work function structure 218 is formed on a surface of the first gate dielectric layer 216; forming a second work function structure 219 on the surface of the second gate dielectric layer 217, wherein the work function of the second work function structure 219 is different from that of the first work function structure 218; forming a third work function structure 254 on the surface of the third gate dielectric layer 252; and forming a fourth work function structure 255 on the surface of the fourth gate dielectric layer 253, wherein the work function of the fourth work function structure 255 is different from that of the third work function structure 254.

In this embodiment, the threshold voltage of the first P-type transistor is less than the threshold voltage of the second P-type transistor. The first work function structure 218 includes: a first work function layer 231, a second work function layer 232 on the surface of the first work function layer 231, and a third work function layer 235 on the surface of the second work function layer 232; the second work function structure 219 includes a first work function layer 231 and a third work function layer 235 on a surface of the first work function layer 231.

In this embodiment, the first work function layer 231 is made of a P-type work function material; the second work function layer 232 is made of a P-type work function material; the third work function layer 235 is made of a P-type work function layer material; the P-type work function material includes TiN and TaN. The material of the first work function layer 231, the material of the second work function layer 232, and the material of the third work function layer are the same or different.

In this embodiment, the material of the first work function layer 231, the material of the second work function layer 232, and the material of the third work function layer are the same. The first work function layer 231 is made of TiN or TaN; the second work function layer 232 is made of TiN or TaN; the material of the third work function layer 235 is TiN or TaN. The thickness range of the first work function layer 231 is 8 to 12 angstroms; the thickness range of the second work function layer 232 is 8 angstroms to 12 angstroms; the thickness of the third work function layer 235 ranges from 8 angstroms to 12 angstroms. The forming process of the first work function layer 231, the second work function layer 232 and the third work function layer 235 includes an atomic layer deposition process.

In this embodiment, the second type transistor is an N-type transistor, and the threshold voltage of the second N-type transistor is greater than the threshold voltage of the first N-type transistor, then the fourth work function structure includes: a third work function layer 235. Since the material of the third work function layer 235 is a P-type work function layer material, the threshold voltage of the second N-type transistor can be greater than that of the first N-type transistor.

When the third work function layer 235 is made of TiN, the threshold voltage of the second N-type transistor is increased by 20 mv compared with the threshold voltage of the first N-type transistor every time the thickness of the third work function layer 235 is increased by 10 angstroms.

In an embodiment, the third work function structure 254 can further include: a fourth work function layer on the surface of the third gate dielectric layer; the fourth work function structure 255 includes: a fourth work function layer on the surface of the third work function layer 235; the fourth work function layer is made of an N-type work function material; the N-type work function material comprises TiAl.

In another embodiment, the first type transistor is an N-type transistor. The second conductive type transistor is a P-type transistor; the third channel column is used for forming a first P-type transistor; the fourth channel column is used for forming a second P-type transistor, and the threshold voltage of the second P-type transistor is different from the threshold voltage of the first P-type transistor.

In other embodiments, there are also fifth channel pillars in the plurality of channel pillars 240 for forming transistors of the first conductivity type, and there are also sixth channel pillars in the plurality of channel pillars 240 for forming transistors of the second conductivity type. In this embodiment, the method further comprises forming a fifth work function structure on the exposed fifth channel region sidewall of the gate opening and forming a sixth work function structure on the exposed sixth channel region sidewall of the gate opening.

When the fifth channel pillar is used to form a third P-type transistor having a threshold voltage less than a threshold voltage of the first P-type transistor, the fifth work function structure comprises: the work function layer comprises a first work function layer, a second work function layer positioned on the surface of the first work function layer, a third work function layer positioned on the surface of the second work function layer and a fourth work function layer positioned on the surface of the third work function layer. The fourth work function layer is made of a P-type work function layer material, and the P-type work function layer material comprises TiN and TaN.

When the sixth channel column is used for forming a third N-type transistor, the threshold voltage of the third N-type transistor is smaller than that of the first N-type transistor; the sixth work function structure includes: the fourth work function layer is positioned on the surface of the sixth gate dielectric layer, and the fifth work function layer is positioned on the surface of the fourth work function layer. The fourth work function layer and the fifth work function layer are both made of N-type work function materials.

In this embodiment, before the first and second work function structures are formed, a barrier layer 233 is formed on the surfaces of the first and second gate dielectric layers. In one embodiment, a stop layer 234 is formed on the surface of the barrier layer. In another embodiment, the stop layer can also not be formed.

In this embodiment, the stop layer is of a different material than the first workfunction structure surface in contact, and the stop layer is of a different material than the second workfunction structure surface in contact. The stop layer and the barrier layer are as described in the previous embodiments and are not described herein.

Referring to fig. 22, a first gate layer 225 is formed on the surface of the first work function structure 218; a second gate layer 226 is formed on the surface of the second work function structure 219.

In this embodiment, the method further includes: forming a third gate layer 227 on a surface of the third work function structure 254; a fourth gate layer 228 is formed on the surface of the fourth work function structure 255.

In one embodiment, a first capping layer is formed on the surface of the first work-function structure 218 before the first gate layer 225 is formed; forming a second capping layer on the surface of the second work function structure 219 before forming the second gate layer 226; forming a third capping layer on a surface of the third work function structure 254 before forming a third gate layer 227; a fourth capping layer is formed on the surface of the fourth work function structure 255 before forming the fourth gate layer 228.

In one embodiment, the first, second, third and fourth capping layers are formed simultaneously.

The size of the first gate layer 225 in the direction vertical to the substrate surface is 28 nm to 32 nm; the size of the second gate layer 226 in a direction perpendicular to the substrate surface is 28 nm to 32 nm; the size of the third gate layer 227 in a direction perpendicular to the substrate surface is 28 nm to 32 nm; the fourth gate layer 228 has a size of 28 nm to 32 nm in a direction perpendicular to the substrate surface.

The materials and formation processes of the first capping layer, the second capping layer, the third capping layer, the fourth capping layer, the first gate layer and the second gate layer are as described in the first capping layer, the second capping layer, the first gate layer and the second gate layer in the previous embodiments, and are not described herein again.

In this embodiment, a fourth dielectric layer 229 is formed on the surface of the first gate layer and the surface of the second gate layer, and the fourth dielectric layer 229 is further located on the surface of the sidewall of the third dielectric layer 214. The material of the fourth dielectric layer is as described in the previous embodiments, and is not described herein again.

The method for forming the fourth dielectric layer 229 includes: forming a fourth dielectric material film on the surfaces of the first gate layer 225, the second gate layer 226, the third gate layer 227, the fourth gate layer 228 and the third dielectric layer 214, wherein the surface of the fourth dielectric material film is higher than the top of the channel column 240; and after the fourth medium material film is flattened, etching the fourth medium material film back to form the initial fourth medium layer.

In this embodiment, the surface of the fourth dielectric layer 229 is lower than the top surface of the channel pillar 240; simultaneously with or after etching back the fourth dielectric material film, a portion of the third dielectric layer 214 is etched and a portion of the sidewalls and top surface of the channel pillar 240 are exposed.

In an embodiment, after forming the fourth dielectric layer, forming a second conductive layer on the surface of the fourth dielectric layer 125 and the exposed surface of the second doped region 109 is further included. The second conductive layer is used for electrically connecting with the second doped region 109. A third conductive layer is formed on the surface of the fourth dielectric layer 125 and the exposed surface of the fourth doped region 251. The third conductive layer is used for electrically connecting with the fourth doped region 251. The material of the second conductive layer and the third conductive layer includes a metal or a metal compound.

Accordingly, an embodiment of the present invention further provides a vertical nanowire transistor formed by the above method, with reference to fig. 22, including:

a substrate, a surface of the substrate 200 has a plurality of channel pillars, the plurality of channel pillars are perpendicular to the surface of the substrate 200, the plurality of channel pillars has a plurality of first channel pillars 221, a plurality of second channel pillars 222, a plurality of third channel pillars 243 and a plurality of fourth channel pillars 224, the first channel pillars 242 and the second channel pillars 243 are used for forming transistors of a first conductivity type, the first channel pillars 242 have first channel regions 221 therein, the second channel pillars 243 have second channel regions 222 therein, the third channel pillars 243 and the fourth channel pillars 224 are used for forming transistors of a second conductivity type, the third channel pillars 243 have third channel regions 223 therein, and the fourth channel pillars 224 have second channel regions 224 therein;

a first gate dielectric layer 216 on a sidewall surface of the first channel region 221 of the first channel pillar 241;

a second gate dielectric layer 217 on a sidewall surface of the second channel region 222 of the second channel pillar 242;

a third gate dielectric layer 252 on a sidewall surface of the third channel region 223 of the third channel pillar 243;

a fourth gate dielectric layer 253 on a sidewall surface of the fourth channel region 224 of the fourth channel pillar 244;

a first work function structure 218 located on a surface of the first gate dielectric layer 216;

a second work function structure 219 located on the surface of the second gate dielectric layer 217, wherein the work function of the second work function structure is different from that of the first work function structure;

a third work function structure 252 on a surface of the third gate dielectric layer 252;

a fourth work function structure 255 located on the surface of the fourth gate dielectric layer 253, wherein the work function of the fourth work function structure is different from the work function of the third work function structure;

a first gate layer 225 on a surface of the first work-function structure 218;

a second gate layer 226 on a surface of the second work function structure 219;

a third gate layer 227 at a surface of the third work function structure 252;

a fourth gate layer 228 on a surface of the fourth work function structure 255.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected by one skilled in the art without departing from the spirit and scope of the invention, as defined in the appended claims.

Claims

1. A method of forming a vertical nanowire transistor, comprising:

providing a substrate, wherein the surface of the substrate is provided with a plurality of channel columns, the channel columns are perpendicular to the surface of the substrate, the channel columns are provided with a plurality of first channel columns and a plurality of second channel columns, the first channel columns and the second channel columns are used for forming transistors of a first conduction type, the first channel columns are provided with first channel regions, and the second channel columns are provided with second channel regions;

forming first doped regions in the first channel column and the second channel column respectively, wherein the first doped regions are located at the bottom of the first channel region and the bottom of the second channel region respectively;

forming a first dielectric layer on the substrate, wherein the first dielectric layer surrounds the plurality of channel columns;

forming a first conductive layer on the surface of the first dielectric layer, wherein the first conductive layer surrounds the channel columns and is positioned on the surface of the side wall of the first doped region;

forming a second dielectric layer on the surface of the first conductive layer;

forming a sacrificial layer on the surface of the second dielectric layer, wherein the surface of the sacrificial layer is lower than the top surfaces of the channel columns, the sacrificial layer surrounds the channel columns, and the sacrificial layer is located on the side wall of the first channel region and the side wall of the second channel region;

forming a third dielectric layer on the surface of the sacrificial layer, wherein the third dielectric layer surrounds the channel columns, is positioned on the exposed side wall surfaces of the channel columns, and is exposed out of part of the sacrificial layer;

removing the sacrificial layer, and forming a gate opening between the third dielectric layer and the second dielectric layer, wherein the gate opening exposes the side wall of the first channel region and the side wall of the second channel region;

forming a first gate dielectric layer on the surface of the side wall of the first channel region of the first channel column exposed by the gate opening and the surface of the second dielectric layer;

forming a second gate dielectric layer on the surface of the side wall of the second channel region of the second channel column exposed by the gate opening and the surface of the second dielectric layer;

forming a first work function structure on the surface of the first gate dielectric layer;

forming a second work function structure on the surface of the second gate dielectric layer, wherein the work function of the second work function structure is different from that of the first work function structure;

forming a first gate layer on the surface of the first work function structure;

and forming a second gate layer on the surface of the second work function structure.

2. The method of forming a vertical nanowire transistor of claim 1, wherein the first conductivity type transistor is a P-type transistor; the first channel column is used for forming a first P-type transistor; the second channel column is used for forming a second P-type transistor, and the threshold voltage of the second P-type transistor is larger than that of the first P-type transistor.

3. The method of forming a vertical nanowire transistor of claim 2, wherein the first work function structure comprises: the first work function layer and the second work function layer are positioned on the surface of the first work function layer; the second work function structure comprises a first work function layer; the first work function layer is made of a P-type work function material; the material of the second work function layer is a P-type work function material.

4. The method of forming a vertical nanowire transistor of claim 3, wherein a material of the first work function layer is the same as or different from a material of the second work function layer; the first work function layer is made of TiN or TaN; the second work function layer is made of TiN or TaN.

5. The method of forming a vertical nanowire transistor of claim 3 or 4, wherein the first work function layer has a thickness of 8 to 12 angstroms; the thickness of the second work function layer is 13-18 angstroms.

6. The method of forming a vertical nanowire transistor of claim 4, wherein when the material of the second work function layer is TiN, the threshold voltage of the second P-type transistor is increased by 80 mV to 120 mV for every 10A increase in the thickness of the second work function layer compared to the threshold voltage of the first P-type transistor.

7. The method of forming a vertical nanowire transistor of claim 2, wherein the first and second work function structures are both single layer structures, the first and second work function structures are of the same material, and the first work function structure has a thickness greater than the second work function structure; the first work function structure and the second work function structure are made of TiN or TaN.

8. The method of forming a vertical nanowire transistor of claim 7, wherein when the material of the first and second work function structures is TiN, the threshold voltage of the second P-type transistor increases by 80 mv to 120 mv compared to the threshold voltage of the first P-type transistor for every 10 a reduction in thickness of the second work function structure compared to the first work function structure.

9. The method of forming a vertical nanowire transistor of claim 2, wherein the plurality of channel pillars further comprises a plurality of third channel pillars and a plurality of fourth channel pillars, the third and fourth channel pillars for forming a transistor of a second conductivity type, the third channel pillar having a third channel region therein and the fourth channel pillar having a fourth channel region therein; the forming method further includes: forming a third gate dielectric layer on the surface of the side wall of the third channel region of the third channel column; forming a fourth gate dielectric layer on the surface of the side wall of the fourth channel region of the fourth channel column; forming a third work function structure on the surface of the third gate dielectric layer; forming a fourth work function structure on the surface of the fourth gate dielectric layer, wherein the work function of the fourth work function structure is different from that of the third work function structure; forming a third gate layer on the surface of the third work function structure; and forming a fourth gate layer on the surface of the fourth work function structure.

10. The method of forming a vertical nanowire transistor of claim 9, wherein the second conductivity type transistor is an N-type transistor; the third channel column is used for forming a first N-type transistor; the fourth channel column is used for forming a second N-type transistor, and the threshold voltage of the second N-type transistor is larger than that of the first N-type transistor.

11. The method of forming a vertical nanowire transistor of claim 10, wherein the fourth work function structure comprises: a third work function layer; the third work function layer is made of a P-type work function layer material.

12. The method of forming a vertical nanowire transistor of claim 11, wherein the first work function structure comprises: the first work function layer, the second work function layer positioned on the surface of the first work function layer and the third work function layer positioned on the surface of the second work function layer; the second work function structure comprises a first work function layer and a third work function layer positioned on the surface of the first work function layer; the first work function layer is made of a P-type work function material; the material of the second work function layer is a P-type work function material.

13. The method of forming a vertical nanowire transistor of claim 11 or 12, wherein the material of the third work function layer is TiN or TaN; the thickness of the third work function layer is 8-12 angstroms.

14. The method of forming a vertical nanowire transistor of claim 13, wherein when the material of the third work function layer is TiN, a threshold voltage of the second N-type transistor increases by 18 mv to 22 mv for every 10 a increase in thickness of the third work function layer compared to a threshold voltage of the first N-type transistor.

15. The method of forming a vertical nanowire transistor of claim 11, wherein the third work function structure comprises: a fourth work function layer; the fourth work function structure includes: a fourth work function layer located on a surface of the third work function layer; the fourth work function layer is made of an N-type work function material; the N-type work function material comprises TiAl.

16. The method of forming a vertical nanowire transistor of claim 1, wherein the first conductivity type transistor is an N-type transistor; the first channel pillar is used for forming a first N-type transistor; the second channel pillar is used for forming a second N-type transistor, and the threshold voltage of the second N-type transistor is larger than that of the first N-type transistor.

17. The method of forming a vertical nanowire transistor of claim 16, wherein the first work function structure comprises: the first work function layer and the second work function layer are positioned on the surface of the first work function layer; the second work function structure comprises a first work function layer, and the first work function layer is made of an N-type work function material; the material of the second work function layer is an N-type work function material.

18. The method of forming a vertical nanowire transistor of claim 17, wherein the material of the first work function layer is TiAl; the material of the second work function layer is TiAl; the thickness of the first work function layer is 8-12 angstroms; the thickness of the second work function layer is 13-18 angstroms.

19. The method of claim 18, wherein when the material of the second work function layer is TiAl, the threshold voltage of the second N-type transistor is increased by 80 mv to 120 mv compared to the threshold voltage of the first N-type transistor for every 10 a increase in the thickness of the second work function layer.

20. The method of forming a vertical nanowire transistor of claim 16, wherein the plurality of channel pillars further comprises a third plurality of channel pillars and a fourth plurality of channel pillars, the third and fourth channel pillars for forming a transistor of a second conductivity type, the third channel pillar having a third channel region therein and the fourth channel pillar having a fourth channel region therein; the forming method further includes: forming a third gate dielectric layer on the surface of the side wall of the third channel region of the third channel column; forming a fourth gate dielectric layer on the surface of the side wall of the fourth channel region of the fourth channel column; forming a third work function structure on the surface of the third gate dielectric layer; forming a fourth work function structure on the surface of the fourth gate dielectric layer, wherein the work function of the fourth work function structure is different from that of the third work function structure; forming a third gate layer on the surface of the third work function structure; and forming a fourth gate layer on the surface of the fourth work function structure.

21. The method of forming a vertical nanowire transistor of claim 20, wherein the second conductivity type transistor is a P-type transistor; the third channel column is used for forming a first P-type transistor; the fourth channel column is used for forming a second P-type transistor, and the threshold voltage of the second P-type transistor is different from the threshold voltage of the first P-type transistor.

22. The method of forming a vertical nanowire transistor of claim 9 or 20, further comprising, prior to forming the third and fourth gate dielectric layers: respectively forming third doped regions in the third channel column and the fourth channel column, wherein the third doped regions are respectively positioned at the bottom of the third channel region and the bottom of the fourth channel region; and forming fourth doped regions in the third channel column and the fourth channel column respectively, wherein the fourth doped regions are positioned at the top of the third channel region and the top of the fourth channel region respectively, and the conductivity types of the third doped region and the fourth doped region are the same.

23. The method of forming a vertical nanowire transistor of claim 1, further comprising, prior to forming the first and second gate dielectric layers: and forming second doped regions in the first channel column and the second channel column respectively, wherein the second doped regions are positioned at the top of the first channel region and the top of the second channel region respectively, and the conductivity types of the first doped region and the second doped region are the same.

24. The method of forming a vertical nanowire transistor of claim 1, wherein the method of forming the first doped region comprises: forming a first mask layer on the substrate and on the side wall surfaces of the channel columns, wherein the first mask layer exposes partial side wall surfaces of the bottoms of the first channel columns, and the first mask layer exposes partial side wall surfaces of the bottoms of the second channel columns; and doping in the first channel column and the second channel column by taking the first mask layer as a mask to form a first doped region.

25. The method of forming a vertical nanowire transistor of claim 23, wherein the method of forming the second doped region comprises: forming a second mask layer on the substrate, wherein the second mask layer exposes the top surface of the first channel column and the top surface of the second channel column; and doping in the first channel column and the second channel column by taking the second mask layer as a mask to form a second doped region.

26. The method of forming a vertical nanowire transistor of claim 1, further comprising: and forming a fourth dielectric layer on the surface of the first grid layer and the surface of the second grid layer, wherein the fourth dielectric layer is also positioned on the surface of the side wall of the third dielectric layer.

27. The method of forming a vertical nanowire transistor of claim 1, further comprising: and forming a barrier layer on the surfaces of the first gate dielectric layer and the second gate dielectric layer before forming the first work function structure and the second work function structure.

28. The method of forming a vertical nanowire transistor of claim 27, further comprising: and forming a stop layer on the surface of the barrier layer.

29. The method of forming a vertical nanowire transistor of claim 28, wherein the stop layer is a different material than the contacted first workfunction structure surface and the stop layer is a different material than the contacted second workfunction structure surface.

30. The method of forming a vertical nanowire transistor of claim 28, wherein the stop layer is a material of TaN.

31. The method of forming a vertical nanowire transistor of claim 28, wherein the material of the barrier layer is TiN or TaN.

32. The method of forming a vertical nanowire transistor of claim 1, wherein a first capping layer is formed on a surface of the first work function structure prior to forming the first gate layer; and forming a second covering layer on the surface of the second work function structure before forming the second gate layer.

33. The method of forming a vertical nanowire transistor of claim 32, wherein the material of the first capping layer comprises TaN or TiN; the material of the second capping layer comprises TaN or TiN.

34. The method of forming a vertical nanowire transistor of claim 1, wherein the perimeter of the channel pillar is between 30 nanometers and 40 nanometers.

35. The method of forming a vertical nanowire transistor of claim 1, wherein the first gate layer has a dimension in a direction perpendicular to a surface of the substrate of between 28 nanometers and 32 nanometers; the size of the second gate layer in the direction vertical to the surface of the substrate is 28-32 nm.

36. The method of forming a vertical nanowire transistor of claim 1, wherein the material of the first and second gate dielectric layers comprises a high-K dielectric material; the material of the first gate layer and the second gate layer comprises a metal.

37. A vertical nanowire transistor formed by the method of any of claims 1 through 36, comprising:

the transistor array substrate comprises a substrate, a plurality of channel columns and a plurality of first and second control units, wherein the surface of the substrate is provided with the plurality of channel columns, the plurality of channel columns are perpendicular to the surface of the substrate, the plurality of channel columns are provided with a plurality of first channel columns and a plurality of second channel columns, the first channel columns and the second channel columns are used for forming transistors of a first conduction type, first channel regions are arranged in the first channel columns, and second channel regions are arranged in the second channel columns;

the first doping regions are respectively positioned in the first channel column and the second channel column and are respectively positioned at the bottom of the first channel region and the bottom of the second channel region;

a first dielectric layer on the substrate, the first dielectric layer surrounding the plurality of channel pillars;

the first conducting layer is positioned on the surface of the first dielectric layer, surrounds the plurality of channel columns and is positioned on the surface of the side wall of the first doped region;

the second dielectric layer is positioned on the surface of the first conductive layer;

a plurality of third dielectric layers respectively surrounding the plurality of channel columns, wherein the third dielectric layers are positioned on the surfaces of the exposed side walls of the plurality of channel columns, a gate opening is arranged between the third dielectric layers and the second dielectric layers, and the side wall of the first channel region and the side wall of the second channel region are exposed from the gate opening;

the first gate dielectric layer is positioned on the side wall surface of the first channel region of the first channel column exposed out of the gate opening and on the surface of the second dielectric layer;

the second gate dielectric layer is positioned on the side wall surface of the second channel region of the second channel column exposed by the gate opening and on the surface of the second dielectric layer;

the first work function structure is positioned on the surface of the first gate dielectric layer;

the second work function structure is positioned on the surface of the second gate dielectric layer, and the work function of the second work function structure is different from that of the first work function structure;

a first gate layer on a surface of the first work function structure;

a second gate layer on a surface of the second work function structure.