CN107293488A - Semiconductor structure and its manufacture method - Google Patents

Semiconductor structure and its manufacture method Download PDF

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Publication number
CN107293488A
CN107293488A CN201610206428.0A CN201610206428A CN107293488A CN 107293488 A CN107293488 A CN 107293488A CN 201610206428 A CN201610206428 A CN 201610206428A CN 107293488 A CN107293488 A CN 107293488A
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Prior art keywords
pseudo
layer
area
side wall
grid structure
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周飞
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Priority to CN201610206428.0A priority Critical patent/CN107293488A/en
Publication of CN107293488A publication Critical patent/CN107293488A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A kind of semiconductor structure and its manufacture method, methods described include：Formation includes the substrate of first area and second area, and protrudes from the fin of substrate；The pseudo- grid structure of fin portion surface formation first in first area, including gate oxide and the first pseudo- gate electrode layer, in the pseudo- grid structure of second area fin portion surface formation second, including pseudo- gate oxide and the second pseudo- gate electrode layer；Form dielectric layer；The first pseudo- gate electrode layer is removed, forming first in dielectric layer is open；In the first opening sidewalls formation compensation side wall；The second pseudo- grid structure is removed, forming second in dielectric layer is open；Gate dielectric layer is formed on the gate oxide surface, the bottom of the side wall of compensation side wall and the second opening and side wall；Metal level is filled in the described first opening and the second opening.The damaged portion that side wall covers gate oxide is compensated, making the damaged portion of gate oxide turns into the non-effective gate oxide above channel region, so as to improve the electrical property of device.

Description

Semiconductor structure and its manufacture method
Technical field
The present invention relates to semiconductor applications, more particularly to a kind of semiconductor structure and its manufacture method.
Background technology
In semiconductor fabrication, with the development trend of super large-scale integration, integrated circuit feature size persistently reduces.For the reduction of meeting market's demand size, the channel length of MOSFET FETs is also corresponding constantly to be shortened.But, with the shortening of device channel length, distance between device source electrode and drain electrode also shortens therewith, therefore grid is deteriorated therewith to the control ability of raceway groove, the difficulty of grid voltage pinch off (pinch off) raceway groove is also increasing, so that sub-threshold leakage (subthreshold leakage) phenomenon, i.e., so-called short-channel effect (SCE：Short-channel effects) it is easier to occur.
Therefore, for the reduction of more preferable meeting market's demand size, semiconductor technology gradually starts the transistor transient to the three-dimensional with more high effect from planar MOSFET transistor, such as fin field effect pipe (FinFET).In FinFET, grid can be at least controlled from both sides to ultra-thin body (fin), with control ability of the grid more much better than than planar MOSFET devices to raceway groove, can be good at suppressing short-channel effect；And FinFET is relative to other devices, the compatibility with more preferable existing production of integrated circuits technology.
Fin field effect pipe is broadly divided into core (Core) device and periphery (I/O) device (or being input/output device) according to function distinguishing.Distinguished according to the conductivity type of fin field effect pipe, core devices can be divided into core nmos device and core PMOS device, and peripheral devices can be divided into periphery nmos device and periphery P MOS device.
Under normal circumstances, much bigger than the operating voltage of core devices of the operating voltage of peripheral devices.The problems such as to prevent electrical breakdown, when the operating voltage of device is bigger, it is desirable to which the thickness of the gate dielectric layer of device is thicker, therefore, the thickness of the gate dielectric layer of peripheral devices is typically larger than the thickness of the gate dielectric layer of core devices.
But, the electric property of the semiconductor devices of prior art formation is poor.
The content of the invention
The problem of present invention is solved is to provide a kind of semiconductor structure and its manufacture method, improves the electric property of semiconductor devices.
To solve the above problems, the present invention provides a kind of manufacture method of semiconductor structure.Comprise the following steps：Semiconductor base is formed, the semiconductor base includes substrate, and protrudes from the fin of the substrate, and the substrate includes first area and second area；The pseudo- grid structure of fin portion surface formation first in the first area and the pseudo- grid structure of fin portion surface formation second in the second area, wherein, described first pseudo- grid structure includes gate oxide and the first pseudo- gate electrode layer, and the described second pseudo- grid structure includes pseudo- gate oxide and the second pseudo- gate electrode layer；In semiconductor substrate surface formation dielectric layer, the dielectric layer flushes with the described first pseudo- grid structure and the second pseudo- grid structure and exposes the described first pseudo- gate electrode layer and the second pseudo- gate electrode layer；The described first pseudo- gate electrode layer is removed, forming first in the dielectric layer is open；In first opening sidewalls formation compensation side wall；The described second pseudo- grid structure is removed, forming second in the dielectric layer is open；Gate dielectric layer is formed on the gate oxide surface, the bottom of the side wall of compensation side wall and the second opening and side wall；Metal level is filled in the described first opening and the second opening.
Compared with prior art, technical scheme has advantages below：
After the pseudo- grid structure of etching technics formation first, the gate oxide as the first grid structure being subsequently formed a part, but the etching technics easily causes damage to the gate oxide, and damage field is close to the trench edges area of device, therefore the present invention is after the first pseudo- gate electrode layer is removed, in the first opening sidewalls formation compensation side wall, formed after device, the gate oxide being damaged is by the compensation side wall covering, the effective gate oxide of the gate oxide being damaged not above channel region, so as to avoid the influence of the gate oxide that is damaged to the electric property of semiconductor devices, and then improve the electric property of semiconductor devices.
In alternative, described first pseudo- grid structure also includes the first barrier layer between the gate oxide and the first pseudo- gate electrode layer, first barrier layer is used for as the etching stop layer for forming the compensation side wall, damage is caused to the gate oxide so as to avoid the formation of the etching technics for compensating side wall, and then avoids having undesirable effect the electric property of semiconductor devices.
Brief description of the drawings
Fig. 1 to Fig. 5 is the corresponding structural representation of each step of manufacture method of prior art semiconductor structure；
Fig. 6 to Figure 19 be semiconductor structure of the present invention the embodiment of manufacture method one in each step counter structure schematic diagram.
Embodiment
The electrical property of the semiconductor devices of prior art is poor, and its reason is analyzed with reference to semiconductor structure manufacture method.Referring to figs. 1 to Fig. 5, the corresponding structural representation of each step of manufacture method of prior art semiconductor structure is shown.The manufacture method of the semiconductor structure comprises the following steps：
With reference to Fig. 1, semiconductor base is formed, the semiconductor base includes substrate 100, protrudes from the fin of the substrate 100；The substrate 100 includes first area I and second area II, and the fin for protruding from the substrate 100 of first area I is the first fin 110, and the fin for protruding from the substrate 100 of second area II is the second fin 120.The first area I is used to form peripheral devices, and the second area II is used to form core devices.
Specifically, the semiconductor base also includes the first pseudo- grid structure (not indicating) positioned at the first area I, the second pseudo- grid structure (not indicating) positioned at the second area II, the first area source region positioned at the described first pseudo- grid structure both sides or drain region 113, and the second area source region positioned at the described second pseudo- grid structure both sides or drain region 123.Wherein, described first pseudo- grid structure includes the gate oxide 111 positioned at the surface of the first fin 110 and the first pseudo- gate electrode layer 112 positioned at the surface of gate oxide 111, and the described second pseudo- grid structure includes the pseudo- gate oxide 121 positioned at the surface of the second fin 120 and the second pseudo- gate electrode layer 122 positioned at the pseudo- surface of gate oxide 121.The semiconductor base also includes the dielectric layer 130 for covering the described first pseudo- grid structure and the second pseudo- grid structure.
With reference to Fig. 2, etching removes the described first pseudo- gate electrode layer 112 (as shown in Figure 1), exposes the part surface of gate oxide 111 and the first opening 200 is formed in the dielectric layer 130；Etching removes the described second pseudo- gate electrode layer 122 (as shown in Figure 1), exposes the part pseudo- surface of gate oxide 121 and the second opening 210 is formed in the dielectric layer 130.
With reference to Fig. 3, the first graph layer 300 of the covering first area I is formed, is mask with first graph layer 300, etching removes the pseudo- gate oxide 121 (as shown in Figure 2) of 210 bottoms of the second opening；Remove first graph layer 300.
With reference to Fig. 4, in the bottom of the described first opening 200 and side wall, in the bottom of the described second opening 210 and side wall formation gate dielectric layer 150, the gate dielectric layer 150 also covers the surface of dielectric layer 130.
With reference to referring to Fig. 5, the full metal formation metal level 140 of filling in the described first 200 (as shown in Figure 4) of opening and the second 210 (as shown in Figure 4) of opening, the gate dielectric layer 150 and metal level 140 of the first area I constitute first grid structure 116, and the gate dielectric layer 150 and metal level 140 of the second area II constitute second grid structure 126.
The first area I is used to form peripheral devices, prior art using the gate oxide 111 as the first grid structure of the first area I a part, but the etching technics for forming the described first pseudo- grid structure (not indicating) easily causes damage to the gate oxide 111, so as to influence the formation quality of the first grid structure, and damage field is close to the trench edges area of peripheral devices, and then reduce the electric property of semiconductor devices.
In order to solve the technical problem, the present invention provides a kind of manufacture method of semiconductor devices, including：Semiconductor base is formed, the semiconductor base includes substrate, and protrudes from the fin of the substrate, and the substrate includes first area and second area；The pseudo- grid structure of fin portion surface formation first in the first area and the pseudo- grid structure of fin portion surface formation second in the second area, wherein, described first pseudo- grid structure includes gate oxide and the first pseudo- gate electrode layer, and the described second pseudo- grid structure includes pseudo- gate oxide and the second pseudo- gate electrode layer；In semiconductor substrate surface formation dielectric layer, the dielectric layer flushes with the described first pseudo- grid structure and the second pseudo- grid structure and exposes the described first pseudo- gate electrode layer and the second pseudo- gate electrode layer；The described first pseudo- gate electrode layer is removed, forming first in the dielectric layer is open；In first opening sidewalls formation compensation side wall；The described second pseudo- grid structure is removed, forming second in the dielectric layer is open；Gate dielectric layer is formed on the gate oxide surface, the bottom of the side wall of compensation side wall and the second opening and side wall；Metal level is filled in the described first opening and the second opening.
After the pseudo- grid structure of etching technics formation first, the gate oxide as the first grid structure being subsequently formed a part, but the etching technics easily causes damage to the gate oxide, and damage field is close to the trench edges area of device, therefore the present invention is after the first pseudo- gate electrode layer is removed, in the first opening sidewalls formation compensation side wall, formed after device, the gate oxide being damaged is by the compensation side wall covering, the effective gate oxide of the gate oxide being damaged not above channel region, so as to avoid the influence of the gate oxide that is damaged to the electric property of semiconductor devices, and then improve the electric property of semiconductor devices.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, the specific embodiment of the present invention is described in detail below in conjunction with the accompanying drawings.
Fig. 6 to Figure 19 be semiconductor structure of the present invention the embodiment of manufacture method one in each step counter structure schematic diagram.
With reference to reference to Fig. 6 and Fig. 7, Fig. 7 is cross-sectional views of the Fig. 6 along AA1 directions, form semiconductor base, the semiconductor base includes substrate 400, and the fin of the substrate 400 is protruded from, the substrate 400 includes first area I (as shown in Figure 7) and second area II (as shown in Figure 7).
In the present embodiment, the fin for protruding from the substrate 400 of first area I is the first fin 410, and the fin for protruding from the substrate 400 of second area II is the second fin 420.
In the present embodiment, the first area I is used to form peripheral devices (for example：Input/output device), the second area II is used to form core devices.The first area I can be N-type region or p type island region, and the second area II can be N-type region or p type island region, and the first area I is identical with the type of second area II.
The material of the substrate 400 is silicon, germanium, SiGe, carborundum, GaAs or gallium indium, and the substrate 400 can also be the silicon substrate on insulator or the germanium substrate on insulator；The material of the fin 420 of first fin 410 and second includes silicon, germanium, SiGe, carborundum, GaAs or gallium indium.In the present embodiment, the substrate 400 is silicon substrate, and the material of the fin 420 of the first fin 410 and second is silicon.
Specifically, the step of forming the semiconductor base includes：Initial substrate is provided, patterned hard mask layer 500 is formed on the initial substrate；It is mask with the hard mask layer 500, etches the initial substrate, forms some discrete projections；It is described it is raised be initial substrate after fin, etching as substrate 400, the substrate 400 includes first area I and second area II, and the fin positioned at the first area I is the first fin 410, is the second fin 420 positioned at the fin of the second area II.
In the present embodiment; the material of the hard mask layer 500 is silicon nitride; subsequently when carrying out flatening process; the surface of hard mask layer 500 can as flatening process stop position, and the hard mask layer 500 can also play a part of the top of protection first fin 410, the top of the second fin 420.
With reference to reference Fig. 8, it is necessary to which explanation, is formed after the semiconductor base, in addition to：Liner oxidation layer 401 is formed on the surface of 410 and second fin of the first fin 420, for repairing the fin 420 of the first fin 410 and second.
In oxidation processes, because the ratio surface of the first fin 410 and the faceted portions of the second fin 420 protrusion is bigger, easily it is oxidized, after subsequently removing liner oxidation layer 401, not only the first fin 410 and the defect layer on the surface of the second fin 420 are removed, and protrusion faceted portions are also removed, make the surface of the fin 420 of the first fin 410 and second smooth, lattice quality is improved, the first fin 410 and the drift angle point discharge problem of the second fin 420 are avoided, is conducive to improving the performance of fin field effect pipe.
In the present embodiment, the liner oxidation layer 401 is also located at the surface of substrate 400, and the material of the liner oxidation layer 401 is silica.
With reference to reference Fig. 9, it is necessary to which explanation, is formed after the liner oxidation layer 401, in addition to：Separation layer 402 is formed on the surface of substrate 400.
The separation layer 402 as semiconductor structure isolation structure, for playing buffer action between adjacent devices, the material of the separation layer 402 can be silica, silicon nitride or silicon oxynitride.In the present embodiment, the material of the separation layer 402 is silica.
It should be noted that in the present embodiment, the separation layer 402 is shallow groove isolation layer, but is not limited to shallow groove isolation layer.
Specifically, the step of forming separation layer 402 includes：Barrier film, the top top (as shown in Figure 8) higher than the hard mask layer 500 of the barrier film are formed on 401 surface of liner oxidation layer；Grinding removes the barrier film higher than the top of hard mask layer 500；The barrier film of segment thickness is removed to form separation layer 402；Remove the hard mask layer 500.
It should be noted that also removing the liner oxidation layer 401 of part fin portion surface during the barrier film of segment thickness is removed.
With reference to Figure 10, Figure 10 is the cross-sectional view along BB1 (as shown in Figure 6) direction, the pseudo- grid structure (not indicating) of fin portion surface formation first in the first area I and the pseudo- grid structure (not indicating) of fin portion surface formation second in the second area II.
In the present embodiment, the fin for protruding from the substrate 400 of first area I is the first fin 410, and the fin for protruding from the substrate 400 of second area II is the second fin 420.Accordingly, in the step of forming described first pseudo- grid structure and the second pseudo- grid structure, the first pseudo- grid structure (not indicating) is formed on the surface of the first fin 410 and the second pseudo- grid structure (not indicating) is formed on the surface of the second fin 420.
The first pseudo- grid structure and the second pseudo- grid structure are that the first grid structure and second grid structure being subsequently formed take up space position.
In the present embodiment, the described first pseudo- grid structure is across the surface of the first fin 410 and covers the atop part surface of the first fin 410 and sidewall surfaces, including gate oxide 411 and the first pseudo- gate electrode layer 413 on the surface of the gate oxide 411；Described second pseudo- grid structure is across the surface of the second fin 420 and covers the atop part surface of the second fin 420 and sidewall surfaces, including pseudo- gate oxide 421 and the second pseudo- gate electrode layer 423 on the surface of pseudo- gate oxide 421.
Specifically, the step of forming described first pseudo- grid structure and the second pseudo- grid structure includes：Form the pseudo- gate oxidation films of the covering fin 420 of the first fin 410 and second；Pseudo- gate electrode film is formed on the pseudo- gate oxidation films surface；Planarization process is carried out to the pseudo- gate electrode film；The first graph layer 510 is formed on the pseudo- gate electrode film surface；It is mask with first graph layer 510, etch the pseudo- gate electrode film and pseudo- gate oxidation films, gate oxide 411 is formed on the surface of the first fin 410, the first pseudo- gate electrode layer 413 is formed on the surface of gate oxide 411, pseudo- gate oxide 421 is formed on the surface of the second fin 420, the second pseudo- gate electrode layer 423 is formed on the pseudo- surface of gate oxide 421；Remove first graph layer 510.
In the present embodiment, first graph layer 510 is hard mask layer, and the material of first graph layer 510 is silicon nitride.
The material of the gate oxide 411 and pseudo- gate oxide 421 is silica.The material of the described first pseudo- pseudo- gate electrode layer 423 of gate electrode layer 413 and second can be polysilicon, silica, silicon nitride, silicon oxynitride, carborundum, carbonitride of silicium, carbon silicon oxynitride or amorphous carbon.In the present embodiment, the material of the described first pseudo- pseudo- gate electrode layer 423 of gate electrode layer 413 and second is polysilicon.
It should be noted that, described first pseudo- grid structure also includes the first barrier layer 412 being located between the pseudo- gate electrode layer 413 of the gate oxide 411 and first, and the described second pseudo- grid structure also includes the second barrier layer 422 being located between the pseudo- gate electrode layer 423 of the pseudo- gate oxide 421 and second.
First barrier layer 412 is used in subsequent etching processes, and the gate oxide 411 is played a protective role, it is to avoid follow-up etching technics causes damage to the gate oxide 411.
The material on the barrier layer 422 of the first barrier layer 412 and second can be titanium nitride or silicon nitride.In the present embodiment, the material on the barrier layer 422 of the first barrier layer 412 and second is titanium nitride.
In the present embodiment, the technique for forming the barrier layer 422 of the first barrier layer 412 and second is atom layer deposition process.The technological parameter of the atom layer deposition process includes：The presoma being passed through into ald room is the presoma of titaniferous and nitrogen, and technological temperature is 400 degrees Celsius to 600 degrees Celsius, and pressure is 5 millitorrs to 100 millitorrs, and frequency of depositing is 20 times to 100 times.
It should be noted that the thickness on the barrier layer 422 of the first barrier layer 412 and second is unsuitable blocked up, it is also unsuitable excessively thin.If the thickness on the barrier layer 422 of the first barrier layer 412 and second is excessively thin, first barrier layer 412 is not obvious to the protecting effect of the gate oxide 411 in subsequent etching processes；The height of the thickness effect subsequent metal grid structure on the barrier layer 422 of the first barrier layer 412 and second, therefore the thickness on the first barrier layer 412 and the second barrier layer 422 is unsuitable blocked up.Therefore, in the present embodiment, the thickness on the barrier layer 422 of the first barrier layer 412 and second isExtremely
With reference to reference to Figure 11, it is necessary to illustrate, after the pseudo- grid structure of formation described first and the second pseudo- grid structure, the manufacture method also includes：In the described first pseudo- grid structure side wall formation first area the first side wall layer 414, in the described second pseudo- grid structure side wall formation second area the first side wall layer 424.
The material of the first area the first side wall layer 414 and second area the first side wall layer 424 can be silica, silicon nitride, carborundum, carbonitride of silicium, carbon silicon oxynitride, silicon oxynitride, boron nitride or boron carbonitrides, and the first area the first side wall layer 414 and second area the first side wall layer 424 can be single layer structure or laminated construction.In the present embodiment, the first area the first side wall layer 414 and second area the first side wall layer 424 are single layer structure, and the material of the first area the first side wall layer 414 and second area the first side wall layer 424 is silicon nitride.
With reference to Figure 12 is referred to, the manufacture method also includes：First area second sidewall layer 415 is formed on 414 surface of first area the first side wall layer, second area second sidewall layer 425 is formed on 424 surface of second area the first side wall layer；First area stressor layers 416 are formed in the first fin 410 of the described first pseudo- grid structure both sides, second area stressor layers 426 are formed in the second fin 420 of the described second pseudo- grid structure both sides；First area source region or drain region (not shown) are formed in the first area stressor layers 416, second area source region or drain region (not shown) are formed in the second area stressor layers 426.
The material of the first area second sidewall layer 415 and second area second sidewall layer 425 can be silica, silicon nitride, carborundum, carbonitride of silicium, carbon silicon oxynitride, silicon oxynitride, boron nitride or boron carbonitrides, and the first area second sidewall layer 415 and second area second sidewall layer 425 can be single layer structure or laminated construction.In the present embodiment, the first area second sidewall layer 415 and second area second sidewall layer 425 are single layer structure, and the material of the first area second sidewall layer 415 and second area second sidewall layer 425 is silicon nitride.
With reference to Figure 13, in semiconductor substrate surface formation dielectric layer 460, the dielectric layer 460 flushes with the described first pseudo- grid structure and the second pseudo- grid structure and exposes the described first pseudo- pseudo- gate electrode layer 423 of gate electrode layer 413 and second.
In the present embodiment, the dielectric layer 460 is laminated construction, including positioned at semiconductor substrate surface first medium layer 440, and the second dielectric layer 450 positioned at 440 surface of first medium layer.
First medium layer 440 and the material of the second dielectric layer 450 are insulating materials, for example, silica, silicon nitride, silicon oxynitride, silicon oxide carbide, carbonitride of silicium or carbon silicon oxynitride.In the present embodiment, the material of the first medium layer 440 and the second dielectric layer 450 is silica.Wherein, because formation process is different, the consistency of the second dielectric layer 450 is more than the consistency of first medium layer 440, so as to during the flatening process of the second dielectric layer 450 is formed, can preferably improve the surface flatness of the second dielectric layer 450.
It should be noted that before the dielectric layer 460 is formed, in addition to：In semiconductor substrate surface formation etching barrier layer 430, the etching barrier layer 430 also covers the described first pseudo- grid body structure surface and the second pseudo- grid body structure surface.
The etching barrier layer 430 is used for as the etching stop layer in the etching technics of subsequent touch hole, and is used as the stop position of subsequent planarization technique.In the present embodiment, the material of the etching barrier layer 430 is silicon nitride.
Specifically, the step of forming dielectric layer 460 includes：Formed after etching barrier layer 430, full first medium film is filled on semiconductor base between the fin and fin, the first medium film also covers the described first pseudo- grid structure and the second pseudo- grid structure, and higher than the described first pseudo- top of gate electrode layer 413 and the second pseudo- top of gate electrode layer 423 at the top of the first medium film；The first medium film is planarized until exposing the top surface of etching barrier layer 430；It is etched back to remove the first medium film of segment thickness to form first medium layer 440；Second medium film is formed on 440 surface of first medium layer, the second medium film also covers the described first pseudo- grid structure and the second pseudo- grid body structure surface, and higher than the described first pseudo- top of gate electrode layer 413 and the second pseudo- top of gate electrode layer 423 at the top of the second medium film；The second medium film is planarized until exposing the described first pseudo- top surface of gate electrode layer 413 and the second pseudo- top surface of gate electrode layer 423, to form second dielectric layer 450.
It should be noted that, while the second medium film is planarized, the etching barrier layer 430 for being located at the described first pseudo- top of gate electrode layer 413 and the second pseudo- top of gate electrode layer 423 is removed, the top of the second dielectric layer 450 to be formed is flushed with the described first pseudo- pseudo- top of gate electrode layer 423 of gate electrode layer 413 and second.
With reference to Figure 14, the described first pseudo- gate electrode layer 413 (as shown in figure 13) is removed, the first opening 600 is formed in the dielectric layer 460.
In the present embodiment, the technique being combined using dry etch process, wet etching or dry etch process and wet etching, etching removes the described first pseudo- gate electrode layer 413, because the etching technics has higher etching selection ratio to the described first pseudo- gate electrode layer 413, that is, the etching technics is more than the etch rate to the dielectric layer 460 to the etch rate of the described first pseudo- gate electrode layer 413, so as to which when etching removes the described first pseudo- gate electrode layer 413, the loss to the dielectric layer 460 can be reduced.
With reference to Figure 15, in the side wall formation compensation side wall 432 of the described first opening 600.
After the pseudo- grid structure of etching technics formation first, the gate oxide 411 as the first grid structure being subsequently formed a part, but the etching technics easily causes damage to the gate oxide 411, and damage field is close to the trench edges area of device, by forming the compensation side wall 432 in the described first 600 side walls of opening, it is subsequently formed after device, the gate oxide 411 being damaged is covered by the compensation side wall 432, the length of device channel region is less than the length of the gate oxide 411, that is, the effective gate oxide of the gate oxide 411 being damaged not above channel region, so as to avoid the gate oxide 411 being damaged from producing harmful effect to the electric property of semiconductor devices, and then it is improved the electric property for the semiconductor devices to be formed.
Specifically, include the step of 600 side wall formation compensation side wall 432 of the described first opening：In the surface of gate oxide 411, the first 600 side walls of opening, the second pseudo- top surface of gate electrode layer 423 formation compensation side wall film, the compensation side wall film also covers the top surface of dielectric layer 460；The compensation side wall film for removing the top surface of dielectric layer 460, the surface of gate oxide 411 and the second pseudo- top surface of gate electrode layer 423 using being etched without mask etching technique, in first opening sidewalls 600 formation compensation side wall 432.
It should be noted that the described first pseudo- grid structure also includes the first barrier layer 412 being located between the pseudo- gate electrode layer 413 of the gate oxide 411 and first.Accordingly, in the step of forming the compensation side wall film, the compensation side wall film is formed at the surface of the first barrier layer 412 of 600 bottoms of the first opening；In the step of etching the compensation side wall film, etching removes the compensation side wall film on the surface of the first barrier layer 412.
The material of the compensation side wall 432 can be silicon nitride or silica.
It should be noted that; in order to reduce the etching technics to form compensation side wall 432; damage to the gate oxide 411; the material of the compensation side wall 432 is different from the material on first barrier layer 412; so that the etching technics is more than the etch rate to first barrier layer 412 to the etch rate of the compensation side wall film, and then realize the protecting effect of 412 pairs of the first barrier layer gate oxide 411.
Specifically, when the material on first barrier layer 412 is titanium nitride, the material of the compensation side wall 432 is silicon nitride；When the material on first barrier layer 412 is silicon nitride, the material of the compensation side wall 432 is silica.
In the present embodiment, the material on first barrier layer 412 is titanium nitride, therefore, and the material of the compensation side wall 432 is silicon nitride.
In the present embodiment, the technique for etching the compensation side wall film is dry plasma etch technique.
In the present embodiment, the technique for forming the compensation side wall film is atom layer deposition process.The technological parameter of the atom layer deposition process includes：The presoma being passed through into ald room is containing SiH2Cl2And NH3Presoma, technological temperature be 350 degrees Celsius to 600 degrees Celsius, pressure be 1 millitorr to 50 millitorrs, frequency of depositing be 10 times to 50 times.
It should be noted that the thickness of the compensation side wall 432 is unsuitable blocked up, it is also unsuitable excessively thin.If the thickness of the compensation side wall 432 is excessively thin, formed after device, the compensation side wall 432 is difficult to be completely covered the part gate oxide 411 being damaged, that is, the part gate oxide 411 being damaged is still effective gate oxide above device channel region, so as to be easily reduced the electric property of device；In addition, the follow-up filling metal in the described first opening 600, if the thickness of the compensation side wall 432 is blocked up, easily influences the formation of follow-up gate electrode layer and the length of channel region, so as to influence the electric property of device to form gate electrode layer.Therefore, in the present embodiment, the compensation thickness of side wall 432 isExtremely
With reference to the described second pseudo- grid structure referring to figures 16 to Figure 18, is removed, the second opening 610 is formed in the dielectric layer 460.
Specifically, the step of removing the described second pseudo- grid structure includes：The described second pseudo- gate electrode layer 423 (as shown in figure 15) is removed, the second opening 610 is formed in the dielectric layer 460；Remove the second barrier layer 422 (as shown in figure 16) of 610 bottoms of the second opening；Remove the pseudo- gate oxide 421 (as shown in figure 17) of 610 bottoms of the second opening.
The step of below with reference to accompanying drawing to removing the described second pseudo- grid structure, is described in detail.
With reference to Figure 16, the described second pseudo- gate electrode layer 423 (as shown in figure 15) is removed, the second opening 610 is formed in the dielectric layer 460.
Remove after the described second pseudo- gate electrode layer 423, locus is provided for the follow-up formation gate electrode layer in the described second opening 610.
In the present embodiment, the technique being combined using dry etch process, wet etching or dry etch process and wet etching, etching removes the described second pseudo- gate electrode layer 423, because the etching technics has higher etching selection ratio to the described second pseudo- gate electrode layer 423, that is, the etching technics is more than the etch rate to the dielectric layer 460 to the etch rate of the described second pseudo- gate electrode layer 423, so as to which when etching removes the described second pseudo- gate electrode layer 423, the loss to the dielectric layer 460 can be reduced.
With reference to Figure 17, the second barrier layer 422 (as shown in figure 16) of 610 bottoms of the second opening is removed.
In the present embodiment, while removing the second barrier layer 422 of second open bottom 610, remove the first barrier layer 412 (as shown in figure 16) of 600 bottoms of the first opening, that is, in the processing step with along with, the barrier layer 422 of the first barrier layer 412 and second is removed.
First barrier layer 412 before the gate dielectric layer of the first area I and second area II is formed, removes the barrier layer 422 of the first barrier layer 412 and second as the etching stop layer for the etching technics for forming the compensation side wall 432.
In the present embodiment, in order to reduce damage of the technique for removing the barrier layer 422 of the first barrier layer 412 and second to the gate oxide 411, the barrier layer 422 of first barrier layer 412 and second is removed using wet-etching technology, the etching solution that the wet-etching technology is used for ammoniacal liquor, hydrogen peroxide and water mixed solution.
With reference to Figure 18, the pseudo- gate oxide 421 (as shown in figure 17) of 610 bottoms of the second opening is removed.
It should be noted that the first area I is used to form peripheral devices (for example：Input/output device), the second area II is used to form core devices, the operating voltage of core devices is smaller than the operating voltage of peripheral devices, the problems such as to prevent electrical breakdown, when the operating voltage of device is bigger, it is required that the thickness of the gate dielectric layer of device is thicker, that is to say, that the thickness of the gate dielectric layer for the second area II being subsequently formed is less than the thickness of the gate dielectric layer of first area I.For this, in the present embodiment, before the gate dielectric layer of second area II is formed, the pseudo- gate oxide 421 is first removed, so that the thickness for the peripheral devices gate dielectric layer (not indicating) being subsequently formed is more than the thickness of core devices gate dielectric layer (not indicating).
Specifically, the step of removing pseudo- gate oxide 421 includes：In semiconductor substrate surface formation second graph layer 520, the covering surface of 411 and first fin of gate oxide 410 of second graph layer 520 simultaneously exposes the surface of pseudo- gate oxide 421；It is mask with second graph layer 520, the pseudo- gate oxide 421 for removing 610 bottoms of the first opening is etched using dry etch process, until exposing the surface of the second fin 420；Remove the second graph layer 520.
With reference to Figure 19, on the surface of gate oxide 411, formation gate dielectric layer (not shown) on the side wall and the bottom of the second 610 (as shown in figure 18) of opening and side wall of side wall 432 is compensated；The filling metal level (not shown) in the described first 600 (as shown in figure 17) of opening and the second opening 610.
In the present embodiment, gate oxide 411, gate dielectric layer and metal level in the described first opening 600 constitute first grid structure 651, and the gate dielectric layer and metal level in the described second opening 610 constitute second grid structure 652.
In the present embodiment, the first grid structure 651 includes the first gate dielectric layer 612 and the first gate electrode layer 614 on first gate dielectric layer 612 of the covering atop part surface of the first fin 410 and sidewall surfaces across first fin 410；The second grid structure 652 includes the second gate dielectric layer 622 and the second gate electrode layer 624 on second gate dielectric layer 622 of the covering atop part surface of the second fin 420 and sidewall surfaces across second fin 420
The first area I is used to form peripheral devices, the second area II is used to form core devices, therefore, the gate oxide 411 and first gate dielectric layer 612 as peripheral devices gate dielectric layer, second gate dielectric layer 622 as core devices gate dielectric layer.In the present embodiment, the material of first gate dielectric layer 612 and second gate dielectric layer 622 is high-k gate dielectric material, wherein, high-k gate dielectric material is referred to, relative dielectric constant is more than the gate dielectric material of silica relative dielectric constant, and high-k gate dielectric material can be HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、ZrO2Or Al2O3。
The material of the metal level is Al, Cu, Ag, Au, Pt, Ni, Ti or W.In the present embodiment, the material of the metal level is W.
In the present embodiment, formed on the surface of gate oxide 411, the bottom of first 600 (as shown in figure 17) side walls of opening and the second 610 (as shown in figure 18) of opening and side wall after gate dielectric layer, formed on the gate dielectric layer before metal level, the step of forming the first grid structure 651 and second grid structure 652 also includes：Work-function layer (not indicating) is formed on the gate dielectric layer surface.
The first grid structure 651 also includes：The first work-function layer 613 between first gate dielectric layer 612 and first gate electrode layer 614, the threshold voltage for adjusting peripheral devices；The second grid structure 652 also includes：The second work-function layer 623 between second gate dielectric layer 622 and second gate electrode layer 624, the threshold voltage for adjusting the core devices.
In the present embodiment, when the first area I and second area II are N-type region, the work-function layer is N-type work function material；When the first area I and second area II is p type island regions, the work-function layer is p-type work function material.
Specifically, the first area I and second area II are N-type region, and the work-function layer is N-type work function material, and N-type work function material workfunction range is 3.9ev to 4.5ev, for example, 4ev, 4.1ev or 4.3ev.The work-function layer is single layer structure or laminated construction, and the material of the work-function layer includes the one or more in TiAl, TaAlN, TiAlN, MoN, TaCN and AlN.In the present embodiment, the material of the work-function layer is TiAl；Accordingly, the material of the work-function layer 623 of the first work-function layer 613 and second is TiAl.
Or, the first area I and second area II are p type island region, and the work-function layer is p-type work function material, and p-type work function material workfunction range is 5.1ev to 5.5ev, for example, 5.2ev, 5.3ev or 5.4ev.The work-function layer is single layer structure or laminated construction, and the material of the work-function layer includes the one or more in Ta, TiN, TaN, TaSiN and TiSiN.In the present embodiment, the material of the work-function layer is TiN；Accordingly, the material of the work-function layer 623 of the first work-function layer 613 and second is TiN.
Specifically, the step of forming the first grid structure 651 and second grid structure 652 includes：The surface of gate oxide 411, the side wall for compensating side wall 432, the second 610 (as shown in figure 18) bottoms of opening and the side wall formation gate dielectric layer of the second opening 610 in described first 600 (as shown in figure 18) bottoms of opening, the gate dielectric layer also cover the surface of dielectric layer 460；Work-function layer is formed on the gate dielectric layer surface；Higher than the top of dielectric layer 460 at the top of the work-function layer forming metal layer on surface, the full opening 610 of first opening 600 and second of metal level filling and the metal level；Grinding removes the metal level higher than the top of dielectric layer 460, forms first gate electrode layer 614 on the work-function layer surface of the first area I, the second gate electrode layer 624 is formed on the work-function layer surface of the second area II.
It should be noted that, while grinding removes the metal level higher than the top of dielectric layer 460, also grinding removes the gate dielectric layer and work-function layer higher than the top of dielectric layer 460, the first gate dielectric layer 612 positioned at the surface of gate oxide 411 and the first 600 side walls of opening is formed in the first area I, and the first work-function layer 613 positioned at the surface of the first gate dielectric layer 612, it is located at the described second 610 side walls of opening and the second gate dielectric layer 622 of bottom in the second area II formation, and the second work-function layer 623 positioned at the surface of the second gate medium 622.
It should be noted that, interface performance in order to improve between the first grid structure 651 and first fin 410, between the second grid structure 652 and second fin 420, before the gate dielectric layer 622 of the first gate dielectric layer 612 and second is formed, the manufacture method also includes：The first boundary layer 611 is formed on the surface of gate oxide 411 of the described first 600 bottoms of opening, second interface layer 621 is formed on the surface of the second fin 420 of the described second 610 bottoms of opening；The step of forming the gate dielectric layer includes：The surface of the first boundary layer 611, the first 600 side walls of opening, the surface of second interface layer 621 of the second 610 bottoms of opening and the second 610 side walls of opening in the described first 600 bottoms of opening form the gate dielectric layer.
Correspondingly, the embodiment of the present invention also provides a kind of semiconductor structure.
Please continue to refer to Figure 19, the schematic diagram of the embodiment of semiconductor structure one of the present invention is shown.The semiconductor structure includes：
Semiconductor base, the semiconductor base includes substrate 400, and protrudes from the fin of the substrate 400, and the substrate 400 includes first area I and second area II；
Grid structure, including the first grid structure 651 on the fin of the first area I, and the second grid structure 652 on the fin of the second area II；
Side wall 432 is compensated, positioned at the sidewall surfaces of the first grid structure 651；
Source region or drain region, including first area source region or drain region (not shown) in the both sides fin of first grid structure 651, and second area source region or drain region (not shown) in the both sides fin of second grid structure 652；
Dielectric layer 460, covers the sidewall surfaces of the first grid structure 651 and second grid structure 652 and is flushed with the first grid structure 651 and second grid structure 652.
In the present embodiment, the fin for protruding from the substrate 400 of first area I is the first fin 410, and the fin for protruding from the substrate 400 of second area II is the second fin 420.
In the present embodiment, the first area I is used to form peripheral devices (for example：Input/output device), the second area II is used to form core devices.The first area I can be N-type region or p type island region, and the second area II can be N-type region or p type island region, and the first area I is identical with the type of second area II.
The material of the substrate 400 is silicon, germanium, SiGe, carborundum, GaAs or gallium indium, and the substrate 400 can also be the silicon substrate on insulator or the germanium substrate on insulator；The material of the fin 420 of first fin 410 and second includes silicon, germanium, SiGe, carborundum, GaAs or gallium indium.In the present embodiment, the substrate 400 is silicon substrate, and the material of the fin 420 of the first fin 410 and second is silicon.
The first grid structure 651 includes the gate oxide 411, the first gate dielectric layer 612 positioned at the surface of gate oxide 411, the first work-function layer 613 positioned at the surface of the first gate dielectric layer 612 across the surface of the first fin 410 and the covering atop part surface of the first fin 410 and sidewall surfaces, and the first gate electrode layer 614 positioned at the surface of the first work-function layer 613；The second grid structure 652 includes the second gate dielectric layer 622, the second work-function layer 623 positioned at the surface of the second gate dielectric layer 622 across the surface of the second fin 420 and the covering atop part surface of the second fin 420 and sidewall surfaces, and the second gate electrode layer 624 positioned at the surface of the second work-function layer 623.
It should be noted that the interface performance in order to improve between the first grid structure 651 and first fin 410, between the second grid structure 652 and second fin 420, the first grid structure 651 also includes：The first boundary layer 611 between the gate dielectric layer 612 of gate oxide 411 and first；The second grid structure 652 also includes：Second interface layer 621 between the gate dielectric layer 622 of the second fin 420 and second.
The material of the compensation side wall 432 is silicon nitride or silica.In the present embodiment, the material of the compensation side wall 432 is silicon nitride.
It should be noted that the thickness of the compensation side wall 432 is unsuitable blocked up, it is also unsuitable excessively thin.The gate oxide 411 includes the subregion being damaged, if the thickness of the compensation side wall 432 is excessively thin, the compensation side wall 432 is difficult to be completely covered the part gate oxide 411 being damaged, the part gate oxide 411 being damaged is still effective gate oxide above device channel region, so as to be easily reduced the electric property of device；If the thickness of the compensation side wall 432 is blocked up, the formation quality of the first grid structure 651 and the length of device channel region are easily influenceed, so as to influence the electric property of device.Therefore, in the present embodiment, the compensation thickness of side wall 432 isExtremely
In the present embodiment, the semiconductor structure also includes：First area the first side wall layer 414 positioned at compensation side wall 432 surface, positioned at the second area the first side wall layer 424 of the described second pseudo- grid structure side wall；First area second sidewall layer 415 positioned at 414 surface of first area the first side wall layer, the second area second sidewall layer 425 positioned at 424 surface of second area the first side wall layer；The first stressor layers 416 in first fin of both sides 410 of first grid structure 651, the second stressor layers 426 in second fin of both sides 420 of second grid structure 652, wherein, the first area source region or drain region are located in first stressor layers 416, and the second area source region or drain region are located in second stressor layers 426.
The gate oxide 411 has damage field, and damage field is close to the trench edges area of device, because the damage field of the gate oxide 411 is covered by the compensation side wall 432, that is the effective gate oxide 411 of damage field not above channel region, so as to avoid the damage field of the gate oxide 411 from having undesirable effect the electric property of semiconductor devices, and then improve the electric property of semiconductor devices.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art, without departing from the spirit and scope of the present invention, can be made various changes or modifications, therefore protection scope of the present invention should be defined by claim limited range.

Claims (20)

1. a kind of manufacture method of semiconductor structure, it is characterised in that including：
Semiconductor base is formed, the semiconductor base includes substrate, and protrudes from the fin of the substrate Portion, the substrate includes first area and second area；
Fin portion surface in the first area forms the first pseudo- grid structure and in the fin of the second area Surface forms the second pseudo- grid structure, wherein, the described first pseudo- grid structure includes gate oxide and the first pseudo- grid Electrode layer, the described second pseudo- grid structure includes pseudo- gate oxide and the second pseudo- gate electrode layer；
In semiconductor substrate surface formation dielectric layer, the dielectric layer and the described first pseudo- grid structure and Second pseudo- grid structure flushes and exposes the described first pseudo- gate electrode layer and the second pseudo- gate electrode layer；
The described first pseudo- gate electrode layer is removed, forming first in the dielectric layer is open；
In first opening sidewalls formation compensation side wall；
The described second pseudo- grid structure is removed, forming second in the dielectric layer is open；
On the gate oxide surface, compensate shape on the side wall and the bottom of the second opening and side wall of side wall Into gate dielectric layer；
Metal level is filled in the described first opening and the second opening.
2. the manufacture method of semiconductor structure as claimed in claim 1, it is characterised in that the compensation side wall Material be silicon nitride or silica.
3. the manufacture method of semiconductor structure as claimed in claim 1, it is characterised in that the compensation side wall Thickness isExtremely
4. the manufacture method of semiconductor structure as claimed in claim 1, it is characterised in that opened described first The step of mouth side wall formation compensation side wall, includes：The gate oxide surface, the first opening sidewalls, Second pseudo- gate electrode layer top surface formation compensation side wall film, the compensation side wall film, which is also covered, to be given an account of Matter layer top surface；
The dielectric layer top surface, gate oxide surface and the are removed using without mask etching technique etching The compensation side wall film of two pseudo- gate electrode layer top surfaces, in first opening sidewalls formation compensation side wall.
5. the manufacture method of semiconductor structure as claimed in claim 4, it is characterised in that form the compensation The technique of side wall film is atom layer deposition process.
6. the manufacture method of semiconductor structure as claimed in claim 5, it is characterised in that the atomic layer deposition The technological parameter of product technique includes：The presoma being passed through into ald room is containing SiH2Cl2With NH3Presoma, technological temperature is 350 degrees Celsius to 600 degrees Celsius, and pressure is 1 millitorr to 50 Millitorr, frequency of depositing is 10 times to 50 times.
7. the manufacture method of semiconductor structure as claimed in claim 4, it is characterised in that etching removes described The compensation side wall film of the pseudo- gate electrode layer top surface of dielectric layer top surface, gate oxide surface and second Technique be dry plasma etch technique.
8. the manufacture method of semiconductor structure as claimed in claim 1, it is characterised in that in firstth area The pseudo- grid structure of fin portion surface formation first in domain is simultaneously pseudo- in the fin portion surface formation second of the second area In the step of grid structure, the described first pseudo- grid structure is also included positioned at the gate oxide and the first pseudo- grid The first barrier layer between electrode layer, the described second pseudo- grid structure also includes being located at the pseudo- gate oxide And second the second barrier layer between pseudo- gate electrode layer, wherein, first barrier layer and second stops Layer is different from the material of the compensation side wall.
9. the manufacture method of semiconductor structure as claimed in claim 8, it is characterised in that described first stops Layer and the material on the second barrier layer are titanium nitride or silicon nitride.
10. the manufacture method of semiconductor structure as claimed in claim 8, it is characterised in that described first stops Layer and the thickness on the second barrier layer areExtremely
11. the manufacture method of semiconductor structure as claimed in claim 8, it is characterised in that form described first The technique on barrier layer and the second barrier layer is atom layer deposition process.
12. the manufacture method of semiconductor structure as claimed in claim 11, it is characterised in that the atomic layer deposition The technological parameter of product technique includes：Before the presoma being passed through into ald room is titaniferous and nitrogen Drive body, technological temperature be 400 degrees Celsius to 600 degrees Celsius, pressure be 5 millitorrs to 100 millitorrs, Frequency of depositing is 20 times to 100 times.
13. the manufacture method of semiconductor structure as claimed in claim 8, it is characterised in that remove described second The step of pseudo- grid structure, includes：The described second pseudo- gate electrode layer is removed, the is formed in the dielectric layer Two openings；Remove the second barrier layer of second open bottom；Remove second open bottom Pseudo- gate oxide；
In the step of removing the second barrier layer of second open bottom, first open bottom is removed The first barrier layer.
14. the manufacture method of semiconductor structure as claimed in claim 13, it is characterised in that remove described first The technique on barrier layer and the second barrier layer is wet-etching technology.
15. the manufacture method of semiconductor structure as claimed in claim 14, it is characterised in that the wet etching The etching solution of technique is the mixed solution of ammoniacal liquor, hydrogen peroxide and water.
16. the manufacture method of semiconductor structure as claimed in claim 1, it is characterised in that the manufacture method Also include：Fin portion surface in the first area forms the first pseudo- grid structure, in the second area The pseudo- grid structure of fin portion surface formation second after, semiconductor substrate surface formation dielectric layer it Before, in the described first pseudo- grid structure side wall formation first area the first side wall layer, in the described second pseudo- grid Structure side wall formation second area the first side wall layer；
In first area the first side wall layer surface formation first area second sidewall layer, described second Area first side parietal layer surface forms second area second sidewall layer；
First area stressor layers are formed in the fin of the described first pseudo- grid structure both sides, it is pseudo- described second Second area stressor layers are formed in the fin of grid structure both sides；
First area source region or drain region are formed in the first area stressor layers, should in the second area Second area source region or drain region are formed in power layer.
17. a kind of semiconductor structure, it is characterised in that including：
Semiconductor base, the semiconductor base includes substrate, and protrudes from the fin of the substrate, The substrate includes first area and second area；
Grid structure, including the first grid structure on the fin of the first area, and be located at Second grid structure on the fin of the second area；
Side wall is compensated, positioned at the sidewall surfaces of the first grid structure；
Source region or drain region, including the first area source region in the fin of first grid structure both sides or drain region, And the second area source region in the second grid structure both sides fin or drain region；
Dielectric layer, covers the sidewall surfaces of the first grid structure and second grid structure and with described the One grid structure and second grid structure are flushed.
18. semiconductor structure as claimed in claim 17, it is characterised in that the material of the compensation side wall is nitrogen SiClx or silica.
19. semiconductor structure as claimed in claim 17, it is characterised in that the compensation side wall thicknesses are Extremely
20. semiconductor structure as claimed in claim 17, it is characterised in that the semiconductor structure also includes： First area the first side wall layer positioned at the compensation side wall surface, positioned at the described second pseudo- grid structure side The second area the first side wall layer of wall；
Positioned at the first area second sidewall layer of the first area the first side wall layer surface, positioned at described the The second area second sidewall layer on two area first side parietal layer surfaces；
First area stressor layers in the described first pseudo- grid structure both sides fin, the first area source Area or drain region are located at the first area stressor layers, and the in the described second pseudo- grid structure both sides fin Two regional stresses layer, the second area source region or drain region are located in the second area stressor layers.
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CN111725068A (en) * 2019-03-22 2020-09-29 中芯国际集成电路制造(上海)有限公司 Method for forming semiconductor structure
CN113327857A (en) * 2020-02-28 2021-08-31 中芯国际集成电路制造（天津）有限公司 Semiconductor structure and forming method thereof

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