CN102299156B - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
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Abstract
In the invention, in the process of preparing a CMOS transistor by a Gate Replacement process (Replacement Gate or Gate last), after high-k Gate dielectric layers are formed in an NMOS device region and a PMOS device region, a first work function adjusting dielectric layer belonging to the NMOS region and a second work function adjusting dielectric layer belonging to the PMOS region are respectively formed so as to respectively adjust the threshold voltages of the NMOS device and the PMOS device.
Description
Technical field
The present invention relates generally to a kind of semiconductor device and manufacture method thereof, specifically, relate to a kind of high-k gate dielectric/metal gate device and manufacture method thereof based on gate replacement technique.
Background technology
Along with the development of semiconductor technology, there is more high-performance and the larger component density of more powerful integrated circuit requirement, and between all parts, element or size, size and the space of each element self also needs further to dwindle.The application of 22 nanometers and following technique lsi core technology has become the inexorable trend of integrated circuit development, is also one of problem that mainly semiconductor company and research organization competitively research and develop in the world.The cmos device grid engineering research that " high-k gate dielectric/metal gate " technology of take is core is most representative core process in 22 nanometers and following technology, and associated material, technique and structural research are in carrying out widely.At present, research for high-k gate dielectric/metal gate technique can probably be divided into both direction, grid technique and gate replacement technique before, before the source that is formed on of the grid of front grid technique, drain electrode generate, the formation of the grid of gate replacement technique is after source, drain electrode generate, and in this technique, grid does not need to bear very high annealing temperature.
In traditional gate replacement technique, typical technique comprises the false grid that form polysilicon or silicon nitride, and after source/drain electrode forms, false grid are etched away to form gate groove, in gate groove, deposit successively afterwards high-k gate dielectric and dual-metal gate electrode material, for dual-metal gate electrode material, the metal that need to form different work functions in the gate groove region of nMOS and pMOS device is in order to regulate the threshold voltage of device, but due to the complexity in metal etch process, be the integrated difficulty of having brought of CMOS integrated technique.
Therefore, need to propose based on threshold voltage rear grid technique, that can effectively regulate device, and the integrated relatively simple semiconductor device of its technique.
Summary of the invention
In view of the above problems, the invention provides a kind of semiconductor device, described device comprises: the Semiconductor substrate with territory, nmos area and PMOS region; Be formed at the source area and the drain region that in described Semiconductor substrate, belong to respectively territory, nmos area and PMOS region; The first grid heap superimposition being formed on territory, described nmos area is formed at the second gate stack on described PMOS region; Wherein, the described first grid is stacking comprises: the first boundary layer; Be formed at the first high-k gate dielectric layer on described the first boundary layer; The first work function being formed on described the first high-k gate dielectric layer regulates dielectric layer; Be formed at described the first work function and regulate the first metal gate electrode on dielectric layer; Described second gate stack comprises: second contact surface layer; Be formed at the second high-k gate dielectric layer on described second contact surface layer; The second work function being formed on described the second high-k gate dielectric layer regulates dielectric layer; Be formed at described the second work function and regulate the second metal gate electrode on dielectric layer; Wherein said the first work function regulates dielectric layer and the second work function to regulate dielectric layer to be formed by different materials, in order to regulate respectively the work function of described nmos device and PMOS device.
The present invention also provides the manufacture method of above-mentioned semiconductor device, and described method comprises: the Semiconductor substrate with territory, nmos area and PMOS region is provided; In described Semiconductor substrate, formation belongs to first boundary layer in territory, nmos area, false grid and side wall thereof, formation belongs to the second contact surface layer in PMOS region, false grid and side wall thereof, and form and belong to source area and the drain region in territory, nmos area and PMOS region respectively, and cover source area, the drain region formation interlayer dielectric layer in described NMOS and PMOS region in described Semiconductor substrate; Remove the false grid in territory, described nmos area and PMOS region, to form the first opening and the second opening; In described the first opening, form the first high-k gate dielectric layer that covers described the first boundary layer, and in described the second opening, form the second high-k gate dielectric layer that covers described second contact surface layer; On described the first high-k gate dielectric layer, form the first work function and regulate dielectric layer, on the second high-k gate dielectric layer, form the second work function and regulate dielectric layer; In described the first work function, regulate on dielectric layer and form the first metal gate electrode that fills up described the first opening, on described the second work function adjusting dielectric layer, form the second metal gate electrode that fills up described the second opening; Described device is processed, the first grid heap superimposition that belongs to territory, nmos area to form respectively belongs to the second gate stack in PMOS region, wherein said the first and second work functions regulate dielectric layer to be formed by different materials, in order to regulate respectively the work function of described nmos device and PMOS device.
By adopting device of the present invention, described device forms high K medium layer respectively on nmos device region and PMOS device area, and the work function of introducing different materials thereon regulates dielectric layer, so not only effectively regulated the threshold voltage of nmos device and PMOS device, and work function regulates dielectric layer to be formed by different dielectric materials, its easier selective etch, be conducive to carry out technology controlling and process, and alleviated the pressure to bimetal gate investigation of materials, in addition, because high-k gate dielectric layer is selected more stable dielectric material under high temperature, therefore in its material, metallic atom can not produce obvious degradation effect to the channel carrier mobility of device because of diffusion problem under certain annealing temperature.
Accompanying drawing explanation
Fig. 1-11 show the schematic diagram of each fabrication stage of semiconductor device according to an embodiment of the invention.
Embodiment
The present invention relates generally to a kind of semiconductor device and manufacture method thereof.Disclosing below provides many different embodiment or example to be used for realizing different structure of the present invention.Of the present invention open in order to simplify, hereinafter the parts of specific examples and setting are described.Certainly, they are only example, and object does not lie in restriction the present invention.In addition, the present invention can be in different examples repeat reference numerals and/or letter.This repetition is in order to simplify and object clearly, itself do not indicate the relation between discussed various embodiment and/or setting.In addition, the various specific technique the invention provides and the example of material, but those of ordinary skills can recognize the property of can be applicable to of other techniques and/or the use of other materials.In addition, First Characteristic described below Second Characteristic it " on " structure can comprise that the first and second Characteristics creations are for the direct embodiment of contact, also can comprise the embodiment of other Characteristics creation between the first and second features, such the first and second features may not be direct contacts.
With reference to Figure 11, Figure 11 shows according to the structural representation of the semiconductor device of the embodiment of the present invention.As shown in figure 11, described device comprises: the Semiconductor substrate 202 with territory, nmos area 204 and PMOS region 206; Be formed at the source area and the drain region 214,216 that in described Semiconductor substrate 202, belong to respectively territory, nmos area 204 and PMOS region 206; Be formed at the first grid stacking 300 on territory, described nmos area 204 and be formed at the second gate stack 400 on described PMOS region 206; Wherein, the described first grid stacking 300 comprises: the first boundary layer 208; The first high-k gate dielectric layer 224 on described the first boundary layer 208; The first work function on described the first high-k gate dielectric layer 224 regulates dielectric layer 226; Be formed at described the first work function and regulate the first metal gate electrode 230 on dielectric layer 226; Described second gate stack 400 comprises: second contact surface layer 208; The second high-k gate dielectric layer 224 on described second contact surface layer 208; The second work function on described the second high-k gate dielectric layer 224 regulates dielectric layer 228; Be formed at described the second work function and regulate the second metal gate electrode 230 on dielectric layer 228; The the wherein said the 1 and second work function regulates dielectric layer 228 to adopt different materials to form, in order to regulate respectively the work function of nmos device and PMOS device.
Preferably, described the first and second high-k gate dielectric layers 224 are selected more stable high K medium material under high temperature, metallic atom in its material can be because diffusion problem produces obvious degradation effect to the channel carrier mobility of device under certain annealing temperature, can be from comprising selects unit usually to form in the group of column element: HfO
2, HfSiO
x, HfON
x, HfZrO
x, HfSiON
x, HfLaO
x, LaAlO
xor its combination, this is only example, the present invention is not limited to this.The thickness of described the first and second high-k gate dielectric layers 224 is about 1-3nm.
Described the first work function regulates dielectric layer 226 and 224, the layer below it to form the electric charge of negative dipole or a large amount of positively chargeds, and to play the effect that regulates effective work function, described the first work function regulates dielectric layer to comprise: MgO
x, the oxide of rare earth and class thulium or its silicide, nitride, or its their combination, described the first work function regulates the example of dielectric layer to comprise: La
2o
3, Sc
2o
3, Gd
2o
3, MgO
x, or their silicide, nitride, or other rare earth oxides or its silicide, nitride etc., this is only example, the present invention is not limited to this.
Described the second work function regulates dielectric layer 228 and 224, the layer below it to form a positive dipole or a large amount of electronegative electric charge, to play the effect that regulates effective work function, described the second work function regulates dielectric layer to comprise: the oxide of other active metal elements except rare earth and class thulium or its silicide, nitride, described the second work function regulates the example of dielectric layer 228 to comprise: Al
2o
3, TiO
2, ZrO
2, HfAlO
x, HfTiO
x, TaO
x, HfTaO
x, or their silicide, nitride, or its combination, this is only example, the present invention is not limited to this.It is about 0.1-2nm that the described the 1 and second work function regulates the thickness of dielectric layer 228.Described the first and second metal gate electrodes 230 are one or more layers structure.
Below with reference to Fig. 1-11, describe manufacture and the realization of described embodiment in detail.
With reference to figure 1, provide and there are territory, nmos area 204 and PMOS region 206 Semiconductor substrate 202, and form boundary layer 208 thereon.
Specifically, first provide Semiconductor substrate 202.Described substrate 202 has been carried out and has been processed operation early stage, described processing operation comprises prerinse, forms well region and forms shallow channel isolation area, in the present embodiment, described substrate 202 is silicon substrate, in other embodiments, described substrate 202 can also comprise other compound semiconductors, as carborundum, GaAs, indium arsenide or indium phosphide.For example, according to the known designing requirement of prior art (p-type substrate or N-shaped substrate), substrate 202 can comprise various doping configurations.In addition, preferably, described substrate 202 comprises epitaxial loayer, and described substrate 202 also can comprise silicon-on-insulator (SOI) structure.
Then, form boundary layer 208 thereon.Boundary layer 208 can be formed directly on substrate 202.In the present embodiment, boundary layer 208 can be SiO
2, SiON or Si
3n
4.The thickness of boundary layer 208 is about 0.5-2nm, can use ald, chemical vapour deposition (CVD) (CVD), high-density plasma CVD, sputter or other suitable methods.Below be only as example, be not limited to this.
With reference to figure 2, on described boundary layer 208, form false grid 210.False grid 210 are sacrifice layer, can form false grid 210 by deposit spathic silicon on described boundary layer 208, and its thickness is about 30-200nm.Described false grid 210 can also form by deposition other materials, such as amorphous silicon etc.
With reference to figure 3, described boundary layer 208 and false grid 210 is graphical.By form mask layer (not shown) on described false grid 210, then utilize dry method or wet etching technique that described boundary layer 208 and false grid 210 is graphical, to form the first boundary layer 208 and the false grid 210 that belong to respectively first area 204, belong to second contact surface layer 208 and the false grid 210 of second area 206.
With reference to figure 4, formation belongs to the side wall 212 of the false grid in territory, nmos area 204, formation belongs to the side wall 212 of the false grid in PMOS region 206, and forms respectively source area and the drain region 214,216 that belongs to territory, nmos area 204 and PMOS region 206 in described Semiconductor substrate 202.
Described side wall 212 can be one or more layers structure, is the side wall of a three-decker in embodiments of the present invention.First in described first area 204 and second area 206, by the method for chemical deposition, for example Atomic layer deposition method or plasma reinforced chemical meteorology deposition, nitride layer, for example silicon nitride or silicon oxynitride, and utilize dry etching technology, the method of RIE for example, carry out graphically to form the first side wall 212-1, then, preferably, can carry out the Implantation in source/drain extension region and/or halo district, can pass through according to the transistor arrangement of expectation, inject p-type or N-shaped alloy or impurity to first area 204 and the substrate 202 of second area 206 and forming.Then, deposition oxide material on described device, as silicon dioxide, and utilizes dry etching technology, and for example the method for RIE, carries out graphically to form the second side wall 212-2.Afterwards, deposit another layer of nitride material on described device, as silicon nitride or silicon oxynitride, and utilize dry etching technology, for example the method for RIE, carries out graphically to form the 3rd side wall 212-3.Above sidewall structure and formation material thereof, method are only example, are only as example, are not limited to this.For simplified characterization, in description and legend after this, comprise that the three-decker side wall of described the first side wall 212-1, the second side wall 212-2, the 3rd side wall 212-3 is all described as side wall 212.
After forming side wall 212, carry out the Implantation of source area and drain region, can pass through according to the transistor arrangement of expectation, inject p-type or N-shaped alloy or impurity to first area 204 and the substrate 202 of second area 206 and forming, can be formed by the method that comprises photoetching, Implantation, diffusion and/or other appropriate process.
With reference to figure 5, on the substrate 202 between the side wall 212 of described first area 204 and the side wall 212 of second area 206, form internal layer dielectric layer (ILD) 218.First, deposition medium material, for example SiO on described device
2, then by its planarization, for example the method for CMP (chemico-mechanical polishing), removes the dielectric material on false grid 210, until expose the upper surface of false grid 210.Described internal layer dielectric layer 218 can be but be not limited to for example unadulterated silica (SiO
2), doping silica (as Pyrex, boron-phosphorosilicate glass etc.) and silicon nitride (Si
3n
4).Described internal layer dielectric layer 218 can be used methods such as chemical vapour deposition (CVD) (CVD), physical vapour deposition (PVD) (PVD), ald (ALD) and/or other suitable technique to form.
With reference to figure 6, remove the false grid 210 in territory, described nmos area and PMOS region, to form the first opening 220 and the second opening 222.In one embodiment, utilize dry method, as RIE, or wet etching technique, as comprise Tetramethylammonium hydroxide (TMAH), KOH or other suitable etch agent solutions, and described false grid 210 etchings are removed, thus the first opening 220 and second opening 222 of formation exposed interface layer 208.In another embodiment, can utilize dry method or wet etching technique further boundary layer 208 to be removed, form the first opening 220 and second opening 222 (not shown)s of the substrate that exposes first area 204 and second area 206, redeposited dielectric material then, in the first opening, form in the first boundary layer, the second opening and form second contact surface layer, described dielectric material can be SiO
2, SiON or Si
3n
4, to improve the quality of boundary layer, in this embodiment, the first and second boundary layers are formed at the inwall of opening.
With reference to figure 7, on described device, form high-k gate dielectric layer 224, can for example, by (deposit high K medium material on described device, compare with silica, the material with high-k) form, preferably, high K medium material is selected the dielectric material of stable performance under high temperature, metallic atom in its material can be because diffusion problem produces obvious degradation effect to the channel carrier mobility of device, as HfO under certain annealing temperature
2, HfSiO
x, HfON
x, HfZrO
x, HfSiON
x, HfLaO
x, LaAlO
xits combination and/or other suitable material, can form by chemical vapour deposition (CVD), ald (ALD) or other suitable methods, and its thickness is about 1-3nm.This is only example, and the present invention is not limited to this.
With reference to figure 8, on the high-k gate dielectric layer 224 in territory, described nmos area 204, form the first work function and regulate dielectric layer 226, and on the high-k gate dielectric layer 226 in described PMOS region 206, form the second work function adjusting dielectric layer 228.After forming high-k gate dielectric layer 224, can deposit the first work function adjusting dielectric layer 226 that belongs to territory, nmos area 204 thereon, described the first work function regulates dielectric layer 226 and 224, the layer below it to form the electric charge of negative dipole or a large amount of positively chargeds, described negative dipole or positive charge will play the effect that regulates effective work function, and described the first work function regulates dielectric layer to comprise: MgO
x, the oxide of rare earth and class thulium or its silicide, nitride, or their combination, described the first work function regulates the example of dielectric layer to comprise: La
2o
3, Sc
2o
3, Gd
2o
3, MgO
x, or their silicide, nitride, or other rare earth oxides and silicide and nitride etc., this is only example, the present invention is not limited to this.And on high-k gate dielectric layer 224, form the second work function belong to PMOS region 206 and regulate dielectric layer 228, described the second work function regulates dielectric layer 228 and 224, the layer below it to form a positive dipole or a large amount of electronegative electric charge, described positive dipole or negative electrical charge will play the effect that regulates effective work function, described the second work function regulates dielectric layer to comprise: the oxide that comprises other active metal elements except rare earth and class thulium or its silicide, nitride, described the second work function regulates the example of dielectric layer 228 to comprise: Al
2o
3, TiO
2, ZrO
2, HfAlO
x, HfTiO
x, TaO
x, HfTaO
x, or their silicide, nitride, or its combination, this is only example, the present invention is not limited to this.It is about 0.1-2nm that described the first and second work functions regulate the thickness of dielectric layer.Work function regulates dielectric layer 226,228 can adopt sputter, PLD, MOCVD, ALD, PEALD or other suitable methods.
With reference to figure 9-10, on described device, form and belong to respectively territory, nmos area 204 and PMOS region 206 metal gate electrodes 230.Described metal gate electrode 230 can be one or more layers structure, metal gate electrode on territory, nmos area 204 and PMOS region 206 can have identical or different material, preferred identical material, metal gate electrode is a two-layer structure in embodiments of the present invention, and the metal gate electrode on territory, nmos area 204 and PMOS region 206 has same material, first on described device, deposit a metal material layer 230-1, such as TiN etc., then on metal material layer 230-1, form and fill up described opening 220, another metal material layer 230-2 of 222, low resistive metal Al for example, Ti, TiAl, W etc., this is only example, the present invention is not limited to this.Described metal gate electrode can be from comprising selects unit usually to form in the group of column element: TiN, TaN, MoN, HfN, HfC, TaC, TiC, MoC, TiAlN, TaAlN, HfAlN, HfTbN, TaTbN, TaErN, TaYbN, TaSiN, TaHfN, TiHfN, HfSiN, MoSiN, MoAlN, RuTa
x, NiTa
x, polysilicon, metal silicide or its combination.
With reference to Figure 11, form respectively the second gate stack that the first grid heap superimposition belong to territory, nmos area belongs to PMOS region.Layer laminate patterning to previous formation, stacking 300 to form the grid of territory, nmos area device, and the grid stacking 400 of PMOS region device.The formation of grid stacking 300 and grid stacking 400 can be carried out one or many etching to previous layer laminate and complete.And then formed the semiconductor device according to the embodiment of the present invention.
The present invention is prepared in CMOS transistor process at gate replacement technique (Replacement gate or Gate last), after forming grid nmos device region and PMOS device area formation high-k gate dielectric layer, form respectively the second work function that belongs to the first work function adjusting dielectric layer in territory, nmos area and belong to PMOS region and regulate dielectric layer, wherein high-k gate dielectric layer is chosen under certain annealing temperature and can to the channel carrier mobility of device, produce the dielectric material of obvious degradation effect because of diffusion problem, and comprise the element that can regulate nmos device threshold voltage in the first work function adjusting dielectric layer, as La, Sc, Gd etc., the second work function regulates in dielectric layer and comprises the element that can regulate PMOS device threshold voltage, as Al, Ti etc., to regulate respectively nmos device, the threshold voltage of PMOS device, and owing to adopting dielectric material to form, its easier selective etching, be conducive to carry out technology controlling and process, and alleviated the pressure to bimetal gate investigation of materials.
Although describe in detail about example embodiment and advantage thereof, be to be understood that in the situation that do not depart from the protection range that spirit of the present invention and claims limit, can carry out various variations, substitutions and modifications to these embodiment.For other examples, when those of ordinary skill in the art should easily understand within keeping protection range of the present invention, the order of processing step can change.
In addition, range of application of the present invention is not limited to technique, mechanism, manufacture, material composition, means, method and the step of the specific embodiment of describing in specification.From disclosure of the present invention, as those of ordinary skill in the art, will easily understand, for the technique, mechanism, manufacture, material composition, means, method or the step that have existed or be about to develop at present later, wherein they carry out identical function or the identical result of acquisition cardinal principle of corresponding embodiment cardinal principle of describing with the present invention, according to the present invention, can apply them.Therefore, claims of the present invention are intended to these technique, mechanism, manufacture, material composition, means, method or step to be included in its protection range.
Claims (2)
1. a semiconductor device, comprising:
The Semiconductor substrate with territory, nmos area and PMOS region;
Be formed at the source area and the drain region that in described Semiconductor substrate, belong to respectively territory, nmos area and PMOS region;
The first grid heap superimposition being formed on the substrate of territory, described nmos area is formed at the second gate stack on the substrate of described PMOS region;
Wherein, the described first grid is stacking comprises: the first boundary layer; Be formed at the first high-k gate dielectric layer on described the first boundary layer; The first work function being formed on described the first high-k gate dielectric layer regulates dielectric layer; Be formed at described the first work function and regulate the first metal gate electrode on dielectric layer;
Described second gate stack comprises: second contact surface layer; Be formed at the second high-k gate dielectric layer on described second contact surface layer; The second work function being formed on described the second high-k gate dielectric layer regulates dielectric layer; Be formed at described the second work function and regulate the second metal gate electrode on dielectric layer;
Wherein said the first and second work functions regulate dielectric layer to be formed by different materials, in order to regulate respectively the work function of described nmos device and PMOS device; It is between 0.1-2nm that described the first and second work functions regulate the thickness of dielectric layer;
Described the first and second metal gate electrodes are one or more layers structure; In the group of described the first and second metal gate electrodes column element from comprising, select unit usually to form: TiN, TaN, MoN, HfN, HfC, TaC, TiC, MoC, TiAlN, TaAlN, HfAlN, HfTbN, TaTbN, TaErN, TaYbN, TaSiN, TaHfN, TiHfN, HfSiN, MoSiN, MoAlN, RuTa
x, NiTa
x, polysilicon, metal silicide or its combination;
In the group of described the first and second high-k gate dielectric layers column element from comprising, select unit usually to form: HfO
2, HfSiO
x, HfON
x, HfZrO
x, HfSiON
x, HfLaO
x, LaAlO
xor its combination, the metallic atom in described its material of the first and second high-k gate dielectric layers can not produce obvious degradation effect to the channel carrier mobility of device because of diffusion problem under certain annealing temperature; The thickness of described the first and second high-k gate dielectric layers is 1-3nm;
Described the first work function regulates the electric charge of dielectric layer and the formation of the interlayer below it negative dipole or a large amount of positively chargeds, to play the effect that regulates effective work function; Described the first work function regulates dielectric layer to comprise: MgO
x, the oxide of rare earth or class thulium or its silicide, nitride, or its combination;
Described the second work function regulates dielectric layer and the interlayer below it to form positive dipole or a large amount of electronegative electric charge, to play the effect that regulates effective work function; Described the second work function regulates dielectric layer to comprise: the oxide of other active metal elements except rare earth and class thulium or its silicide, nitride, and in the group of described the second work function adjusting dielectric layer column element from comprising, select unit usually to form: Al
2o
3, TiO
2, ZrO
2, HfAlO
x, HfTiO
x, TaO
x, HfTaO
x, or its silicide, nitride, or its combination.
2. manufacture a method for semiconductor device, described method comprises:
The Semiconductor substrate with territory, nmos area and PMOS region is provided;
In described Semiconductor substrate, formation belongs to first boundary layer in territory, nmos area, false grid and side wall thereof, formation belongs to the second contact surface layer in PMOS region, false grid and side wall thereof, and form and belong to source area and the drain region in territory, nmos area and PMOS region respectively, and cover source area, the drain region formation interlayer dielectric layer in described NMOS and PMOS region in described Semiconductor substrate;
Remove the false grid in territory, described nmos area and PMOS region, to form the first opening and the second opening;
In described the first opening, form the first high-k gate dielectric layer that covers described the first boundary layer, and in described the second opening, form the second high-k gate dielectric layer that covers described second contact surface layer;
On described the first high-k gate dielectric layer, form the first work function and regulate dielectric layer, on the second high-k gate dielectric layer, form the second work function and regulate dielectric layer;
In described the first work function, regulate on dielectric layer and form the first metal gate electrode that fills up described the first opening, on described the second work function adjusting dielectric layer, form the second metal gate electrode that fills up described the second opening;
Described device is processed, and the first grid heap superimposition that belongs to territory, nmos area to form respectively belongs to the second gate stack in PMOS region;
Wherein said the first and second work functions regulate dielectric layer to be formed by different materials, in order to regulate respectively the work function of described nmos device and PMOS device; It is between 0.1-2nm that described the first and second work functions regulate the thickness of dielectric layer;
Described the first and second metal gate electrodes are one or more layers structure; In the group of described the first and second metal gate electrodes column element from comprising, select unit usually to form: TiN, TaN, MoN, HfN, HfC, TaC, TiC, MoC, TiAlN, TaAlN, HfAlN, HfTbN, TaTbN, TaErN, TaYbN, TaSiN, TaHfN, TiHfN, HfSiN, MoSiN, MoAlN, RuTa
x, NiTa
x, polysilicon, metal silicide or its combination;
In the group of described the first and second high-k gate dielectric layers column element from comprising, select unit usually to form: HfO
2, HfSiO
x, HfON
x, HfZrO
x, HfSiON
x, HfLaO
x, LaAlO
xor its combination, the metallic atom in described its material of the first and second high-k gate dielectric layers can not produce obvious degradation effect to the channel carrier mobility of device because of diffusion problem under certain annealing temperature; The thickness of described the first and second high-k gate dielectric layers is 1-3nm;
Described the first work function regulates the electric charge of dielectric layer and the formation of the interlayer below it negative dipole or a large amount of positively chargeds, to play the effect that regulates effective work function; Described the first work function regulates dielectric layer to comprise: MgO
x, the oxide of rare earth or class thulium or its silicide, nitride, or its combination;
Described the second work function regulates dielectric layer and the interlayer below it to form positive dipole or a large amount of electronegative electric charge, to play the effect that regulates effective work function; Described the second work function regulates dielectric layer to comprise: the oxide of other active metal elements except rare earth and class thulium or its silicide, nitride, and in the group of described the second work function adjusting dielectric layer column element from comprising, select unit usually to form: Al
2o
3, TiO
2, ZrO
2, HfAlO
x, HfTiO
x, TaO
x, HfTaO
x, or its silicide, nitride, or its combination.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103456735A (en) * | 2012-06-05 | 2013-12-18 | 中芯国际集成电路制造(上海)有限公司 | Cmos device and manufacturing method thereof |
| CN103531540B (en) * | 2012-07-02 | 2016-06-08 | 中国科学院微电子研究所 | Semiconductor device manufacturing method |
| CN103545191B (en) * | 2012-07-16 | 2016-06-15 | 中国科学院微电子研究所 | Method for forming grid structure, method for forming semiconductor device and semiconductor device |
| US9064713B2 (en) | 2012-09-06 | 2015-06-23 | Infineon Technologies Austria Ag | Voltage regulator using N-type substrate |
| CN103681344A (en) * | 2012-09-26 | 2014-03-26 | 中芯国际集成电路制造(上海)有限公司 | Formation method of transistor |
| CN103871890B (en) * | 2012-12-18 | 2016-06-29 | 中芯国际集成电路制造(上海)有限公司 | Mos transistor and forming method thereof |
| CN104008973A (en) * | 2013-02-26 | 2014-08-27 | 中国科学院微电子研究所 | Method for manufacturing semiconductor device |
| CN104124144A (en) * | 2013-04-23 | 2014-10-29 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of semiconductor device |
| CN104124143B (en) * | 2013-04-23 | 2017-11-14 | 中芯国际集成电路制造(上海)有限公司 | The forming method of gate lateral wall layer |
| CN104425351A (en) * | 2013-09-11 | 2015-03-18 | 中国科学院微电子研究所 | Trench forming method and semiconductor device manufacturing method |
| CN104952798B (en) * | 2014-03-26 | 2018-07-20 | 中芯国际集成电路制造(上海)有限公司 | A kind of manufacturing method of semiconductor devices |
| KR102336033B1 (en) * | 2015-04-22 | 2021-12-08 | 에스케이하이닉스 주식회사 | Semiconductor device having buried gate structure and method for manufacturing the same, memory cell having the same and electronic device having the same |
| KR102455869B1 (en) * | 2015-12-23 | 2022-10-20 | 에스케이하이닉스 주식회사 | Semiconductor device having buried gate structure and method for manufacturing the same, memory cell having the same |
| CN111293118B (en) * | 2018-12-10 | 2023-07-04 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| US11735593B2 (en) | 2021-11-04 | 2023-08-22 | International Business Machines Corporation | Gate stack dipole compensation for threshold voltage definition in transistors |
| CN118073188B (en) * | 2024-04-18 | 2024-07-02 | 上海陛通半导体能源科技股份有限公司 | Multifunctional gate dielectric layer structure, semiconductor device with multifunctional gate dielectric layer structure and preparation method of semiconductor device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101027770A (en) * | 2004-09-27 | 2007-08-29 | 英特尔公司 | A metal gate electrode semiconductor device |
| CN101425479A (en) * | 2007-10-29 | 2009-05-06 | 台湾积体电路制造股份有限公司 | High-k dielectric metal gate device structure and method for forming the same |
| CN101533842A (en) * | 2008-03-12 | 2009-09-16 | 台湾积体电路制造股份有限公司 | Hybrid process for forming metal gates of mos devices |
| CN101714526A (en) * | 2008-10-06 | 2010-05-26 | 台湾积体电路制造股份有限公司 | Method for fabricating semiconductor device |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7807522B2 (en) * | 2006-12-28 | 2010-10-05 | Texas Instruments Incorporated | Lanthanide series metal implant to control work function of metal gate electrodes |
| US20080246099A1 (en) * | 2007-04-09 | 2008-10-09 | Ajith Varghese | Low temperature poly oxide processes for high-k/metal gate flow |
| JP5336814B2 (en) * | 2008-10-27 | 2013-11-06 | ルネサスエレクトロニクス株式会社 | Semiconductor device and manufacturing method thereof |
-
2010
- 2010-06-28 CN CN201010220686.7A patent/CN102299156B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101027770A (en) * | 2004-09-27 | 2007-08-29 | 英特尔公司 | A metal gate electrode semiconductor device |
| CN101425479A (en) * | 2007-10-29 | 2009-05-06 | 台湾积体电路制造股份有限公司 | High-k dielectric metal gate device structure and method for forming the same |
| CN101533842A (en) * | 2008-03-12 | 2009-09-16 | 台湾积体电路制造股份有限公司 | Hybrid process for forming metal gates of mos devices |
| CN101714526A (en) * | 2008-10-06 | 2010-05-26 | 台湾积体电路制造股份有限公司 | Method for fabricating semiconductor device |
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