CN103681344A - Formation method of transistor - Google Patents
Formation method of transistor Download PDFInfo
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- CN103681344A CN103681344A CN201210364951.8A CN201210364951A CN103681344A CN 103681344 A CN103681344 A CN 103681344A CN 201210364951 A CN201210364951 A CN 201210364951A CN 103681344 A CN103681344 A CN 103681344A
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66553—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using inside spacers, permanent or not
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
Abstract
A formation method of a transistor is provided. The formation method of the transistor includes the following steps that: a semiconductor substrate is provided, the surface of the semiconductor substrate is provided with a gate structure; a silicon oxide layer coating on the surfaces of the gate structure and the semiconductor substrate is formed; the silicon oxide layer on the surface of the semiconductor substrate is removed, a silicon nitride layer coating on the surfaces of the semiconductor substrate, the gate structure and the silicon oxide layer are formed; after the silicon nitride layer on the surface of the semiconductor substrate and the top of the gate structure is removed, first silicon nitride sidewalls are formed; and after the first silicon nitride sidewalls are formed, stress layers located at two sides of the gate structure are formed inside the semiconductor substrate. The transistor formed by using the method is stable in performance.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, relate in particular to a kind of transistorized formation method.
Background technology
Transistor is just being widely used at present as the most basic semiconductor device, and along with the raising of component density and the integrated level of semiconductor device, transistorized grid size becomes than in the past shorter; Yet transistorized grid size shortens and can make transistor produce short-channel effect, and then produces leakage current, finally affects the electric property of semiconductor device.At present, prior art mainly, by improving the stress of transistor channel region, to improve carrier mobility, and then improves transistorized drive current, reduces the leakage current in transistor.
The method that prior art improves the stress of transistor channel region is, in transistorized source/and drain region formation stressor layers, wherein, the material of the transistorized stressor layers of PMOS is SiGe (SiGe), the compression forming because of lattice mismatch between silicon and SiGe, thus the transistorized performance of PMOS improved; The material of the stressor layers of nmos pass transistor is carborundum (SiC), the tension stress forming because of lattice mismatch between silicon and carborundum, thereby the performance of raising nmos pass transistor.
Prior art has the cross-sectional view of the transistor forming process of stressor layers, as shown in Figure 1 to Figure 3, comprising:
Please refer to Fig. 1, Semiconductor substrate 10 is provided, described Semiconductor substrate 10 surfaces have grid structure 11.
Please refer to Fig. 2, the interior formation opening 12 of Semiconductor substrate 10 in described grid structure 11 both sides, the surface of the sidewall of described opening 12 and Semiconductor substrate 10 forms Sigma (Σ, sigma) shape.
Please refer to Fig. 3, in the interior formation stressor layers 13 of described opening 12, the material of described stressor layers 13 is SiGe or carborundum.
Yet the transistor with stressor layers forming with prior art easily produces leakage current, unstable properties.
The transistors with stressor layers please refer to the U.S. patent documents that publication number is US 2011256681A1 more.
Summary of the invention
The problem that the present invention solves is to provide a kind of transistorized formation method, makes formed transistor performance more stable.
For addressing the above problem, the invention provides a kind of transistorized formation method, comprising: Semiconductor substrate is provided, and described semiconductor substrate surface has grid structure; Form the silicon oxide layer that covers described grid structure and semiconductor substrate surface; Remove the silicon oxide layer of semiconductor substrate surface; After removing the silicon oxide layer of semiconductor substrate surface, form the silicon nitride layer that covers described Semiconductor substrate, grid structure and silicon oxide layer surface; Remove the silicon nitride layer at semiconductor substrate surface and grid structure top, form the first silicon nitride side wall; After forming the first silicon nitride side wall, in the Semiconductor substrate of grid structure both sides, form stressor layers.
Alternatively, the technique of the silicon oxide layer of described removal semiconductor substrate surface is the first anisotropic dry etch process, and the technique of the silicon nitride layer at described removal semiconductor substrate surface and grid structure top is the second anisotropic dry etch process.
Alternatively, described the first anisotropic dry etch process comprises the first main etching and the first main etching the first over etching afterwards; Described the second anisotropic dry etch process comprises the second over etching after the second main etching and the second main etching.
Alternatively, the gas of described the first main etching technique comprises CHF
3and He, the time is 5 seconds ~ 45 seconds.
Alternatively, the gas of described the second main etching technique comprises CF
4and O
2, the time is 10 seconds ~ 45 seconds.
Alternatively, the thickness of described silicon oxide layer is 10 dust-15 dusts, and the thickness of described silicon nitride layer is 50 dust-300 dusts.
Alternatively, the material of described stressor layers is SiGe or carborundum.
Alternatively, the sidewall of described stressor layers and semiconductor substrate surface are " Σ " type.
Alternatively, the formation technique of described stressor layers is: take grid structure and the first silicon nitride side wall is mask, adopt the dry etch process of anisotropic to form opening in the Semiconductor substrate of grid structure both sides, the sidewall of described opening is vertical with semiconductor substrate surface; Adopt opening described in anisotropic wet-etching technology etching, the sidewall of described opening is extended in Semiconductor substrate, make the sidewall of described opening and the surface of Semiconductor substrate be " Σ " shape; After described anisotropic dry etching, adopt selective epitaxial depositing operation to form stressor layers in described opening.
Alternatively, also comprise: after the wet-etching technology of described anisotropic, Semiconductor substrate, grid structure and the first silicon nitride side wall surface are cleaned, the cleaning fluid of described cleaning includes hydrofluoric acid.
Alternatively, described grid structure comprises: the gate dielectric layer of semiconductor substrate surface, be positioned at the gate electrode layer on described gate dielectric layer surface, and the mask layer that is positioned at gate electrode layer surface.
Alternatively, the material of described gate dielectric layer is high K dielectric material or silica, and the material of described gate electrode layer is polysilicon.
Alternatively, when the material of described gate dielectric layer is high K dielectric material, described grid structure also comprises: be positioned at the protection side wall of described gate dielectric layer and gate electrode layer both sides, the material of described protection side wall is silicon nitride.
Alternatively, when the material of described gate dielectric layer is high K dielectric material, after forming stressor layers, remove described gate electrode layer, and form metal gate electrode in the position of described gate electrode layer.
Alternatively, after forming stressor layers, in described Semiconductor substrate and grid structure both sides, form the second silicon nitride side wall.
Alternatively, after forming stressor layers, before forming the second silicon nitride side wall, remove the first silicon nitride side wall.
Alternatively, take described the second silicon nitride side wall and grid structure is mask, and counter stress layer carries out Implantation, forms source region and drain region.
Compared with prior art, technical scheme of the present invention has the following advantages:
At grid structure and semiconductor substrate surface, form after silicon oxide layer, remove the silicon oxide layer of semiconductor substrate surface, the silicon nitride layer of follow-up formation is directly contacted with Semiconductor substrate, avoided making to there is silicon oxide layer between formed the first silicon nitride side wall and Semiconductor substrate; And then, in the forming process of stressor layers, avoided being removed because cleaning makes the silicon oxide layer between the first silicon nitride side wall and Semiconductor substrate, and produced gap; Because formed the first silicon nitride side wall directly contacts with Semiconductor substrate, therefore when forming stressor layers, the material of stressor layers can not enter between the first silicon nitride side wall and Semiconductor substrate, has avoided the generation of leakage current, makes formed transistorized stable performance.
Accompanying drawing explanation
Fig. 1 to Fig. 3 is the cross-sectional view that prior art has the transistor forming process of stressor layers;
Fig. 4 and Fig. 5 are in the transistor grid structure of prior art, the cross-sectional view of the forming process of monox lateral wall and silicon nitride side wall;
Fig. 6 to Figure 13 is the cross-sectional view of transistorized forming process described in embodiments of the invention.
Embodiment
As stated in the Background Art, the transistor with stressor layers that prior art forms easily produces leakage current, unstable properties.
The present inventor finds through research, while thering is the transistor of stressor layers due to prior art formation, can between the side wall of grid structure and Semiconductor substrate, form gap, and in described gap, easily be packed into the material of stressor layers, cause transistor to produce leakage current.Concrete, in the transistor with stressor layers of prior art, grid structure 11(is as shown in Figure 1) comprising: the gate dielectric layer on Semiconductor substrate 10 surfaces, the gate electrode layer on gate dielectric layer surface, the monox lateral wall of gate dielectric layer and gate electrode layer both sides, and the silicon nitride side wall at gate dielectric layer, gate electrode layer and monox lateral wall two ends; Wherein, the forming process of described monox lateral wall and silicon nitride side wall, as shown in Fig. 4 to Fig. 5, comprising:
Please refer to Fig. 4, Semiconductor substrate 20 is provided, described Semiconductor substrate 20 surfaces have grid structure 21, the silicon nitride layer 23 on described Semiconductor substrate 20 and grid structure 21 surface formation silicon oxide layers 22 and silicon oxide layer 22 surfaces.
Please refer to Fig. 5, adopt described in anisotropic dry etch process etching silicon oxide layer 22(as shown in Figure 4) and silicon nitride layer 23(is as shown in Figure 4), until expose Semiconductor substrate 20, form monox lateral wall 22a and silicon nitride side wall 23a.
Wherein, first adopt anisotropic dry etch process for the first time to remove silicon nitride layer 23, and described etching technics stop at silicon oxide layer 22 surfaces; Adopt again the silicon oxide layer 22 of anisotropic dry etch process removal semiconductor substrate surface for the second time, until expose Semiconductor substrate 20; At this, the stop-layer of described silicon oxide layer 22 during as etch silicon nitride layer 23; And in the technique of silicon nitride layer described in etching 23, described silicon oxide layer 22 is injury-free for the protection of described Semiconductor substrate 20 surfaces; Owing to making the protection of described silicon oxide layer 22, the damage of the technique of having avoided etch silicon nitride layer 23 to Semiconductor substrate 20, thus the technique of etch silicon nitride layer 23 is more easily controlled, and described etching technics is easier to operation.
In said method, because the technique of etch silicon nitride layer 23 stops at silicon oxide layer 22 surfaces, therefore to take described silicon nitride side wall 23a and grid structure 21 be mask when follow-up, and after silicon oxide layer 22, formed monox lateral wall 22a is L-shaped described in etching; And, between described silicon nitride side wall 23a and Semiconductor substrate 20, there is one side of " L " conformal silicon oxide side wall 22a, region A as shown in Figure 5; Further, outside the monox lateral wall 22a between silicon nitride side wall 23a and Semiconductor substrate 20 is exposed to.
The present inventor studies discovery, in prior art, at following adopted etching technics, form opening 12(as shown in Figure 2) afterwards, need to carry out cleaning, to residue in Semiconductor substrate 10(as shown in Figure 2 in each etching process before removing) and the etch by-products of device surface, to guarantee to be formed at stressor layers 13(in opening 12 as shown in Figure 3) quality is good; And the cleaning fluid that described cleaning adopts includes hydrofluoric acid, be mainly used in removing silica accessory substance; Therefore in described cleaning process, between Semiconductor substrate 20 and silicon nitride side wall 23a, and be exposed to outer monox lateral wall 22a(as shown in Figure 5) can be removed by described hydrofluoric acid, thus between silicon nitride side wall 23a and Semiconductor substrate 20, form gap; And then, while causing follow-up formation stressor layers 13, can between described silicon nitride side wall 23a and Semiconductor substrate 20, fill the material of stressor layers 13, make formed transistor easily produce leakage current, cause unstable properties.
The present inventor after further research, after forming silicon oxide layer, the silicon oxide layer of removing semiconductor substrate surface, directly contacts the silicon nitride layer of follow-up formation, thereby makes the silicon nitride side wall of follow-up formation directly be formed at semiconductor substrate surface with semiconductor substrate surface; Therefore, can the cleaning process after follow-up formation opening in, avoided forming gap between silicon nitride side wall and Semiconductor substrate; Therefore, fluid-tight engagement between silicon nitride side wall and Semiconductor substrate; In the process of follow-up formation stressor layers, can between described silicon nitride side wall and Semiconductor substrate, not fill the material of described stressor layers, make formed transistorized stable performance, leakage current reduces.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.Fig. 6 to Figure 13 is the cross-sectional view of transistorized forming process described in embodiments of the invention, comprising:
Please refer to Fig. 6, Semiconductor substrate 200 is provided, described Semiconductor substrate 200 surfaces have grid structure 201.
Described Semiconductor substrate 200 is used to subsequent technique that workbench is provided, and the material of described Semiconductor substrate 200 is monocrystalline silicon, or described Semiconductor substrate 200 is silicon-on-insulator (SOI) structure; In the present embodiment, the indices of crystallographic plane on described Semiconductor substrate 200 surfaces are (100), the follow-up opening that can form " Σ " (Sigma, Sigma) shape in described Semiconductor substrate.
Described grid structure 201 comprises: the gate dielectric layer 210 on Semiconductor substrate 200 surfaces, be positioned at the gate electrode layer 211 on described gate dielectric layer 210 surfaces, and the mask layer 212 that is positioned at gate electrode layer 211 surfaces; The formation technique of described grid structure 201 is: on described Semiconductor substrate 200 surfaces, form gate dielectric membrane; On described gate dielectric membrane surface, form gate electrode film; At described gate electrode film surface, form mask layer 212, described mask layer 212 covers the correspondence position that need to form grid structure 201, and the material of described mask layer 212 is silicon nitride; The described mask layer 212 of take is mask, adopts gate electrode film and gate dielectric membrane described in anisotropic dry etch process etching, forms gate dielectric layer 210 and gate electrode layer 211.
Wherein, the material of described gate dielectric layer 210 is silica or high K dielectric material, and the material of described gate electrode layer 211 is polysilicon.
It should be noted that, when the material of described gate dielectric layer 210 is high K dielectric material, in the follow-up formation that completes stressor layers and form behind source region and drain region, describedly take the gate electrode layer 211 that polysilicon is material and need be removed, and form metal gate electrode in the position of described gate electrode layer 211; Gate dielectric layer 210 and the described metal gate electrode of described high K dielectric material form high K/ metal gate electrode (HKMG, High-KMetal Gate) transistor.
When formed transistor is high K/ metal gate electrode transistor, described grid structure 201 also comprises the protection side wall 213 that is positioned at described gate dielectric layer 210 and gate electrode layer 211 both sides; The material of described protection side wall 213 is silicon nitride, and because metal is very easily oxidized, therefore described protection side wall 213 covers the sidewall of the metal gate electrode of follow-up formation, avoids described metal gate electrode oxidized, has guaranteed formed transistorized performance.
In the present embodiment, the material of described gate dielectric layer 210 is high K dielectric material, and described grid structure 201 comprises the protection side wall 213 that is positioned at described gate dielectric layer 210 and gate electrode layer 211 both sides.
Please refer to Fig. 7, form the silicon oxide layer 202 that covers described grid structure 201 and Semiconductor substrate 200 surfaces.
The formation technique of described silicon oxide layer 202 is depositing operation, preferably chemical vapor deposition method; The thickness of described silicon oxide layer 202 is 10 dust-50 dusts; Described silicon oxide layer 202 is used to form monox lateral wall in subsequent technique, and described monox lateral wall is when follow-up removal the first silicon nitride side wall, injury-free for the protection of the sidewall of described grid structure 201, thereby has guaranteed that formed transistor performance is stable; The formation technique of described silicon oxide layer 202 is well known to those skilled in the art, and therefore not to repeat here.
Please refer to Fig. 8, adopt the silicon oxide layer 202(on the first anisotropic dry etch process removal Semiconductor substrate 200 surfaces as shown in Figure 7), form monox lateral wall 202a.
Described monox lateral wall 202a is for after follow-up formation stressor layers and source region and drain region, and while removing the first silicon nitride side wall, the sidewall surfaces of grill-protected electrode structure 201 is injury-free; And, because the silicon oxide layer 202 on described Semiconductor substrate 200 surfaces is removed, therefore follow-up formed the first silicon nitride side wall can directly be formed at Semiconductor substrate 200 surfaces, and fluid-tight engagement between described the first silicon nitride side wall and Semiconductor substrate 200, does not have gap; And then, follow-up, take described the first silicon nitride side wall when mask forms stressor layers, between described the first silicon nitride side wall and Semiconductor substrate 200, can not be packed into the material of stressor layers, avoid formed transistor to produce leakage current, make formed transistorized stable performance.
Adopt ion vertical bombarding semiconductor substrate 200 surfaces that described the first anisotropic dry etch process can make etching gas and the top of grid structure 201, to remove the silicon oxide layer 202 on Semiconductor substrate 200 and grid structure 201 surfaces; And, because the ion of etching gas is in the direction motion perpendicular to Semiconductor substrate 200, therefore the silicon oxide layer 202 that is positioned at grid structure 201 sidewall surfaces is parallel with the direction of motion of described gas ion, removal is difficult for being etched, can, when removing the silicon oxide layer 202 on Semiconductor substrate 200 surfaces, form the monox lateral wall 202a that is positioned at described grid structure 201 both sides.
Described the first anisotropic dry etch process comprises the first over etching after the first main etching and the first main etching; Described the first main etching and the first over etching are in the situation that accurately controlling etch period, can remove more accurately the silicon oxide layer 202 on Semiconductor substrate 200 surfaces, make described etching technics just stop at semiconductor substrate surface, and without additionally forming etching stop layer to control described the first anisotropic dry etch process; Wherein, the gas of described the first main etching technique comprises CHF3 and He, and the time is 5 seconds ~ 45 seconds.
Please refer to Fig. 9, after forming monox lateral wall 202a, form the silicon nitride layer 203 that covers described Semiconductor substrate 200, grid structure 201 and monox lateral wall 202a surface.
The formation technique of described silicon nitride layer 203 is depositing operation, preferably chemical vapor deposition method; The thickness of described silicon oxide layer 202 is 50 dust-300 dusts; The formation technique of described silicon nitride layer 203 is well known to those skilled in the art, and therefore not to repeat here.
Due in preorder technique, be positioned at the silicon oxide layer 202(on Semiconductor substrate 200 surfaces as shown in Figure 7) be removed, so described silicon nitride layer 203 is direct and Semiconductor substrate 200 Surface Contacts, thereby follow-up the first silicon nitride side wall being formed by described silicon nitride layer 203 is directly contacted with Semiconductor substrate 200, can avoid being packed into the material of follow-up formation stressor layers between described the first silicon nitride side wall and Semiconductor substrate 200; Therefore, can make formed transistorized stable performance, leakage current reduces.
Please refer to Figure 10, adopt the silicon nitride layer 203(at the second anisotropic dry etch process removal Semiconductor substrate 200 surfaces and grid structure 201 tops as shown in Figure 8), form the first silicon nitride side wall 203a.
Described the first silicon nitride side wall 203a is for determining the position of the stressor layers of follow-up formation; When the stressor layers of follow-up formation, take described grid structure 201 and the first silicon nitride side wall 203a is mask, avoids the hypotelorism between formed stressor layers and produces short-channel effect.
Described the second anisotropic dry etch process, makes the ion of etching gas vertically to Semiconductor substrate 200 and grid structure 201 surface bombardments, removes the silicon nitride layer 203 at Semiconductor substrate 200 surfaces and grid structure 201 tops; Because the ion of etching gas is parallel with the direction of motion of described gas ion with the silicon nitride layer 203 of grid structure 201 sidewall surfaces, removal is difficult for being etched, therefore can, when removing the silicon nitride layer 203 on Semiconductor substrate 200 surfaces, form the first silicon nitride side wall 203a that is positioned at described grid structure 201 and monox lateral wall 202a both sides.
Because the surface of described Semiconductor substrate 200 directly contacts with silicon nitride layer 203, therefore the dry etching of described the second anisotropic need to pass through the accurate control to etch period, and the problem of overetch does not occur so that etching technics stops at semiconductor substrate surface; And described etch period is relevant with the thickness of silicon nitride layer 203, the thickness of described silicon nitride layer 203 is thicker, and etch period is more of a specified duration.
Described the second anisotropic dry etch process comprises the second over etching after the second main etching and the second main etching; Described the second main etching and the first over etching, in the situation that accurately controlling etch period, can be removed the silicon nitride layer 203 of semiconductor substrate surface more accurately, make described etching technics just stop at Semiconductor substrate 200 surfaces; Thereby, avoided forming silicon oxide layer 202 as etching stop layer between described silicon nitride layer 203 and Semiconductor substrate 200, formed transistorized leakage current is reduced, stable performance; The gas of described the second main etching technique comprises CF
4and O
2, the time is 10 ~ 45 seconds.
Please refer to Figure 11, after forming the first silicon nitride side wall 203a, take grid structure 201 and the first silicon nitride side wall 203a is mask, the interior formation opening 204 of Semiconductor substrate 200 in grid structure 201 both sides, the surface of the sidewall of described opening 204 and Semiconductor substrate 200 is " Σ " shape, and the sidewall of described opening 204 is to the interior extension of Semiconductor substrate 200.
The formation technique of described opening 204 is: take described grid structure 201, monox lateral wall 202a and the first silicon nitride side wall 203a is mask, adopts dry etch process at the interior formation sidewall of the described Semiconductor substrate 200 opening (not shown) surperficial vertical with Semiconductor substrate 200; After dry etching, opening described in wet etching, makes drift angle on described opening sidewalls to the interior extension of Semiconductor substrate 200 of grid structure 201 belows, forms opening 204 sidewalls of " Σ " shape.
Described dry etching is anisotropic dry etching, and etching gas comprises the mist of chlorine, hydrogen bromide or chlorine and hydrogen bromide; Described dry etch process parameter is: the flow of hydrogen bromide be 200 standard milliliters per minute ~ 800 standard milliliters are per minute, the flow of chlorine be 20 standard milliliters per minute ~ 100 standard milliliters are per minute, the flow of inert gas be 50 standard milliliters per minute ~ 1000 standard milliliters are per minute, the pressure of etching cavity is 2 millitorr ~ 200 millitorrs, and etch period is 15 seconds ~ 60 seconds.
Described wet etching is anisotropic wet etching, and described etching liquid comprises alkaline solution, and described alkaline solution is potassium hydroxide (KOH), NaOH (NaOH), lithium hydroxide (LiOH), lithium hydroxide ammoniacal liquor (NH
4oH) be one or more combinations in Tetramethylammonium hydroxide (TMAH).
Because the crystal face on described Semiconductor substrate 200 surfaces is (100), and described anisotropic wet etching is very fast perpendicular to Semiconductor substrate 200 surface and the etch rate that is parallel in the direction on Semiconductor substrate 200 surfaces, and etch rate when etching crystal face (111) is the slowest, thus the sidewall of described opening 204 is " Σ " shape; After the interior formation stressor layers of described opening 204, between adjacent stressor layers, distance is less when follow-up, and described stressor layers 210 applies with the stress of channel region larger.
It should be noted that, after forming the opening 204 of " Σ " shape sidewall, need to clean described opening, Semiconductor substrate 200 surfaces and device surface, to remove each the residual etch by-products of etching technics in preorder technique; In the cleaning fluid of described cleaning, contain hydrofluoric acid, for removing the silica of etch by-products; Because described the first silicon nitride side wall 203a is formed at Semiconductor substrate 200 surfaces, directly contact with described Semiconductor substrate 200, therefore between described the first silicon nitride side wall 203a and semiconductor layer 200, and described hydrofluoric acid only can be removed silica, therefore described hydrofluoric acid can not cause producing gap between the first silicon nitride side wall 203a and semiconductor layer 200; When follow-up formation stressor layers, between described the first silicon nitride side wall 203a and semiconductor layer 200, can not be packed into the material of described stressor layers, thereby make formed transistorized stable performance.
Please refer to Figure 12, adopt selective epitaxial depositing operation at described opening 204(as shown in figure 10) in formation stressor layers 205.
The material of described stressor layers 205 is SiGe or carborundum; When formed transistor is PMOS pipe, the material of described stressor layers 205 is SiGe; When formed transistor is NMOS pipe, the material of described stressor layers 205 is carborundum; Owing to thering is lattice mismatch between described stressor layers 205 and Semiconductor substrate 200, can provide stress to formed transistorized channel region, to improve the mobility of charge carrier.
The temperature of described selective epitaxial depositing operation is 500 degrees Celsius-800 degrees Celsius, and air pressure is 1 holder-100 holder, and reacting gas comprises silicon source gas (SiH
4or SiH
2cl
2) and germanium source gas (GeH
4) or carbon-source gas (CH
4, CH
3cl or CH
2cl
2), the flow of described silicon source gas, germanium source gas or carbon-source gas be 1 standard milliliter per minute ~ 1000 standard milliliters are per minute; The gas of described selective epitaxial depositing operation also comprises HCl and H
2, the flow of described HCl be 1 standard milliliter per minute ~ 1000 standard milliliters are per minute, H
2flow be 0.1 standard Liter Per Minute ~ 50 standard Liter Per Minute.
In one embodiment, in described stressor layers 205, there is doping ion, to reduce the diffusion of charge carrier, avoid producing building electric power; The ion adulterating is doped in described stressor layers 205 with Implantation or in-situ doped technique; The ion adulterating in SiGe comprises boron ion or indium ion, and the ion adulterating in carborundum is arsenic ion or phosphonium ion.
Please refer to Figure 13, after forming stressor layers 205, on Semiconductor substrate 200 surfaces of described grid structure 201 and monox lateral wall 202a both sides, form the second silicon nitride side wall 206; Take described the second silicon nitride side wall 206 and grid structure 201 is mask, and counter stress layer 205 carries out Implantation, forms source region and drain region.
In the present embodiment, before forming the second silicon nitride side wall 206, remove the first silicon nitride side wall 203a(as shown in figure 12); Owing to forming in the process of stressor layers 205, described the first silicon nitride side wall 203a is as mask, in order to determine the position of stressor layers 205; And, forming opening 204(as shown in figure 11) after, described the first silicon nitride side wall 203a is thinned, and therefore need to remove described the first silicon nitride side wall 203a, and form accurate in size the second silicon nitride side wall 206; Described the second silicon nitride side wall 206 is in order to determine the position in source region and drain region, and makes formed transistorized dimensional standard, stable performance.
The technique of described the first silicon nitride side wall 203a of described removal is dry etching or wet etching; The technique of described formation the second silicon nitride side wall 206 is identical with the technique that forms the first silicon nitride side wall 203a, and therefore not to repeat here.
In another embodiment, after forming stressor layers 205, on Semiconductor substrate 200 surfaces of described grid structure 201 and monox lateral wall 202a both sides, form the second silicon nitride side wall 206, and without removing described the first silicon nitride side wall 203a; Described in this in, simplified processing step, save time and cost.
The formation technique in described source region and drain region is ion implantation technology, described Implantation is usingd grid structure 201, silicon oxide layer side wall 202a and the second silicon nitride side wall 206 as mask, because the dimensional standard of described the second silicon nitride side wall 206 is accurate, the position in formed source region and drain region is standard more; When the material of described stressor layers 205 is SiGe, the ion injecting is p-type ion; When the material of described stressor layers 205 is carborundum, the ion injecting is N-shaped ion.
It should be noted that, because the material of the gate dielectric layer 210 of the present embodiment is high K dielectric material, after forming stressor layers 205, removes described mask layer 212 and gate electrode layer 211, and form metal gate electrode in the position of described gate electrode layer 211; Described gate dielectric layer 210, metal gate electrode, silicon oxide layer side wall 202a, the second silicon nitride side wall 206, stressor layers 205 and source region and drain region form high K/ metal gate electrode transistor.
In the present embodiment, after forming silicon oxide layer 202, remove the silicon oxide layer 202 on Semiconductor substrate 200 surfaces, to form monox lateral wall 202a, make formed the first silicon nitride side wall 203a directly with Semiconductor substrate 200 Surface Contacts, so fluid-tight engagement between described the first silicon nitride side wall 203a and Semiconductor substrate 200; After the cleaning through after forming opening 204, between described the first silicon nitride side wall 203a and Semiconductor substrate 200, can not produce gap, avoided the material of stressor layers 205 to enter described gap and make transistorized unstable properties; Formed transistor drain current reduces, functional.
In sum, at grid structure and semiconductor substrate surface, form after silicon oxide layer, remove the silicon oxide layer of semiconductor substrate surface, the silicon nitride layer of follow-up formation is directly contacted with Semiconductor substrate, avoided making to there is silicon oxide layer between formed the first silicon nitride side wall and Semiconductor substrate; And then, in the forming process of stressor layers, avoided being removed because cleaning makes the silicon oxide layer between the first silicon nitride side wall and Semiconductor substrate, and produced gap; Because formed the first silicon nitride side wall directly contacts with Semiconductor substrate, therefore when forming stressor layers, the material of stressor layers can not enter between the first silicon nitride side wall and Semiconductor substrate, has avoided the generation of leakage current, makes formed transistorized stable performance.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement to make possible change and modification to technical solution of the present invention; therefore; every content that does not depart from technical solution of the present invention; any simple modification, equivalent variations and the modification above embodiment done according to technical spirit of the present invention, all belong to the protection range of technical solution of the present invention.
Claims (17)
1. a transistorized formation method, is characterized in that, comprising:
Semiconductor substrate is provided, and described semiconductor substrate surface has grid structure;
Form the silicon oxide layer that covers described grid structure and semiconductor substrate surface;
Remove the silicon oxide layer of semiconductor substrate surface;
After removing the silicon oxide layer of semiconductor substrate surface, form the silicon nitride layer that covers described Semiconductor substrate, grid structure and silicon oxide layer surface;
Remove the silicon nitride layer at semiconductor substrate surface and grid structure top, form the first silicon nitride side wall;
After forming the first silicon nitride side wall, in the Semiconductor substrate of grid structure both sides, form stressor layers.
2. transistorized formation method as claimed in claim 1, it is characterized in that, the technique of the silicon oxide layer of described removal semiconductor substrate surface is the first anisotropic dry etch process, and the technique of the silicon nitride layer at described removal semiconductor substrate surface and grid structure top is the second anisotropic dry etch process.
3. transistorized formation method as claimed in claim 2, is characterized in that, described the first anisotropic dry etch process comprises the first over etching after the first main etching and the first main etching; Described the second anisotropic dry etch process comprises the second over etching after the second main etching and the second main etching.
4. transistorized formation method as claimed in claim 3, is characterized in that, the gas of described the first main etching technique comprises CHF
3and He, the time is 5 seconds ~ 45 seconds.
5. transistorized formation method as claimed in claim 3, is characterized in that, the gas of described the second main etching technique comprises CF
4and O
2, the time is 10 seconds ~ 45 seconds.
6. transistorized formation method as claimed in claim 1, is characterized in that, the thickness of described silicon oxide layer is 10 dust-15 dusts, and the thickness of described silicon nitride layer is 50 dust-300 dusts.
7. transistorized formation method as claimed in claim 1, is characterized in that, the material of described stressor layers is SiGe or carborundum.
8. transistorized formation method as claimed in claim 1, is characterized in that, sidewall and the semiconductor substrate surface of described stressor layers is " Σ " type.
9. transistorized formation method as claimed in claim 8, it is characterized in that, the formation technique of described stressor layers is: take grid structure and the first silicon nitride side wall is mask, adopt the dry etch process of anisotropic to form opening in the Semiconductor substrate of grid structure both sides, the sidewall of described opening is vertical with semiconductor substrate surface; Adopt opening described in anisotropic wet-etching technology etching, the sidewall of described opening is extended in Semiconductor substrate, make the sidewall of described opening and the surface of Semiconductor substrate be " Σ " shape; After described anisotropic dry etching, adopt selective epitaxial depositing operation to form stressor layers in described opening.
10. transistorized formation method as claimed in claim 9, it is characterized in that, also comprise: after the wet-etching technology of described anisotropic, Semiconductor substrate, grid structure and the first silicon nitride side wall surface are cleaned, the cleaning fluid of described cleaning includes hydrofluoric acid.
11. transistorized formation methods as claimed in claim 1, is characterized in that, described grid structure comprises: the gate dielectric layer of semiconductor substrate surface, be positioned at the gate electrode layer on described gate dielectric layer surface, and the mask layer that is positioned at gate electrode layer surface.
12. transistorized formation methods as claimed in claim 11, is characterized in that, the material of described gate dielectric layer is high K dielectric material or silica, and the material of described gate electrode layer is polysilicon.
13. transistorized formation methods as claimed in claim 12; it is characterized in that; when the material of described gate dielectric layer is high K dielectric material, described grid structure also comprises: be positioned at the protection side wall of described gate dielectric layer and gate electrode layer both sides, the material of described protection side wall is silicon nitride.
14. transistorized formation methods as claimed in claim 12, is characterized in that, when the material of described gate dielectric layer is high K dielectric material, after forming stressor layers, remove described gate electrode layer, and form metal gate electrode in the position of described gate electrode layer.
15. transistorized formation methods as claimed in claim 1, is characterized in that, after forming stressor layers, in described Semiconductor substrate and grid structure both sides, form the second silicon nitride side wall.
16. transistorized formation methods as claimed in claim 15, is characterized in that, after forming stressor layers, before forming the second silicon nitride side wall, remove the first silicon nitride side wall.
17. transistorized formation methods as claimed in claim 15, is characterized in that, take described the second silicon nitride side wall and grid structure is mask, and counter stress layer carries out Implantation, forms source region and drain region.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110544620A (en) * | 2019-09-06 | 2019-12-06 | 上海华力微电子有限公司 | Silicon epitaxial growth method and semiconductor structure |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090246922A1 (en) * | 2008-03-27 | 2009-10-01 | Meng-Yi Wu | Method of forming cmos transistor |
| US20110049567A1 (en) * | 2009-08-27 | 2011-03-03 | Taiwan Semiconductor Manufacturing Company, Ltd | Bottle-neck recess in a semiconductor device |
| CN102299156A (en) * | 2010-06-28 | 2011-12-28 | 中国科学院微电子研究所 | Semiconductor device and manufacturing method thereof |
-
2012
- 2012-09-26 CN CN201210364951.8A patent/CN103681344A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090246922A1 (en) * | 2008-03-27 | 2009-10-01 | Meng-Yi Wu | Method of forming cmos transistor |
| US20110049567A1 (en) * | 2009-08-27 | 2011-03-03 | Taiwan Semiconductor Manufacturing Company, Ltd | Bottle-neck recess in a semiconductor device |
| CN102299156A (en) * | 2010-06-28 | 2011-12-28 | 中国科学院微电子研究所 | Semiconductor device and manufacturing method thereof |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110544620A (en) * | 2019-09-06 | 2019-12-06 | 上海华力微电子有限公司 | Silicon epitaxial growth method and semiconductor structure |
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