CN103632969A - Method of forming a transistor - Google Patents
Method of forming a transistor Download PDFInfo
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- CN103632969A CN103632969A CN201210299790.9A CN201210299790A CN103632969A CN 103632969 A CN103632969 A CN 103632969A CN 201210299790 A CN201210299790 A CN 201210299790A CN 103632969 A CN103632969 A CN 103632969A
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- semiconductor substrate
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- transistorized formation
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- 238000000034 method Methods 0.000 title claims abstract description 67
- 239000004065 semiconductor Substances 0.000 claims abstract description 69
- 239000000758 substrate Substances 0.000 claims abstract description 66
- 239000000463 material Substances 0.000 claims abstract description 42
- 229910052732 germanium Inorganic materials 0.000 claims abstract description 26
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims abstract description 26
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims abstract description 19
- 229910052799 carbon Inorganic materials 0.000 claims abstract description 19
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims abstract description 15
- 229910010271 silicon carbide Inorganic materials 0.000 claims abstract description 15
- 230000015572 biosynthetic process Effects 0.000 claims description 52
- 238000000151 deposition Methods 0.000 claims description 19
- 229910052710 silicon Inorganic materials 0.000 claims description 14
- 239000010703 silicon Substances 0.000 claims description 14
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- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 13
- 229910052785 arsenic Inorganic materials 0.000 claims description 13
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 13
- 229910052796 boron Inorganic materials 0.000 claims description 13
- 229910052738 indium Inorganic materials 0.000 claims description 13
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- 238000005468 ion implantation Methods 0.000 claims description 3
- 150000002500 ions Chemical class 0.000 abstract description 65
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- ILCYGSITMBHYNK-UHFFFAOYSA-N [Si]=O.[Hf] Chemical compound [Si]=O.[Hf] ILCYGSITMBHYNK-UHFFFAOYSA-N 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
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- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
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- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
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- CZXRMHUWVGPWRM-UHFFFAOYSA-N strontium;barium(2+);oxygen(2-);titanium(4+) Chemical compound [O-2].[O-2].[O-2].[O-2].[Ti+4].[Sr+2].[Ba+2] CZXRMHUWVGPWRM-UHFFFAOYSA-N 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
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- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
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- -1 tungsten nitride Chemical class 0.000 description 1
- GFQYVLUOOAAOGM-UHFFFAOYSA-N zirconium(iv) silicate Chemical compound [Zr+4].[O-][Si]([O-])([O-])[O-] GFQYVLUOOAAOGM-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0856—Source regions
- H01L29/086—Impurity concentration or distribution
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
- H01L29/0878—Impurity concentration or distribution
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
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- Crystallography & Structural Chemistry (AREA)
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- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Disclosed is a method of forming a transistor, the method comprising: providing a semiconductor substrate, the surface of which is provided with a gate structure; forming an opening in the semiconductor substrate on both sides of the gate structure; forming a first liner layer made of silicon germanium or silicon carbide on a side wall and a bottom surface of the opening, a P-type doping ion or an N-type doping ion being disposed in the first liner layer; and filling the surface of the first liner layer with a second liner layer of the opening. The second liner layer is made of the same material as that of the first liner layer, and the atomic percent concentration of germanium or carbon in the second liner layer is greater than that in the first liner layer. The doping ion in the second liner layer is the same as that in the first liner layer, and the concentration of the doping ion in the second liner layer is greater than that in the first liner layer. The formed transistor is lower in threshold voltage and stable in performance.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, relate in particular to a kind of transistorized formation method.
Background technology
Transistor is just being widely used at present as the most basic semiconductor device, and along with the raising of component density and the integrated level of semiconductor device, transistorized grid size becomes than in the past shorter; Yet transistorized grid size shortens and can make transistor produce short-channel effect, and then produces leakage current, finally affects the electric property of semiconductor device.At present, prior art mainly, by improving the stress of transistor channel region, to improve carrier mobility, and then improves transistorized drive current, reduces the leakage current in transistor.
The method that prior art improves the stress of transistor channel region is, in transistorized source/drain region formation stress liner layer, wherein, the material of the transistorized stress liner layer of PMOS is SiGe (SiGe), the compression forming because of lattice mismatch between silicon and SiGe, thus the transistorized performance of PMOS improved; The material of the stress liner layer of nmos pass transistor is carborundum (SiC), the tension stress forming because of lattice mismatch between silicon and carborundum, thereby the performance of raising nmos pass transistor.
Prior art has the cross-sectional view of the transistor forming process of stress liner layer, as shown in Figure 1 to Figure 3, comprising:
Please refer to Fig. 1, Semiconductor substrate 10 is provided, on described Semiconductor substrate 10 surfaces, form grid structure 11.Described grid structure 11 comprises: the gate dielectric layer 14 on described Semiconductor substrate 10 surfaces, the gate electrode layer 15 on described gate dielectric layer 14 surfaces, and the side wall 16 on Semiconductor substrate 10 surfaces of described gate electrode layer 15 both sides.
Please refer to Fig. 2, the interior formation opening 12 of Semiconductor substrate 10 in described grid structure 11 both sides.Described opening 12Wei Sigma (Σ, sigma) shape, the surface of the sidewall of described opening 12 and Semiconductor substrate 10 forms Sigma's shape, and the drift angle on described opening 12 sidewalls is to the interior extension of Semiconductor substrate 10 of described grid structure 11 belows.
Please refer to Fig. 3, at the interior formation stress liner of described opening 12 layer 13, the material of described stress liner layer 13 is SiGe or carborundum.
It should be noted that, for stress liner layer 13 is more mated with the lattice between Semiconductor substrate 10, prior art forms transition zone 14 between stress liner layer 13 and Semiconductor substrate 10, the material of described excessive layer 14 is identical with the material of described stress liner layer 13, and the atom percentage concentration of the carbon in described transition zone 14 or germanium is less than described stress liner layer 13.
Yet the transistorized threshold voltage with stress liner layer forming with prior art is too high, performance is bad.
The transistors with stress liner layer please refer to the U.S. patent documents that publication number is US 2011256681A1 more.
Summary of the invention
The problem that the present invention solves is to provide a kind of transistorized formation method, and formed transistorized threshold voltage is reduced, and improves performance.
For addressing the above problem, the invention provides a kind of transistorized formation method, comprising: Semiconductor substrate is provided, and described semiconductor substrate surface has grid structure; In the Semiconductor substrate of described grid structure both sides, form opening; Sidewall and lower surface at described opening form the first laying, and the material of described the first laying is SiGe or carborundum, tool doping ion in described the first laying, and described doping ion is P type ion or N-type ion; On described the first laying surface, form second laying of filling full described opening, the material of described the second laying is consistent with the first laying, and the germanium in described the second laying or the atom percentage concentration of carbon are than the first liner floor height, in described the second laying, have and doping ion identical in the first laying, and the first liner floor height of the doping ion concentration in the second laying.
Alternatively, when the material of described the first laying and the second laying is SiGe, described doping ion is boron or indium.
Alternatively, the boron in described the first laying or the doping content of indium are 1E17 atom/cubic centimetre-1E19 atom/cubic centimetre, and the boron in described the second laying or the doping content of indium are 1E19 atom/cubic centimetre-1E21 atom/cubic centimetre.
Alternatively, in described the first laying, the atom percentage concentration of germanium is 1%-25%, and in described the second laying, the atom percentage concentration of germanium is 25%-45%.
Alternatively, when the material of described the first laying and the second laying is carborundum, described doping ion is phosphorus or arsenic.
Alternatively, the phosphorus in described the first laying or the doping content of arsenic are 1E17 atom/cubic centimetre-1E19 atom/cubic centimetre, and the phosphorus in described the second laying or the doping content of arsenic are 1E19 atom/cubic centimetre-1E21 atom/cubic centimetre.
Alternatively, in described the first laying, the atom percentage concentration of carbon is 0.05%-1%, and in described the second laying, the atom percentage concentration of germanium is 1%-10%.
Alternatively, the formation technique of described the first laying and the second laying is selective epitaxial depositing operation.
Alternatively, the temperature of selective epitaxial depositing operation is 500 degrees Celsius-800 degrees Celsius, and air pressure is 1 holder-100 holder.
Alternatively, the gas of described selective epitaxial depositing operation comprises SiH
4or SiH
2cl
2, described SiH
4or SiH
2cl
2flow be 1sccm-1000sccm.
Alternatively, the gas of described selective epitaxial depositing operation also comprises: HCl and H
2, the flow of described HCl is 1sccm-1000sccm, H
2flow be 0.1slm-50slm.
Alternatively, in described the first laying and the second laying, the technique of doping ion is in-situ doped technique.
Alternatively, the gas of described in-situ doped technique is B
2h
6, InCl
3, PH
3or AsH
3, described B
2h
6, InCl
3, PH
3or AsH
3flow be 1sccm-1000sccm.
Alternatively, in described the second laying, the technique of doping ion is ion implantation technology.
Alternatively, the thickness of described the first laying is 1 dust ~ 200 nanometer, and the bottom of described the second laying is 1 dust ~ 200 nanometer to the thickness of semiconductor substrate surface.
Alternatively, the sidewall of described opening and the surface of Semiconductor substrate form Sigma's shape, and the drift angle on described opening sidewalls extends in the Semiconductor substrate of described grid structure below.
Alternatively, at described the first laying and the second laying surface, form cover layer.
Alternatively, described tectal material is titanium silicon, nisiloy or cobalt silicon.
Alternatively, the material of described Semiconductor substrate is silicon or silicon-on-insulator.
Alternatively, described grid structure comprises: the gate dielectric layer of described semiconductor substrate surface, the gate electrode layer on described gate dielectric layer surface, and the side wall of the semiconductor substrate surface of described gate electrode layer both sides.
Compared with prior art, technical scheme of the present invention has the following advantages:
At opening sidewalls and bottom, form the first laying, and second substrate layer of filling full described opening, the material of described the second laying is consistent with the first laying, and the atom percentage concentration of the germanium in described the second laying or carbon is than the first liner floor height; Make to have and doping ion identical in the first laying in the second laying, when formed transistor work, in the first laying, the ion of doping can enter channel region, and the migration of doping ion in described the first laying, can make the doping ion in the second laying be easier to through described the first laying, and enter channel region, thus formed transistorized threshold voltage is reduced, performance improvement; In addition, doping ion concentration the second laying in the first laying is low, has guaranteed under non operating state, and the doping ion in the first laying diffusion can not occur and forms leakage current, makes transistorized stable performance.
Accompanying drawing explanation
Fig. 1 to Fig. 3 is the cross-sectional view that prior art has the transistor forming process of stress liner layer;
Fig. 4 to Fig. 8 is the cross-sectional view of transistorized forming process described in the present embodiment.
Embodiment
As stated in the Background Art, the transistorized threshold voltage with stress liner layer that prior art forms is too high, and performance is bad.
Please continue to refer to Fig. 3, have in the transistor of stress liner layer, in order to improve stress liner layer 13, put on the stress of channel region, need to improve the atom percentage concentration of carbon in stress liner layer 13 or germanium; Yet the atom percentage concentration of carbon or germanium is higher in stress liner layer 13, the crystal lattice difference between described stress liner layer 13 and Semiconductor substrate 10 is more serious, easily in the interface of described stress liner layer 13 and Semiconductor substrate 10, causes defect.Therefore, prior art is in order to alleviate the crystal lattice difference between described stress liner layer 13 and Semiconductor substrate 10, can between described stress liner layer 13 and Semiconductor substrate 10, form again one deck transition zone 14, carbon in described transition zone 14 or the atom percentage concentration of germanium are interior low compared with stress liner layer 13, thereby play transitional function; And the atom percentage concentration of the carbon in described transition zone 14 or germanium is while being 20%-25%, transition effect is better.
The present inventor finds through research, at the interior doping ion of described stress liner layer 13, form behind source/drain region, when described transistor work, the ion adulterating is difficult to cross described transition zone 14 and enters channel region, cause described transistorized threshold voltage to be elevated, improved the power consumption of semiconductor device; And the atom percentage concentration of the interior carbon of described transition zone 14 or germanium is higher, the ion adulterating is larger through the difficulty of described transition zone 14, makes threshold voltage higher; Yet, if while reducing the atom percentage concentration of the interior carbon of described transition zone 14 or germanium, described transition zone 14 cannot counter stress laying 13 and Semiconductor substrate 10 between crystal lattice difference play transitional function, can correspondingly reduce the stress that stress liner layer 13 puts on channel region simultaneously, be unfavorable for transistorized performance improvement.
The present inventor after further research, at grid structure both-side opening sidewall and bottom, form the first laying, on described the first laying surface, form second laying of filling full described opening, and the material of described the first laying is identical with the second laying, and the atom percentage concentration of germanium in the second laying or carbon is than the first liner floor height; Make to have and doping ion identical in the first laying in described the second laying, when transistor is worked, doping ion in the first laying can move to channel region, thereby drive the doping ion in the second laying to move in channel region, make the doping ion in the second laying be easier to enter channel region, thereby reduced transistorized threshold voltage; On the other hand, doping ion concentration the second laying in the first laying is low, can when transistor disconnects, avoid the doping ion in the first laying diffusion to occur and produce leakage current, makes transistorized performance more stable.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.Fig. 4 to Fig. 8 is the cross-sectional view of transistorized forming process described in the present embodiment.
Please refer to Fig. 4, Semiconductor substrate 100 is provided, described Semiconductor substrate 100 surfaces have grid structure 101.
Described Semiconductor substrate 100 is used to subsequent technique that workbench is provided, the material of described Semiconductor substrate 100 is monocrystalline silicon or silicon-on-insulator, thereby between the first laying of follow-up formation and the second laying and described Semiconductor substrate 100, there is lattice mismatch, can provide stress to channel region and improve the mobility of charge carrier; The crystal face on described Semiconductor substrate 100 surfaces is (100), makes the sidewall of the opening that forms after follow-up anisotropic wet etching and Semiconductor substrate 100 surfaces form Sigma's shapes, further improves stress.
Described grid structure 101 comprises: is positioned at the gate dielectric layer 110 on described Semiconductor substrate 100 surfaces, is positioned at the gate electrode layer 111 on described gate dielectric layer 110 surfaces, and the side wall 112 that is positioned at Semiconductor substrate 100 surfaces of described gate electrode layer 111 both sides.
The material of described gate electrode layer 111 is polysilicon or metal; When the material of described gate electrode layer 111 is polysilicon, described gate dielectric layer 110 is silica, silicon nitride, silicon oxynitride; When the material of described gate electrode layer 111 is metal, described gate dielectric layer 110 is high K dielectric material, described high K dielectric material comprises: hafnium oxide, zirconia, hafnium silicon oxide, lanthana, zirconium silicon oxide, titanium oxide, tantalum oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia titanium or aluminium oxide, and described metal comprises: aluminium, copper, silver, gold, platinum, nickel, titanium, cobalt, thallium, tantalum or tungsten; The material of described side wall 112 is one or more combinations in silica, silicon nitride, silicon oxynitride.
When the material of described gate electrode layer 111 is polysilicon, when described gate dielectric layer 110 is silica, silicon nitride, silicon oxynitride, the formation technique of described grid structure 101 is: at described Semiconductor substrate 100 surface depositions, form gate dielectric membranes; On described gate dielectric membrane surface, form gate electrode film; Gate dielectric membrane and gate electrode film described in etching, form gate dielectric layer 110 and gate electrode layer 111; On described Semiconductor substrate 100, gate dielectric layer 110 and gate electrode layer 111 surfaces, form side wall layer; Return side wall layer described in etching, on Semiconductor substrate 100 surfaces of described gate electrode layer 111 both sides, form side walls 112.
When the material of described gate electrode layer 111 is metal, when described gate dielectric layer 110 is high K dielectric material, the formation technique of described grid structure 101 is: at described Semiconductor substrate 100 surface depositions, form gate dielectric membranes; On described gate dielectric membrane surface, form dummy grid film, the material of described dummy grid film is polysilicon; Gate dielectric membrane and be grid film described in etching, forms gate dielectric layer 110 and dummy grid; On described Semiconductor substrate 100, gate dielectric layer 110 and dummy grid surface, form side wall layer; Return side wall layer described in etching, on Semiconductor substrate 100 surfaces of described dummy grid both sides, form side walls 112; Semiconductor substrate surface in described side wall 112 and dummy grid both sides forms insulating barrier; Form after insulating barrier, remove described dummy grid, form opening; In described opening, fill metal, form gate electrode layer 111.
It should be noted that also have mask layer (not shown) on described gate electrode layer 111 surfaces, the material of described mask layer is one or more combinations in silicon nitride, titanium nitride, nitrogenize thallium, tungsten nitride, aluminium oxide; Described mask layer, in follow-up dry etching and the wet etching process that forms Sigma's shape opening, is avoided described gate electrode layer 211 surfaces to cause damage; Described mask layer is removed after subsequent technique forms the first laying and the second laying.
Please refer to Fig. 5, the interior formation opening 102 of Semiconductor substrate 100 in described grid structure 101 both sides.
Described opening 102 is for forming the first laying and the second laying at subsequent technique; In the present embodiment, the surface of the sidewall of described opening 102 and Semiconductor substrate 100 forms the (Σ of Sigma, sigma) shape, drift angle on described opening 102 sidewalls is to the interior extension of Semiconductor substrate 100 of described grid structure 101 belows, make the close together between the first laying of the follow-up opening 102 interior formation in grid structure 101 both sides, to put on the stress of channel region of grid structure 101 belows larger for the first laying of follow-up formation and the second laying, and formed transistorized performance improves.
In the present embodiment, the formation technique of described opening 102 is: the described grid structure 101 of take is mask, adopts and is dry-etched in the opening (not shown) that the interior formation sidewall of described Semiconductor substrate 100 is vertical with Semiconductor substrate 100 surfaces; After dry etching, adopt opening described in wet etching, make drift angle on described opening sidewalls to the interior extension of Semiconductor substrate 100 of grid structure 101 belows, form the opening 102 of Sigma's shape.
Described dry etching is anisotropic dry etching, and etching gas is the mist of chlorine, hydrogen bromide or chlorine and hydrogen bromide; Described dry etch process parameter is: the flow of hydrogen bromide is 200 ~ 800sccm, and the flow of chlorine is 20 ~ 100sccm, and the flow of inert gas is 50 ~ 1000sccm, and the pressure of etching cavity is 2 ~ 200mTorr, and etch period is 15 ~ 60 seconds.
Described wet etching is anisotropic wet etching, and described etching liquid is alkaline solution, and described alkaline solution is potassium hydroxide (KOH), NaOH (NaOH), lithium hydroxide (LiOH), lithium hydroxide ammoniacal liquor (NH
4oH) be one or more combinations in Tetramethylammonium hydroxide (TMAH).
Because the crystal face on described Semiconductor substrate 100 surfaces is (100), and described anisotropic wet etching is very fast perpendicular to Semiconductor substrate 100 surface and the etch rate that is parallel in the direction on Semiconductor substrate 100 surfaces, and etch rate when etching crystal face (111) is the slowest, thereby make the shape of described opening 102 become Sigma's shape; After interior formation the first laying of described opening 102, between adjacent the first laying, distance is less when follow-up, and described the first laying applies with the stress of channel region larger.
In another embodiment, the formation technique of described opening 102 is anisotropic dry etching, and the sidewall of described opening 102 is vertical with semiconductor substrate surface, makes work simplification, cost-saving.
Please refer to Fig. 6, in sidewall and the lower surface of described opening 102, form the first laying 103, the material of described the first laying 103 is SiGe or carborundum, the interior tool doping of described the first laying 103 ion, and described doping ion is P type ion or N-type ion.
The thickness of described the first laying 103 is 1 dust ~ 200 nanometer, and the formation technique of described the first laying 103 is selective epitaxial depositing operation; When formed transistor is PMOS transistor, the material of described the first laying 103 is SiGe, wherein the atom percentage concentration of germanium is 1% ~ 25%, preferably, the atom percentage concentration of germanium is 20%-25%, make the first laying 103 can be as the second laying of follow-up formation and the transition between Semiconductor substrate 100 time, to formed transistor channel region, provide enough stress, to improve carrier mobility; When formed transistor is nmos pass transistor, the material of described the first laying 103 is carborundum, and wherein the atom percentage concentration of carbon is 0.05% ~ 1%.
When formed transistor is PMOS transistor, when the material of described the first laying 103 is SiGe, the interior dopant of described the first laying 103 is P type ion, comprises boron or indium; Described boron or the indium doping content in the first laying 103 is 1E17 atom/cubic centimetre-1E19 atom/cubic centimetre; When formed transistor is nmos pass transistor, when the material of described the first laying 103 is carborundum, the interior dopant of described the first laying 103 is N-type ion, comprises phosphorus or arsenic; Described phosphorus or the arsenic doping content in the first laying 103 is 1E17 atom/cubic centimetre-1E19 atom/cubic centimetre.
The ion adulterating in described the first laying 103, when formed transistor work, can move to channel region; And the migration of the ion that adulterates in the first laying 103 can drive doping ion in the second laying of follow-up formation through described the first laying, and enter in channel region, thereby formed transistorized threshold voltage is reduced; In addition, the second laying of the follow-up formation of concentration of the doping ion of described the first laying 103 is low, therefore when formed transistor turn-offs, can there is not diffusion and form leakage current, formed transistorized stable performance in the ion in the first laying 103.
When formed transistor is PMOS transistor, the formation technique of described the first laying 103 is selective epitaxial depositing operation, and temperature is 500-800 degree Celsius, and air pressure is 1 holder-100 holder, and reacting gas comprises silicon source gas SiH
4or SiH
2cl
2, and germanium source gas GeH
4, the flow of described silicon source gas and germanium source gas is 1sccm-1000sccm; The gas of described selective epitaxial depositing operation also comprises HCl and H
2, the flow of described HCl is 1sccm-1000sccm, H
2flow be 0.1slm-50slm.
Technique at the interior doped with boron of described the first laying 103 or indium is in-situ doped technique,, when selective epitaxial deposits the first laying 103, adds boron source gas B in reacting gas again
2h
6, or indium source gas InCl
3, the flow of described boron source gas or indium source gas is 1sccm-1000sccm.
When formed transistor is nmos pass transistor, the formation technique of described the first laying 103 is selective epitaxial depositing operation, and temperature is 500 degrees Celsius-800 degrees Celsius, and air pressure is 1 holder-100 holder, and reacting gas comprises silicon source gas SiH
4or SiH
2cl
2, and carbon-source gas CH
4, CH
3cl or CH
2cl
2, the flow of described silicon source gas and carbon-source gas is 1sccm-1000sccm; The gas of described selective epitaxial depositing operation also comprises HCl and H
2, the flow of described HCl is 1sccm-1000sccm, H
2flow be 0.1slm-50slm.
Technique at the interior Doping Phosphorus of described the first laying 103 or arsenic is in-situ doped technique,, when selective epitaxial deposits the first laying 103, adds phosphorus source gas PH in reacting gas again
3, or arsenic source gas AsH
3, the flow of described phosphorus source gas or arsenic source gas is 1sccm-1000sccm.
Please refer to Fig. 7, the second laying 104 at the full described opening 102(of described the first laying 103 surface formation filling as shown in Figure 6), the material of described the second laying 104 is consistent with the first laying 103, and the germanium in described the second laying 104 or the atom percentage concentration of carbon are than the first laying 103 height, in described the second laying 104, have and the interior identical doping ion of the first laying 103, and the first laying 103 height of the doping ion concentration in the second laying 104.
The thickness of described the second laying 104 is 1 dust ~ 200 nanometer, and the formation technique of described the second laying 104 is selective epitaxial depositing operation; When formed transistor is PMOS transistor, the material of described the second laying 104 is SiGe, and wherein the atom percentage concentration of germanium is 25% ~ 45%; When formed transistor is nmos pass transistor, the material of described the second laying 104 is carborundum, and wherein the atom percentage concentration of carbon is 1% ~ 10%; The atom percentage concentration of the interior germanium of described the second laying 104 or carbon, compared with the first laying 103 height, can provide larger stress to channel region, carrier mobility is improved, transistorized functional.
When formed transistor is PMOS transistor, when the material of described the second laying 104 is SiGe, the interior dopant of described the second laying 104 is P type ion, comprises boron or indium; Described boron or the indium doping content in the first laying 103 is 1E19-1E21 atom/cubic centimetre; When formed transistor is nmos pass transistor, when the material of described the second laying 104 is carborundum, the interior dopant of described the first laying 103 is N-type ion, comprises phosphorus or arsenic; Described phosphorus or the arsenic doping content in the first laying 103 is 1E19 atom/cubic centimetre-1E21 atom/cubic centimetre; After the interior doping ion of described the second laying 104, formation source/drain region; When formed transistor work, the doping ion in described the second laying 104 is subject to the impact of operating voltage and moves to channel region.
Owing to being formed with the first laying 103 as transition between described the second laying 104 and Semiconductor substrate 100, make can in interface, not cause defect because of crystal lattice difference between the second laying 104 and Semiconductor substrate 100; Therefore,, when formed transistor work, the ion of the second laying 104 interior doping need to could arrive channel region through the first laying 103; In the present embodiment, in described the first laying 103, have and the interior identical doping ion of the second laying 104, when formed transistor work, doping ion in the first laying 103 can move to channel region, thereby drive the doping ion in described the second laying 104 to pass described the first laying 103, therefore the doping ion in the second laying 104 is easier to through the first laying 103, thereby has reduced formed transistorized threshold voltage, transistorized performance improvement.
The formation technique of described the second laying 104 is selective epitaxial depositing operation, and the technique of doping ion is in-situ doped technique, and the technique of the formation technique of described the second laying 104 and doping ion is identical with the first laying 103, and therefore not to repeat here.
It should be noted that, in other embodiments, interior the adulterated ion of described the second laying 104 can deposit after SiGe or carborundum at selective epitaxial, adopts ion implantation technology to adulterate.
Please refer to Fig. 8, at described the first laying 103 and the second laying 104 surfaces, form cover layer 105.
Described cover layer 105 is for the electrode as formed source transistor/drain region; The material of described cover layer 105 is metal silicide (salicide), comprises titanium silicon, nisiloy or cobalt silicon; The formation technique of described cover layer 105 is: Semiconductor substrate 100 surfaces in described grid structure 101 both sides form mask layer, and described mask layer exposes the first laying 103 and the second laying 104 surfaces; After forming mask layer, at described the first laying 103 and the second laying 104 surface selectivity epitaxial depositions, form silicon layer; In described silicon surface deposition, form metal level, the material of described metal level is titanium, nickel or cobalt; After forming metal level, carry out thermal annealing, make described metal level and silicon layer reaction, form cover layer 105; Remove the surperficial remaining metal level of cover layer 105 and mask layer.
Transistorized formation method described in the present embodiment forms the first laying 103 and is positioned at the first laying 103 surfaces and fills completely the second laying 104 of described opening in the opening of grid structure 101 both sides; In described the second laying 104, have and the interior identical doping ion of the first laying 103, when described transistor work, the ion of described the first laying 103 interior doping can move to channel region, thereby drives the ion of the second laying 104 interior doping pass described the first laying 103 and enter channel region; Formed transistorized threshold voltage reduces; Secondly, doping ion concentration the second laying 104 in the first laying 103 is interior low, and when described transistor turn-offs, the ion of described the first laying 103 interior doping can not spread, and has avoided generation leakage current, described transistorized stable performance.
In sum, at opening sidewalls and bottom, form the first laying, and second substrate layer of filling full described opening, the material of described the second laying is consistent with the first laying, and the atom percentage concentration of the germanium in described the second laying or carbon is than the first liner floor height; Make to have and doping ion identical in the first laying in the second laying, when formed transistor work, in the first laying, the ion of doping can enter channel region, and the migration of doping ion in described the first laying, can make the doping ion in the second laying be easier to through described the first laying, and enter channel region, thus formed transistorized threshold voltage is reduced, performance improvement; In addition, doping ion concentration the second laying in the first laying is low, has guaranteed under non operating state, and the doping ion in the first laying diffusion can not occur and forms leakage current, makes transistorized stable performance.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement to make possible change and modification to technical solution of the present invention; therefore; every content that does not depart from technical solution of the present invention; any simple modification, equivalent variations and the modification above embodiment done according to technical spirit of the present invention, all belong to the protection range of technical solution of the present invention.
Claims (20)
1. a transistorized formation method, is characterized in that, comprising:
Semiconductor substrate is provided, and described semiconductor substrate surface has grid structure;
In the Semiconductor substrate of described grid structure both sides, form opening;
Sidewall and lower surface at described opening form the first laying, and the material of described the first laying is SiGe or carborundum, tool doping ion in described the first laying, and described doping ion is P type ion or N-type ion;
On described the first laying surface, form second laying of filling full described opening, the material of described the second laying is consistent with the first laying, and the germanium in described the second laying or the atom percentage concentration of carbon are than the first liner floor height, in described the second laying, have and doping ion identical in the first laying, and the first liner floor height of the doping ion concentration in the second laying.
2. transistorized formation method as claimed in claim 1, is characterized in that, when the material of described the first laying and the second laying is SiGe, described doping ion is boron or indium.
3. transistorized formation method as claimed in claim 2, it is characterized in that, boron in described the first laying or the doping content of indium are 1E17 atom/cubic centimetre-1E19 atom/cubic centimetre, and the boron in described the second laying or the doping content of indium are 1E19 atom/cubic centimetre-1E21 atom/cubic centimetre.
4. transistorized formation method as claimed in claim 2, is characterized in that, in described the first laying, the atom percentage concentration of germanium is 1%-25%, and in described the second laying, the atom percentage concentration of germanium is 25%-45%.
5. transistorized formation method as claimed in claim 1, is characterized in that, when the material of described the first laying and the second laying is carborundum, described doping ion is phosphorus or arsenic.
6. transistorized formation method as claimed in claim 5, it is characterized in that, phosphorus in described the first laying or the doping content of arsenic are 1E17 atom/cubic centimetre-1E19 atom/cubic centimetre, and the phosphorus in described the second laying or the doping content of arsenic are 1E19 atom/cubic centimetre-1E21 atom/cubic centimetre.
7. transistorized formation method as claimed in claim 5, is characterized in that, in described the first laying, the atom percentage concentration of carbon is 0.05%-1%, and in described the second laying, the atom percentage concentration of germanium is 1%-10%.
8. transistorized formation method as claimed in claim 1, is characterized in that, the formation technique of described the first laying and the second laying is selective epitaxial depositing operation.
9. transistorized formation method as claimed in claim 8, is characterized in that, the temperature of selective epitaxial depositing operation is 500 degrees Celsius-800 degrees Celsius, and air pressure is 1 holder-100 holder.
10. transistorized formation method as claimed in claim 8, is characterized in that, the gas of described selective epitaxial depositing operation comprises SiH
4or SiH
2cl
2, described SiH
4or SiH
2cl
2flow be 1sccm-1000sccm.
11. transistorized formation methods as claimed in claim 10, is characterized in that, the gas of described selective epitaxial depositing operation also comprises: HCl and H
2, the flow of described HCl is 1sccm-1000sccm, H
2flow be 0.1slm-50slm.
12. transistorized formation methods as claimed in claim 1, is characterized in that, in described the first laying and the second laying, the technique of doping ion is in-situ doped technique.
13. transistorized formation methods as claimed in claim 12, is characterized in that, the gas of described in-situ doped technique is B
2h
6, InCl
3, PH
3or AsH
3, described B
2h
6, InCl
3, PH
3or AsH
3flow be 1sccm-1000sccm.
14. transistorized formation methods as claimed in claim 1, is characterized in that, in described the second laying, the technique of doping ion is ion implantation technology.
15. transistorized formation methods as claimed in claim 1, is characterized in that, the thickness of described the first laying is 1 dust ~ 200 nanometer, and the bottom of described the second laying is 1 dust ~ 200 nanometer to the thickness of semiconductor substrate surface.
16. transistorized formation methods as claimed in claim 1, is characterized in that, the sidewall of described opening and the surface of Semiconductor substrate form Sigma's shape, and the drift angle on described opening sidewalls extends in the Semiconductor substrate of described grid structure below.
17. transistorized formation methods as claimed in claim 1, is characterized in that, at described the first laying and the second laying surface, form cover layer.
18. transistorized formation methods as claimed in claim 17, is characterized in that, described tectal material is titanium silicon, nisiloy or cobalt silicon.
19. transistorized formation methods as claimed in claim 1, is characterized in that, the material of described Semiconductor substrate is silicon or silicon-on-insulator.
20. transistorized formation methods as claimed in claim 1, it is characterized in that, described grid structure comprises: the gate dielectric layer of described semiconductor substrate surface, the gate electrode layer on described gate dielectric layer surface, and the side wall of the semiconductor substrate surface of described gate electrode layer both sides.
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| US10361301B2 (en) | 2016-03-31 | 2019-07-23 | International Business Machines Corporation | Fabrication of vertical fin transistor with multiple threshold voltages |
| US10991823B2 (en) | 2016-03-31 | 2021-04-27 | International Business Machines Corporation | Fabrication of vertical fin transistor with multiple threshold voltages |
| US11018254B2 (en) | 2016-03-31 | 2021-05-25 | International Business Machines Corporation | Fabrication of vertical fin transistor with multiple threshold voltages |
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Application publication date: 20140312 |
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