CN104124144A - Manufacturing method of semiconductor device - Google Patents

Abstract

The invention provides a method for manufacturing a semiconductor device, comprising: providing a semiconductor substrate, sequentially forming a high-k dielectric layer, a cover layer, and a sacrificial gate electrode layer on the semiconductor substrate; forming a patterned first gate electrode layer on the sacrificial gate electrode layer A hard mask layer; using the patterned first hard mask layer as a mask, sequentially etch the sacrificial gate electrode layer, the cover layer and the high-k dielectric layer; remove the patterned first hard mask layer, and form a layer an inter-dielectric layer to cover the dummy gate structure formed by stacking the sacrificial gate electrode layer, the covering layer and the high-k dielectric layer; removing the sacrificial gate electrode layer in the dummy gate structure, leaving a gate trench; A sidewall material layer is formed on the sidewall of the gate trench; a metal gate structure is formed in the gate trench. According to the present invention, the width of the metal gate structure can be made smaller than the width of the covering layer and the high-k dielectric layer, further improving the performance of the finally formed semiconductor device.

Description

A method of manufacturing a semiconductor device

technical field

The invention relates to a semiconductor manufacturing process, in particular to a method for forming a metal gate structure.

Background technique

When the semiconductor process node reaches 28nm and below, replacing the traditional silicon oxynitride or silicon oxide dielectric layer/polysilicon gate structure with a high-k dielectric layer/metal gate structure is considered to be the solution to the problems faced by the traditional gate structure. The main or even the only method, the problems faced by the traditional gate structure mainly include gate leakage, polysilicon loss and boron penetration caused by the thin gate silicon oxide dielectric layer.

For transistor structures with higher process nodes, the high-k-metal gate process is usually a gate-last process, and its typical implementation process includes: first, forming a dummy gate on a semiconductor substrate structure, the dummy gate structure is composed of a bottom-up interface layer, a high-k dielectric layer, a cover layer and a sacrificial gate electrode layer; then, a gate spacer structure is formed on both sides of the dummy gate structure , and then remove the sacrificial gate electrode layer in the dummy gate structure, leaving a trench between the gate spacer structures; then, sequentially deposit a workfunction metal layer (workfunction metal layer) in the trench ), a barrier layer (barrier layer) and a wetting layer (wetting layer); finally, the metal gate material is filled to form a metal gate structure on the covering layer.

In the above process, the width of the formed metal gate structure is greater than or equal to the width of the cover layer/high-k dielectric layer, and the electrical performance test shows that the performance of the semiconductor device with the above structural characteristics is inferior to that of the metal gate The performance of semiconductor devices where the width of the structure is smaller than the width of the capping layer/high-k dielectric layer.

Therefore, it is necessary to propose a method to form a semiconductor device in which the width of the metal gate structure is smaller than the width of the capping layer/high-k dielectric layer.

Contents of the invention

Aiming at the deficiencies of the prior art, the present invention provides a method for manufacturing a semiconductor device, comprising: providing a semiconductor substrate, on which a high-k dielectric layer, a cover layer, and a sacrificial gate electrode layer are sequentially formed; Forming a patterned first hard mask layer on the sacrificial gate electrode layer; using the patterned first hard mask layer as a mask, sequentially etching the sacrificial gate electrode layer, the covering layer and the high k dielectric layer; removing the patterned first hard mask layer, and forming an interlayer dielectric layer to cover the stack formed by the sacrificial gate electrode layer, the capping layer and the high-k dielectric layer The formed dummy gate structure; removing the sacrificial gate electrode layer in the dummy gate structure, leaving a gate trench; forming a sidewall material layer on the sidewall of the gate trench; in the gate trench A metal gate structure is formed.

Further, after forming the interlayer dielectric layer, it further includes the step of performing chemical mechanical polishing to polish the interlayer dielectric layer until the top of the dummy gate structure is exposed.

Further, the step of forming the sidewall material layer includes forming a sidewall material layer to cover the top of the interlayer dielectric layer and the sidewall and bottom of the gate trench; a layer of sidewall material on the top and bottom of the gate trench.

Further, an interface layer is formed under the high-k dielectric layer.

Further, the material of the high-k dielectric layer is hafnium oxide; the material of the covering layer is titanium nitride.

Further, the material of the first hard mask layer includes dielectric material, metal and its nitride, polysilicon or a combination thereof.

Further, the material of the first hard mask layer is a dielectric material formed by a chemical vapor deposition process.

Further, the sidewall material layer is formed by using a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process.

Further, the material of the sidewall material layer is silicon nitride or oxide.

Further, the metal gate structure includes a work function metal layer, a barrier layer, a wetting layer and a metal gate material layer stacked from bottom to top.

According to the present invention, the width of the metal gate structure can be made smaller than the width of the covering layer and the high-k dielectric layer, further improving the performance of the finally formed semiconductor device.

Description of drawings

The following drawings of the invention are hereby included as part of the invention for understanding the invention. The accompanying drawings illustrate embodiments of the invention and description thereof to explain principles of the invention.

In the attached picture:

1A-1H are schematic cross-sectional views of devices respectively obtained by sequentially implementing steps of a method according to an exemplary embodiment of the present invention;

FIG. 2 is a flowchart of a method for forming a metal gate structure according to an exemplary embodiment of the present invention.

Detailed ways

In the following description, numerous specific details are given in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without one or more of these details. In other examples, some technical features known in the art are not described in order to avoid confusion with the present invention.

In order to thoroughly understand the present invention, detailed steps will be provided in the following description to illustrate the method for forming the metal gate structure proposed by the present invention. Obviously, the practice of the invention is not limited to specific details familiar to those skilled in the semiconductor arts. Preferred embodiments of the present invention are described in detail below, however, the present invention may have other embodiments besides these detailed descriptions.

It should be understood that when the terms "comprising" and/or "comprising" are used in this specification, they indicate the presence of the features, integers, steps, operations, elements and/or components, but do not exclude the presence or addition of one or Multiple other features, integers, steps, operations, elements, components and/or combinations thereof.

Hereinafter, detailed steps of forming a metal gate structure according to a method according to an exemplary embodiment of the present invention will be described with reference to FIGS. 1A-1H and FIG. 2 .

Referring to FIG. 1A-FIG. 1H , there are shown schematic cross-sectional views of devices respectively obtained by sequentially implementing steps of a method according to an exemplary embodiment of the present invention.

Firstly, as shown in FIG. 1A , a semiconductor substrate 100 is provided. The constituent material of the semiconductor substrate 100 can be undoped single crystal silicon, single crystal silicon doped with impurities, silicon on insulator (SOI) and the like. As an example, in this embodiment, single crystal silicon is selected as the constituent material of the semiconductor substrate 100 . Isolation structures, various well structures, and the like are formed in the semiconductor substrate 100 , which are omitted from illustration for simplicity.

An interface layer 101 , a high-k dielectric layer 102 , a capping layer 103 and a sacrificial gate electrode layer 104 are sequentially formed on a semiconductor substrate 100 . The material of the interface layer 101 includes oxide, such as silicon dioxide (SiO ₂ ). The material of the high-k dielectric layer 102 includes hafnium-containing materials, metal oxides or combinations thereof, such as hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, zirconium oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, Barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, aluminum oxide, etc., particularly preferred is hafnium oxide (HfO ₂ ). The material of the cover layer 103 includes metal or metal nitride, particularly preferably titanium nitride (TiN). The material of the sacrificial gate electrode layer 104 includes polysilicon. Various suitable processes familiar to those skilled in the art can be used to form the above layers, such as chemical vapor deposition process or physical vapor deposition process. It should be noted that the interface layer 101 is optional, and the function of forming the interface layer 101 is to improve the interface characteristics between the high-k dielectric layer 101 and the semiconductor substrate 100 .

Next, as shown in FIG. 1B , a first hard mask layer 105 and a second hard mask layer 106 are sequentially formed on the sacrificial gate electrode layer 104 . In this embodiment, the material of the first hard mask layer 105 includes SiN, SiON, SiO ₂ or a combination thereof; the material of the second hard mask layer 106 includes dielectric materials (such as SiC, SiCN, etc.), metals and their combinations. Nitride (such as TiN, TaN, Ti, etc.), polysilicon, or combinations thereof, are particularly preferred as dielectric materials that can be formed using a chemical vapor deposition process.

Next, the second hard mask layer 106 is patterned. Embodiments of this patterning are photolithography, nanoimprinting or digital angiography (DSA) followed by dry etching. The process steps involved in this patterned embodiment are photolithography and subsequent dry etching include: forming a photoresist layer on the second hard mask layer 106; Adhesive layer; With the patterned photoresist layer as a mask, perform etching to the second hard mask layer 106, which is dry etching and terminates when the first hard mask layer 105 is exposed; remove the photoresist layer, the removal of the photoresist layer can be performed using an ashing process. In order to ensure the quality of exposure, before forming the photoresist layer, an organic dielectric layer (ODL) and a bottom anti-reflective coating (BARC) are sequentially formed on the second hard mask layer 106: the function of the organic dielectric layer is to make the formation The top surface of the semiconductor substrate 100 after the aforementioned layers is flat, and the function of the bottom anti-reflection coating is to improve the quality of exposure and ensure the formation of a photoresist layer with expected patterns after development.

It should be noted that, when forming gates with different widths on the semiconductor substrate 100 , at least one patterning of the second hard mask layer 106 is performed. In addition, the second hard mask layer 106 may not be formed, and the first hard mask layer 105 may be directly patterned. At this time, the material of the first hard mask layer 105 includes a dielectric material (such as SiC, SiCN, etc.) , metals and their nitrides (such as TiN, TaN, Ti, etc.), polysilicon or combinations thereof, and dielectric materials that can be formed by chemical vapor deposition are particularly preferred.

Next, as shown in FIG. 1C, using the patterned second hard mask layer 106 as a mask, the first hard mask layer 105, the sacrificial gate electrode layer 104, the cover layer 103 and the high-k dielectric layer 102 are sequentially etched, The etching ends when the interface layer 101 is exposed, and when the interface layer 101 is not formed, the etching ends when the semiconductor substrate 100 is exposed. During the etching process, the etching gas for etching the first hard mask layer 105 and the sacrificial gate electrode layer 104 includes HBr, NF ₃ , Cl ₂ , O ₂ , N _{2 ,} etc., and for the covering layer 103 and the high-k dielectric Etching gases for layer 102 etching include Cl ₂ , BCl ₃ , NF ₃ , CH ₄ and the like.

Next, as shown in FIG. 1D, the second hard mask layer 106 and the first hard mask layer 105 are removed, and the removal of the second hard mask layer 106 and the first hard mask layer 105 can be performed by those skilled in the art. Familiar with various suitable processes, such as wet etching process.

Next, an interlayer dielectric layer 108 is formed to cover the dummy gate structure 107 formed by stacking the sacrificial gate electrode layer 104 , the capping layer 103 and the high-k dielectric layer 102 . The interlayer dielectric layer 108 can be formed by various suitable processes familiar to those skilled in the art, such as chemical vapor deposition process. The material of the interlayer dielectric layer 108 is usually oxide, such as silicon oxide. Then, chemical mechanical polishing is performed to polish the interlayer dielectric layer 108 until the top of the dummy gate structure 107 is exposed.

Next, as shown in FIG. 1E , the sacrificial gate electrode layer 104 in the dummy gate structure 107 is removed, leaving the gate trench 109 . The removal of the sacrificial gate electrode layer 104 may adopt various suitable processes familiar to those skilled in the art, such as dry etching or wet etching.

Next, as shown in FIG. 1F , a sidewall material layer 110 is formed to cover the top of the interlayer dielectric layer 108 and the sidewalls and bottom of the gate trench 109 . The sidewall material layer 110 can be formed by various suitable processes familiar to those skilled in the art, such as chemical vapor deposition process, physical vapor deposition process or atomic layer deposition process. The material of the sidewall material layer 110 is silicon nitride, oxide or other materials that can withstand the voltage between the gate and the source/drain region.

Next, as shown in FIG. 1G , the sidewall material layer 110 on the top of the interlayer dielectric layer 108 and the bottom of the gate trench 109 is removed. The removal of the sidewall material layer 110 may adopt various suitable processes familiar to those skilled in the art, such as an anisotropic dry etching process.

Next, as shown in FIG. 1H , a metal gate structure 111 is formed in the gate trench 109 . As an example, the metal gate structure 111 includes a work function metal layer 111a, a barrier layer 111b, a wetting layer 111c and a metal gate material layer 111d stacked from bottom to top, wherein the work function metal layer 111a includes one or more layer metal or metal compound, its constituent material includes titanium nitride, titanium aluminum alloy or tungsten nitride; the material of barrier layer 111b includes tantalum nitride or titanium nitride; the material of wetting layer 111c includes titanium or titanium aluminum alloy; metal gate The material of the electrode material layer 111d includes tungsten or aluminum. The work function metal layer 111a, the barrier layer 111b and the wetting layer 111c are formed by atomic layer deposition or physical vapor deposition, and the metal gate material layer 111d is formed by chemical vapor deposition or physical vapor deposition. Then, chemical mechanical polishing is performed to polish the materials of the above-mentioned layers, and the polishing is terminated when the interlayer dielectric layer 108 is exposed.

So far, all the process steps implemented by the method according to the exemplary embodiment of the present invention are completed, and then, the fabrication of the entire semiconductor device can be completed through subsequent processes. According to the present invention, the width of the metal gate structure can be made smaller than the width of the covering layer and the high-k dielectric layer, further improving the performance of the finally formed semiconductor device.

Referring to FIG. 2 , there is shown a flowchart of a method for forming a metal gate structure according to an exemplary embodiment of the present invention, which is used to briefly illustrate the flow of the entire manufacturing process.

In step 201, a semiconductor substrate is provided, and a high-k dielectric layer, a cover layer and a sacrificial gate electrode layer are sequentially formed on the semiconductor substrate;

In step 202, a patterned first hard mask layer is formed on the sacrificial gate electrode layer;

In step 203, using the patterned first hard mask layer as a mask, sequentially etch the sacrificial gate electrode layer, the cover layer and the high-k dielectric layer;

In step 204, the patterned first hard mask layer is removed, and an interlayer dielectric layer is formed to cover the dummy gate structure formed by stacking the sacrificial gate electrode layer, the cover layer and the high-k dielectric layer;

In step 205, removing the sacrificial gate electrode layer in the dummy gate structure, leaving gate trenches;

In step 206, a sidewall material layer is formed on the sidewall of the gate trench;

In step 207, a metal gate structure is formed in the gate trench.

The present invention has been described through the above-mentioned embodiments, but it should be understood that the above-mentioned embodiments are only for the purpose of illustration and description, and are not intended to limit the present invention to the scope of the described embodiments. In addition, those skilled in the art can understand that the present invention is not limited to the above-mentioned embodiments, and more variations and modifications can be made according to the teachings of the present invention, and these variations and modifications all fall within the claimed scope of the present invention. within the range. The protection scope of the present invention is defined by the appended claims and their equivalent scope.

Claims (10)

1. a manufacture method for semiconductor device, comprising:

Semiconductor substrate is provided, in described Semiconductor substrate, forms successively high k dielectric layer, cover layer and sacrificial gate dielectric layer;

In described sacrificial gate dielectric layer, form patterned the first hard mask layer;

Described patterned the first hard mask layer of take is mask, successively sacrificial gate dielectric layer, described cover layer and described high k dielectric layer described in etching;

Remove described patterned the first hard mask layer, and form interlayer dielectric layer, to cover the dummy gate structure being formed by described sacrificial gate dielectric layer, described cover layer and described high k dielectric layer stack;

Remove the sacrificial gate dielectric layer in described dummy gate structure, leave gate groove;

On the sidewall of described gate groove, form side-wall material layer;

In described gate groove, form metal gate structure.

2. method according to claim 1, is characterized in that, after forming described interlayer dielectric layer, also comprises and carries out cmp to grind the step of described interlayer dielectric layer, until expose the top of described dummy gate structure.

3. method according to claim 1, is characterized in that, the step that forms described side-wall material layer comprises formation side-wall material layer, to cover the top of described interlayer dielectric layer and the sidewall of described gate groove and bottom; Removal is positioned at the side-wall material layer on the top of described interlayer dielectric layer and the bottom of described gate groove.

4. method according to claim 1, is characterized in that, is also formed with boundary layer below described high k dielectric layer.

5. method according to claim 1, is characterized in that, the material of described high k dielectric layer is hafnium oxide; Described tectal material is titanium nitride.

6. method according to claim 1, is characterized in that, the material of described the first hard mask layer comprises dielectric material, metal and nitride thereof, polysilicon or its combination.

7. method according to claim 6, is characterized in that, the dielectric material of the material of described the first hard mask layer for adopting chemical vapor deposition method to form.

8. method according to claim 1, is characterized in that, adopts chemical vapor deposition method, physical gas-phase deposition or atom layer deposition process to form described side-wall material layer.

9. according to the method described in claim 1 or 8, it is characterized in that, the material of described side-wall material layer is silicon nitride or oxide.

10. method according to claim 1, is characterized in that, described metal gate structure comprises the stacking workfunction layers forming, barrier layer, soakage layer and metal gate material layer from bottom to top.