CN104124144A - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor device Download PDFInfo
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- CN104124144A CN104124144A CN201310143965.1A CN201310143965A CN104124144A CN 104124144 A CN104124144 A CN 104124144A CN 201310143965 A CN201310143965 A CN 201310143965A CN 104124144 A CN104124144 A CN 104124144A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 33
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 8
- 239000010410 layer Substances 0.000 claims abstract description 213
- 239000000463 material Substances 0.000 claims abstract description 53
- 229910052751 metal Inorganic materials 0.000 claims abstract description 35
- 239000002184 metal Substances 0.000 claims abstract description 35
- 239000011229 interlayer Substances 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 238000005530 etching Methods 0.000 claims abstract description 8
- 238000000034 method Methods 0.000 claims description 51
- 238000005229 chemical vapour deposition Methods 0.000 claims description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical class O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 9
- 239000003989 dielectric material Substances 0.000 claims description 8
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 7
- 230000004888 barrier function Effects 0.000 claims description 7
- 230000015572 biosynthetic process Effects 0.000 claims description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 7
- 229920005591 polysilicon Polymers 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 6
- 230000008021 deposition Effects 0.000 claims description 6
- 150000004767 nitrides Chemical class 0.000 claims description 5
- 238000005137 deposition process Methods 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 229910000449 hafnium oxide Inorganic materials 0.000 claims description 3
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical group [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- NHDHVHZZCFYRSB-UHFFFAOYSA-N pyriproxyfen Chemical compound C=1C=CC=NC=1OC(C)COC(C=C1)=CC=C1OC1=CC=CC=C1 NHDHVHZZCFYRSB-UHFFFAOYSA-N 0.000 description 7
- 238000001312 dry etching Methods 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 3
- 239000000470 constituent Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 229910000838 Al alloy Inorganic materials 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 2
- UQZIWOQVLUASCR-UHFFFAOYSA-N alumane;titanium Chemical compound [AlH3].[Ti] UQZIWOQVLUASCR-UHFFFAOYSA-N 0.000 description 2
- 239000006117 anti-reflective coating Substances 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- IATRAKWUXMZMIY-UHFFFAOYSA-N strontium oxide Chemical compound [O-2].[Sr+2] IATRAKWUXMZMIY-UHFFFAOYSA-N 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910004541 SiN Inorganic materials 0.000 description 1
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
- WUNIMIODOAGQAW-UHFFFAOYSA-N [O-2].[Ba+2].[Ti+4] Chemical compound [O-2].[Ba+2].[Ti+4] WUNIMIODOAGQAW-UHFFFAOYSA-N 0.000 description 1
- ILCYGSITMBHYNK-UHFFFAOYSA-N [Si]=O.[Hf] Chemical compound [Si]=O.[Hf] ILCYGSITMBHYNK-UHFFFAOYSA-N 0.000 description 1
- JIMUOUDLWPNFAY-UHFFFAOYSA-N [Si]=O.[Hf].[N] Chemical compound [Si]=O.[Hf].[N] JIMUOUDLWPNFAY-UHFFFAOYSA-N 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(iv) oxide Chemical group O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 229910000765 intermetallic Inorganic materials 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 238000002601 radiography Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- CZXRMHUWVGPWRM-UHFFFAOYSA-N strontium;barium(2+);oxygen(2-);titanium(4+) Chemical compound [O-2].[O-2].[O-2].[O-2].[Ti+4].[Sr+2].[Ba+2] CZXRMHUWVGPWRM-UHFFFAOYSA-N 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- -1 tungsten nitride Chemical class 0.000 description 1
- 238000009736 wetting Methods 0.000 description 1
- GFQYVLUOOAAOGM-UHFFFAOYSA-N zirconium(iv) silicate Chemical compound [Zr+4].[O-][Si]([O-])([O-])[O-] GFQYVLUOOAAOGM-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention provides a manufacturing method of a semiconductor device. The manufacturing method comprises: providing a semiconductor substrate and forming a high k dielectric layer, a covering layer, and a sacrificial gate electrode layer at the semiconductor substrate successively; forming a graphical first hard mask layer at the sacrificial gate electrode layer; etching the sacrificial gate electrode layer, the covering layer, and the high k dielectric layer successively by using the graphical first hard mask layer as a mask; removing the graphical first hard mask layer and forming an interlayer dielectric layer to cover a dummy grid structure formed by stacking of the sacrificial gate electrode layer, the covering layer, and the high k dielectric layer; removing the sacrificial gate electrode layer of the dummy grid structure to leave a gate trench; forming a side wall material layer at the side wall of the gate trench; and forming a metal gate structure in the gate trench. According to the invention, the width of the metal gate structure is less than the widths of the covering layer and the high k dielectric layer, thereby further improving the performance of the semiconductor device that is finally formed.
Description
Technical field
The present invention relates to semiconductor fabrication process, in particular to a kind of method that forms metal gate structure.
Background technology
At the node of semiconductor technology processing procedure, reach 28nm and when following, with high k dielectric layer/metal-gate structures, replace traditional silicon oxynitride or silica medium layer/polysilicon grating structure to be regarded as solving the main or even unique method of the problem that traditional grid structure faces, the problem that traditional grid structure faces mainly comprises grid leak electricity, polysilicon loss and by the caused boron penetration of thin oxide gate silicon dielectric layer.
For having compared with for the transistor arrangement of high technology node, described high k-metal gate process is generally rear grid (gate-last) technique, its typical implementation process comprises: first, in Semiconductor substrate, form dummy gate structure, described dummy gate structure consists of boundary layer from bottom to top, high k dielectric layer, cover layer and sacrificial gate dielectric layer; Then, in the both sides of described dummy gate structure, form grid gap wall structure, remove afterwards the sacrificial gate dielectric layer in described dummy gate structure, between described grid gap wall structure, leave a groove; Then, in described groove, deposit successively workfunction layers (workfunction metal layer), barrier layer (barrier layer) and soakage layer (wetting layer); Finally carry out the filling of metal gate material, to form metal gate structure on described cover layer.
In above-mentioned technical process, the width of formed metal gate structure is greater than or equal to the width of described cover layer/high k dielectric layer, and the width that the performance that shows to have the semiconductor device of said structure feature by electrical performance testing is inferior to metal gate structure is less than the performance of semiconductor device of the width of cover layer/high k dielectric layer.
Therefore, need to propose a kind of method, to form the width of metal gate structure, be less than the semiconductor device of the width of cover layer/high k dielectric layer.
Summary of the invention
For the deficiencies in the prior art, the invention provides a kind of manufacture method of semiconductor device, comprising: Semiconductor substrate is provided, in described Semiconductor substrate, forms successively high k dielectric layer, cover layer and sacrificial gate dielectric layer; In described sacrificial gate dielectric layer, form patterned the first hard mask layer; Described patterned the first hard mask layer of take is mask, successively sacrificial gate dielectric layer, described cover layer and described high k dielectric layer described in etching; Remove described patterned the first hard mask layer, and form interlayer dielectric layer, to cover the dummy gate structure being formed by described sacrificial gate dielectric layer, described cover layer and described high k dielectric layer stack; Remove the sacrificial gate dielectric layer in described dummy gate structure, leave gate groove; On the sidewall of described gate groove, form side-wall material layer; In described gate groove, form metal gate structure.
Further, after forming described interlayer dielectric layer, also comprise and carry out cmp to grind the step of described interlayer dielectric layer, until expose the top of described dummy gate structure.
Further, the step that forms described side-wall material layer comprises formation side-wall material layer, to cover the top of described interlayer dielectric layer and the sidewall of described gate groove and bottom; Removal is positioned at the side-wall material layer on the top of described interlayer dielectric layer and the bottom of described gate groove.
Further, below described high k dielectric layer, be also formed with boundary layer.
Further, the material of described high k dielectric layer is hafnium oxide; Described tectal material is titanium nitride.
Further, the material of described the first hard mask layer comprises dielectric material, metal and nitride thereof, polysilicon or its combination.
Further, the dielectric material of the material of described the first hard mask layer for adopting chemical vapor deposition method to form.
Further, adopt chemical vapor deposition method, physical gas-phase deposition or atom layer deposition process to form described side-wall material layer.
Further, the material of described side-wall material layer is silicon nitride or oxide.
Further, described metal gate structure comprises the stacking workfunction layers forming, barrier layer, soakage layer and metal gate material layer from bottom to top.
According to the present invention, can make the width of metal gate structure be less than the width of cover layer and high k dielectric layer, further promote the performance of the final semiconductor device forming.
Accompanying drawing explanation
Following accompanying drawing of the present invention is used for understanding the present invention in this as a part of the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.
In accompanying drawing:
The schematic cross sectional view of the device that Figure 1A-Fig. 1 H obtains respectively for method is implemented successively according to an exemplary embodiment of the present invention step;
Fig. 2 is that method forms the flow chart of metal gate structure according to an exemplary embodiment of the present invention.
Embodiment
In the following description, a large amount of concrete details have been provided to more thorough understanding of the invention is provided.Yet, it is obvious to the skilled person that the present invention can be implemented without one or more these details.In other example, for fear of obscuring with the present invention, for technical characterictics more well known in the art, be not described.
In order thoroughly to understand the present invention, will detailed step be proposed in following description, so that the method for the formation metal gate structure that explaination the present invention proposes.Obviously, execution of the present invention is not limited to the specific details that the technical staff of semiconductor applications has the knack of.Preferred embodiment of the present invention is described in detail as follows, yet except these are described in detail, the present invention can also have other execution modes.
Should be understood that, when using in this manual term " to comprise " and/or when " comprising ", it indicates and has described feature, integral body, step, operation, element and/or assembly, but do not get rid of, does not exist or additional one or more other features, integral body, step, operation, element, assembly and/or their combination.
Below, with reference to Figure 1A-Fig. 1 H and Fig. 2, the detailed step of method formation metal gate structure is according to an exemplary embodiment of the present invention described.
With reference to Figure 1A-Fig. 1 H, wherein show the schematic cross sectional view of the device that method is implemented successively according to an exemplary embodiment of the present invention step obtains respectively.
First, as shown in Figure 1A, provide Semiconductor substrate 100, the constituent material of Semiconductor substrate 100 can adopt unadulterated monocrystalline silicon, the monocrystalline silicon doped with impurity, silicon-on-insulator (SOI) etc.As example, in the present embodiment, the constituent material of Semiconductor substrate 100 is selected monocrystalline silicon.In Semiconductor substrate 100, to be formed with isolation structure, various trap (well) structure etc., in order simplifying, in diagram, to be omitted.
In Semiconductor substrate 100, form successively boundary layer 101, high k dielectric layer 102, cover layer 103 and sacrificial gate dielectric layer 104.The material of boundary layer 101 comprises oxide, for example silicon dioxide (SiO
2).The material of high k dielectric layer 102 comprises material, metal oxide or its combination containing hafnium, such as hafnium oxide, hafnium silicon oxide, nitrogen hafnium silicon oxide, lanthana, zirconia, zirconium silicon oxide, titanium oxide, tantalum oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia titanium, aluminium oxide etc., particularly preferably is hafnium oxide (HfO
2).The material of cover layer 103 comprises metal or metal nitride, particularly preferably is titanium nitride (TiN).The material of sacrificial gate dielectric layer 104 comprises polysilicon.Form the various suitable technique that above-mentioned each layer can adopt those skilled in the art to have the knack of, for example chemical vapor deposition method or physical gas-phase deposition.It should be noted that, boundary layer 101 is optional, and the effect that forms boundary layer 101 is the interfacial characteristics improving between high k dielectric layer 101 and Semiconductor substrate 100.
Then, as shown in Figure 1B, in sacrificial gate dielectric layer 104, form successively the first hard mask layer 105 and the second hard mask layer 106.In the present embodiment, the material of the first hard mask layer 105 comprises SiN, SiON, SiO
2or its combination; The material of the second hard mask layer 106 comprises dielectric material (such as SiC, SiCN etc.), metal and nitride thereof (such as TiN, TaN, Ti etc.), polysilicon or its combination, particularly preferably is the dielectric material that can adopt chemical vapor deposition method to form.
Next, graphical the second hard mask layer 106.This patterned execution mode is photoetching, nano impression or digital radiography (DSA) and dry etching afterwards.The processing step that this patterned execution mode relates to while being photoetching and dry etching afterwards comprises: on the second hard mask layer 106, form a photoresist layer; By techniques such as exposure, developments, form patterned photoresist layer; Take patterned photoresist layer as mask, carry out the etching to the second hard mask layer 106, this is etched to dry etching and stops when exposing the first hard mask layer 105; Remove photoresist layer, can adopt cineration technics to carry out the removal of photoresist layer.In order to guarantee the quality of exposure, conventionally before forming photoresist layer, on the second hard mask layer 106, form successively organic dielectric layer (ODL) and bottom antireflective coating (BARC): the effect of organic dielectric layer is that the end face of the Semiconductor substrate 100 after making to form aforementioned each layer is smooth, the effect of bottom antireflective coating is the quality that improves exposure, after guaranteeing to develop, forms the photoresist layer with expection figure.
It should be noted that, in Semiconductor substrate 100, form while thering is the grid of different width dimensions, at least carry out once graphical to the second hard mask layer 106.In addition, can not form the second hard mask layer 106, directly implement graphical to the first hard mask layer 105, now, the material of the first hard mask layer 105 comprises dielectric material (such as SiC, SiCN etc.), metal and nitride thereof (such as TiN, TaN, Ti etc.), polysilicon or its combination, particularly preferably is the dielectric material that can adopt chemical vapor deposition method to form.
Then, as shown in Figure 1 C, patterned the second hard mask layer 106 of take is mask, etching the first hard mask layer 105, sacrificial gate dielectric layer 104, cover layer 103 and high k dielectric layer 102 successively, described being etched in while exposing boundary layer 101 stops, in the situation that not forming boundary layer 101, described in be etched in while exposing Semiconductor substrate 100 and stop.In described etching process, the etched etching gas of the first hard mask layer 105 and sacrificial gate dielectric layer 104 is comprised to HBr, NF
3, Cl
2, O
2, N
2deng, cover layer 103 and the etched etching gas of high k dielectric layer 102 are comprised to Cl
2, BCl
3, NF
3, CH
4deng.
Then, as shown in Fig. 1 D, remove the second hard mask layer 106 and the first hard mask layer 105, the various suitable technique that enforcement can adopt those skilled in the art to have the knack of to the removal of the second hard mask layer 106 and the first hard mask layer 105, for example wet etching process.
Next, form interlayer dielectric layer 108, to cover by sacrificial gate dielectric layer 104, cover layer 103 and the stacking dummy gate structure forming 107 of high k dielectric layer 102.The various suitable technique that the formation of interlayer dielectric layer 108 can adopt those skilled in the art to have the knack of, for example chemical vapor deposition method.The material of interlayer dielectric layer 108 is generally oxide, for example silica.Then, carry out cmp to grind interlayer dielectric layer 108, until expose the top of dummy gate structure 107.
Then, as shown in Fig. 1 E, remove the sacrificial gate dielectric layer 104 in dummy gate structure 107, leave gate groove 109.The various suitable technique that enforcement can adopt those skilled in the art to have the knack of to the removal of sacrificial gate dielectric layer 104, for example dry etching or wet etching process.
Then,, as shown in Fig. 1 F, form side-wall material layer 110, to cover the top of interlayer dielectric layer 108 and sidewall and the bottom of gate groove 109.The various suitable technique that the formation of side-wall material layer 110 can adopt those skilled in the art to have the knack of, for example chemical vapor deposition method, physical gas-phase deposition or atom layer deposition process.The material of side-wall material layer 110 is that silicon nitride, oxide or other can bear the material of the voltage between grid and source/drain region.
Then, as shown in Figure 1 G, remove and be positioned at the side-wall material layer 110 on the top of interlayer dielectric layer 108 and the bottom of gate groove 109.The various suitable technique that the removal of enforcement oppose side wall material layer 110 can adopt those skilled in the art to have the knack of, for example anisotropic dry method etch technology.
Then,, as shown in Fig. 1 H, in gate groove 109, form metal gate structure 111.As example, metal gate structure 111 comprises the stacking workfunction layers 111a forming, barrier layer 111b, soakage layer 111c and metal gate material layer 111d from bottom to top, wherein, workfunction layers 111a comprises one or more layers metal or metallic compound, and its constituent material comprises titanium nitride, titanium-aluminium alloy or tungsten nitride; The material of barrier layer 111b comprises tantalum nitride or titanium nitride; The material of soakage layer 111c comprises titanium or titanium-aluminium alloy; The material of metal gate material layer 111d comprises tungsten or aluminium.Adopt atom layer deposition process or physical gas-phase deposition to form workfunction layers 111a, barrier layer 111b and soakage layer 111c, adopt chemical vapor deposition method or physical gas-phase deposition to form metal gate material layer 111d.Then, carry out cmp to grind above-mentioned layers of material, described grinding stops when exposing interlayer dielectric layer 108.
So far, complete whole processing steps that method is implemented according to an exemplary embodiment of the present invention, next, can complete by subsequent technique the making of whole semiconductor device.According to the present invention, can make the width of metal gate structure be less than the width of cover layer and high k dielectric layer, further promote the performance of the final semiconductor device forming.
With reference to Fig. 2, wherein show the flow chart of method formation metal gate structure according to an exemplary embodiment of the present invention, for schematically illustrating the flow process of whole manufacturing process.
In step 201, Semiconductor substrate is provided, in Semiconductor substrate, form successively high k dielectric layer, cover layer and sacrificial gate dielectric layer;
In step 202, in sacrificial gate dielectric layer, form patterned the first hard mask layer;
In step 203, patterned the first hard mask layer of take is mask, successively etch sacrificial gate electrode layer, cover layer and high k dielectric layer;
In step 204, remove patterned the first hard mask layer, and form interlayer dielectric layer, to cover the dummy gate structure being formed by sacrificial gate dielectric layer, cover layer and high k dielectric layer stack;
In step 205, remove the sacrificial gate dielectric layer in dummy gate structure, leave gate groove;
In step 206, on the sidewall of gate groove, form side-wall material layer;
In step 207, in gate groove, form metal gate structure.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment is the object for giving an example and illustrating just, but not is intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, according to instruction of the present invention, can also make more kinds of variants and modifications, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.
Claims (10)
1. a manufacture method for semiconductor device, comprising:
Semiconductor substrate is provided, in described Semiconductor substrate, forms successively high k dielectric layer, cover layer and sacrificial gate dielectric layer;
In described sacrificial gate dielectric layer, form patterned the first hard mask layer;
Described patterned the first hard mask layer of take is mask, successively sacrificial gate dielectric layer, described cover layer and described high k dielectric layer described in etching;
Remove described patterned the first hard mask layer, and form interlayer dielectric layer, to cover the dummy gate structure being formed by described sacrificial gate dielectric layer, described cover layer and described high k dielectric layer stack;
Remove the sacrificial gate dielectric layer in described dummy gate structure, leave gate groove;
On the sidewall of described gate groove, form side-wall material layer;
In described gate groove, form metal gate structure.
2. method according to claim 1, is characterized in that, after forming described interlayer dielectric layer, also comprises and carries out cmp to grind the step of described interlayer dielectric layer, until expose the top of described dummy gate structure.
3. method according to claim 1, is characterized in that, the step that forms described side-wall material layer comprises formation side-wall material layer, to cover the top of described interlayer dielectric layer and the sidewall of described gate groove and bottom; Removal is positioned at the side-wall material layer on the top of described interlayer dielectric layer and the bottom of described gate groove.
4. method according to claim 1, is characterized in that, is also formed with boundary layer below described high k dielectric layer.
5. method according to claim 1, is characterized in that, the material of described high k dielectric layer is hafnium oxide; Described tectal material is titanium nitride.
6. method according to claim 1, is characterized in that, the material of described the first hard mask layer comprises dielectric material, metal and nitride thereof, polysilicon or its combination.
7. method according to claim 6, is characterized in that, the dielectric material of the material of described the first hard mask layer for adopting chemical vapor deposition method to form.
8. method according to claim 1, is characterized in that, adopts chemical vapor deposition method, physical gas-phase deposition or atom layer deposition process to form described side-wall material layer.
9. according to the method described in claim 1 or 8, it is characterized in that, the material of described side-wall material layer is silicon nitride or oxide.
10. method according to claim 1, is characterized in that, described metal gate structure comprises the stacking workfunction layers forming, barrier layer, soakage layer and metal gate material layer from bottom to top.
Priority Applications (1)
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| CN102237363A (en) * | 2010-04-21 | 2011-11-09 | 中国科学院微电子研究所 | Structure of semiconductor device and forming method thereof |
| CN102299156A (en) * | 2010-06-28 | 2011-12-28 | 中国科学院微电子研究所 | Semiconductor device and manufacturing method thereof |
| CN102956542A (en) * | 2011-08-19 | 2013-03-06 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of semiconductor devices |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102237363A (en) * | 2010-04-21 | 2011-11-09 | 中国科学院微电子研究所 | Structure of semiconductor device and forming method thereof |
| CN102299156A (en) * | 2010-06-28 | 2011-12-28 | 中国科学院微电子研究所 | Semiconductor device and manufacturing method thereof |
| CN102956542A (en) * | 2011-08-19 | 2013-03-06 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of semiconductor devices |
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