CN104425351A - Trench forming method and semiconductor device manufacturing method - Google Patents

Trench forming method and semiconductor device manufacturing method Download PDF

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Publication number
CN104425351A
CN104425351A CN201310412253.5A CN201310412253A CN104425351A CN 104425351 A CN104425351 A CN 104425351A CN 201310412253 A CN201310412253 A CN 201310412253A CN 104425351 A CN104425351 A CN 104425351A
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China
Prior art keywords
layer
substrate
groove
etching
hard mask
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CN201310412253.5A
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唐兆云
闫江
李峻峰
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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Application filed by Institute of Microelectronics of CAS filed Critical Institute of Microelectronics of CAS
Priority to CN201310412253.5A priority Critical patent/CN104425351A/en
Priority to PCT/CN2013/086126 priority patent/WO2015035691A1/en
Publication of CN104425351A publication Critical patent/CN104425351A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3085—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
    • H—ELECTRICITY
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    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H01L22/26—Acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection, in-situ thickness measurement
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66553—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using inside spacers, permanent or not

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  • Engineering & Computer Science (AREA)
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  • Thin Film Transistor (AREA)

Abstract

The application discloses a trench forming method and a semiconductor device manufacturing method. An example method may include: forming a hard mask layer on a substrate; forming an etching stop determination layer on the hard mask layer; respectively patterning the etching stop determining layer and the hard mask layer to form a pattern corresponding to a trench to be formed therein; etching the substrate by using the patterned etching stop determining layer and the hard mask layer as masks to form a groove therein, wherein the etching of the substrate is performed while the etching stop determining layer is etched; and detecting a signal indicating that the etch stop determining layer is etched to an endpoint to determine a stop to the etching of the substrate.

Description

Groove forming method and method, semi-conductor device manufacturing method
Technical field
The disclosure relates to semiconductor applications, more specifically, relates to a kind of groove forming method and a kind of method, semi-conductor device manufacturing method.
Background technology
Need in numerous applications to form recessed groove in the substrate.But, along with the continuous miniaturization of device, be difficult to the formation, particularly its degree of depth and depth consistency that effectively control this groove.
Summary of the invention
Object of the present disclosure is to provide a kind of groove forming method and a kind of method, semi-conductor device manufacturing method at least in part, to control the degree of depth and the depth consistency of formed groove better.
According to an aspect of the present disclosure, provide a kind of method forming groove in the substrate, comprising: on substrate, form hard mask layer; Hard mask layer is formed etching stopping and determines layer; Respectively etching stopping is determined that layer and hard mask layer carry out composition, with the pattern that the groove formed with will be formed is corresponding wherein; Determine that layer and hard mask layer are for mask, etch substrate with the etching stopping of composition, to form groove wherein, wherein, to etching stopping, the etching of substrate is determined that layer etches simultaneously; And detection instruction etching stopping determines that layer is etched into the signal of terminal, to determine the stopping to substrate etching.
According to another aspect of the present disclosure, provide a kind of method manufacturing semiconductor device, comprising: according to said method, form groove in the substrate; Form side wall on the sidewalls of the trench; Fill shielding layer in the trench; Groove both sides formation source/drain region in the substrate; And the shielding layer of filling in removal groove, and it is stacking to form grid in the trench.
According to exemplary embodiment of the present invention, hard mask layer defines etching stopping and determines layer.Determining that layer is etched into the signal of terminal by detecting this etching stopping of instruction, the stopping to substrate etching can be determined.Like this, the depth consistency of the groove obtained can be improved.
Accompanying drawing explanation
By referring to the description of accompanying drawing to disclosure embodiment, above-mentioned and other objects of the present disclosure, feature and advantage will be more clear, in the accompanying drawings:
Fig. 1-6 shows the schematic diagram forming multiple stage in the flow process of groove in the substrate according to disclosure embodiment; And
Fig. 7-17 shows the schematic diagram in the multiple stage in the flow process of semiconductor device that manufactures based on groove according to another embodiment of the disclosure.
Embodiment
Below, with reference to the accompanying drawings embodiment of the present disclosure is described.But should be appreciated that, these describe just exemplary, and do not really want to limit the scope of the present disclosure.In addition, in the following description, the description to known features and technology is eliminated, to avoid unnecessarily obscuring concept of the present disclosure.
Various structural representations according to disclosure embodiment shown in the drawings.These figure not draw in proportion, wherein in order to the object of clear expression, are exaggerated some details, and may eliminate some details.The shape of the various regions shown in figure, layer and the relative size between them, position relationship are only exemplary, in reality may due to manufacturing tolerance or technical limitations deviation to some extent, and those skilled in the art can design the regions/layers with difformity, size, relative position in addition needed for actual.
In context of the present disclosure, when one deck/element is called be positioned at another layer/element " on " time, this layer/element can be located immediately on this another layer/element, or can there is intermediate layer/element between them.In addition, if one to be positioned at towards middle one deck/element another layer/element " on ", so when turn towards time, this layer/element can be positioned at this another layer/element D score.
According to embodiment of the present disclosure, provide a kind of method forming groove in the substrate.According to the method, substrate forms hard mask layer, this hard mask layer can serve as mask when etching substrate subsequently.In order to strengthen the control to substrate etching, particularly to the control of etching depth and depth consistency, an etching stopping can be formed determine layer on hard mask layer.This etching stopping determines that the material of layer can be chosen as and can be etched with substrate.Like this, can determine that layer is etched into the signal of terminal (that is, being substantially etched completely away) by detecting instruction etching stopping, determining the stopping to substrate etching.Such as, layer and substrate etch rate separately can be determined (such as according to the degree of depth of the groove that will etch and etching stopping, when both materials are identical, their etch rate can be roughly the same), determine that etching stopping determines the thickness of layer.
Before to substrate etching, can determine that layer and hard mask layer carry out composition to etching stopping respectively, with the pattern that the groove formed with will be formed is corresponding wherein.Like this, can they be mask subsequently, substrate be etched, to form corresponding groove wherein.
After so forming groove, based on the fluted substrate of this formation, semiconductor device can be manufactured further as field-effect transistor (FET).According to an example, grid can be formed in groove stacking.For this reason, can form side wall (spacer) on the sidewalls of the trench, it serves as grid side wall subsequently.For the impact avoiding source/drain formation processing stacking on grid, first can form source/drain region, then it is stacking to form grid.Such as, shielding layer can be filled in the trench, to cover groove (and the substrate portions of below, it serves as channel region subsequently).Subsequently, such as can by modes such as ion implantations, groove both sides formation source/drain region in the substrate.Then, shielding layer can be removed, and it is stacking to form grid in the trench.Grid are stacking can be various suitable forms, such as high-K gate dielectric and metal gate conductor (and the work function regulating course be optionally sandwiched between them) stacking.
According to an advantageous example, in order to avoid the manufacture difficulty (particularly when device is constantly miniaturized) of source/drain region contact site, after formation source/drain region, silicidation can be carried out, to form the contact site with source/drain region to the part that substrate is positioned at groove both sides.Owing to there is shielding layer (being generally dielectric substance) in groove, therefore this silicidation can not impact groove (and substrate portions of below) substantially.Thus contact site is self-aligned to the source/drain region of groove both sides.And the formation of this contact site does not need etching and the filling of contact hole, simplifies technique.
The disclosure can present in a variety of manners, below will describe some of them example.
As shown in Figure 1, substrate 1000 is provided.Substrate 1000 can be various forms of suitable substrate, such as body Semiconductor substrate is as Si, Ge etc., compound semiconductor substrate as SiGe, GaAs, GaSb, AlAs, InAs, InP, GaN, SiC, InGaAs, InSb, InGaSb etc., semiconductor-on-insulator substrate (SOI) etc.At this, be described for SOI substrate and silicon based material.But it is pointed out that the disclosure is not limited thereto.
Particularly, SOI substrate 1000 can comprise stacked base substrate 1000-1, buried insulating layer 1000-2 and soi layer 1000-3.Such as, base substrate 1000-1 can comprise body silicon.Buried insulating layer 1000-2 can comprise oxide (as silica), and thickness is such as about typical as soi layer 1000-3 can comprise crystalline silicon, and thickness is such as about typical as
In substrate 1000, yet forms both shallow trench isolation for being limited with source region from (STI) 1002.STI1002 such as can comprise oxide, and extends in buried insulating layer 1000-2, to guarantee effective electric isolution.It may occur to persons skilled in the art that various ways is to form this STI, does not repeat them here.In addition, on the surface of substrate 1000, pad oxide (pad oxide) layer 1004 can also be formed with.Pad oxide skin(coating) 1004 such as can be formed by thermal oxidation or deposit, and thickness can be about typical as
Then, as shown in Figure 2, can on substrate 1000 (or, at pad oxide skin(coating) 1004), such as by deposit as low-pressure chemical vapor deposition (LPCVD), form hard mask layer 1006.Such as, hard mask layer 1006 can comprise nitride (as silicon nitride) or nitrogen oxide (as silicon oxynitride), and thickness is about typical as
As mentioned above, in order to improve the control to etching, on hard mask layer 1006, such as, by deposit, etching stopping can be formed and determines layer 1010.In this example, etching stopping determines that layer 1010 comprises the silicon materials identical with substrate, such as amorphous silicon.But the disclosure is not limited thereto, etching stopping determines that layer 1010 also can comprise the other materials being different from substrate.In addition, in order to improve the combination that hard mask layer 1006 and etching stopping are determined between layer 1010, on hard mask layer 1006, first can form (such as, passing through deposit) pad oxide skin(coating) 1008, its thickness can be about typical as and then on this pad oxide skin(coating) 1008, form etching stopping determine layer 1010.
At this, the etch rate of layer 1010 and the degree of depth of needs etching can be determined according to the etch approach adopted subsequently to substrate (particularly, soi layer 1000-3) and etching stopping, determine that etching stopping determines the thickness of layer 1010.In this example, because soi layer 1000-3 and etching stopping determine that layer 1010 is silicon materials (is crystalline silicon, and is amorphous silicon), therefore by selecting suitable etch approach, their etch rate can be roughly the same.In this case, etching stopping can be determined that the thickness of layer 1010 is set to substantially the same with the degree of depth needing to etch.
Next, can etch.Particularly, as shown in Figure 3, can determine layer 1010 forms photoresist 1012 in etching stopping, and by photoetching, composition be carried out to photoresist 1012, with the opening G1 that the groove formed wherein with will be formed is corresponding.Then, with the photoresist 1012 of this composition for mask, can determine that layer 1010 and hard mask layer 1006 carry out selective etch as reactive ion etching (RIE) to etching stopping successively, with by the design transfer of opening G1 to wherein, thus form opening G2 wherein.In this example, also etch pad oxide skin(coating) 1004 and 1008, thus also form opening G2 wherein.Then, photoresist 1012 can be removed, as shown in Figure 5.
Next, as shown in Figure 6, the etching stopping after composition can determine that layer 1010 and hard mask layer 1006 are mask, etching be carried out as RIE to substrate (particularly, soi layer 1000-3), to form groove G3 wherein.At this, can determine that layer 1010 is etched into the signal of terminal according to etching stopping, determine to stop the moment to substrate etching.Such as, one endpoint signal can be detected, just stop the etching to substrate; Or, after detecting the end point signal, then over etching to a certain degree can be carried out.For the detection of endpoint signal, those skilled in the art can be susceptible to kinds of schemes.Such as, can detection etch product being passed through, judging that etching stopping determines whether layer 1010 is etched (such as, when nitrogen-containing products being detected, can judge that etching has arrived hard mask layer 1006, and therefore judge that etching stopping determines that layer 1010 is etched).
According to an example, after etching, the thickness of the remaining soi layer 1000-3 of beneath trenches is about 2-20nm.This part soi layer of beneath trenches can serve as the channel region CH of device subsequently.Subsequently, can removal pad oxide skin(coating) 1008, hard mask layer 1006 and pad oxide skin(coating) 1004.
Like this, just in substrate (particularly, soi layer 1000-3), groove G3 is defined.Due to the etching stopping condition of groove G3 effectively can be controlled, thus effectively can control the degree of depth and the depth consistency thereof of groove G3.
Based on this groove G3 formed in substrate, various structure can be made.Below, describe one and manufacture semiconductor device as the example of FET, wherein can form grid in groove G3 stacking.
Adapt with the grid that will be formed in groove are stacking, grid side wall can be formed on the sidewalls of the trench.Particularly, as shown in Figure 7, on the fluted substrate of formation, oxide skin(coating) 1014 (such as by original position vapor phase growth (ISSG)) and nitride layer 1016 (such as passing through deposit) can be formed successively.The thickness of oxide skin(coating) 1014 can be about typical as ; The thickness of nitride layer 1016 can be about typical as afterwards, as shown in Figure 8, anisotropic etching can be carried out as RIE to nitride layer 1016, thus form side wall.Here it is pointed out that according to another example, this oxide skin(coating) 1014 can not be formed, and only form nitride layer 1016.
When forming oxide skin(coating) 1014, after formation oxide skin(coating) 1014 and before formation nitride layer 1016, trap can also be carried out alternatively and inject and threshold voltage adjustments injection.
Subsequently, shielding layer can be filled in the trench.Particularly, as shown in Figure 9, can in the structure shown in Fig. 8, such as, by high-aspect-ratio depositing technics (HARP) or high-density plasma (HDP) deposit, form that one deck is thicker is enough to the masking material 1018 filling up groove.This masking material 1018 can comprise oxide.Then, as shown in Figure 10, planarization such as chemico-mechanical polishing (CMP) can be carried out.This planarization can soi layer 1000-3 (in this example, silicon) be stop-layer.Like this, shielding layer 1018 stays in groove, and exposes the part that soi layer 1000-3 is positioned at groove both sides, so that follow-up source/drain region process.
Then, as shown in figure 11, such as, can pass through ion implantation, groove both sides (particularly channel region CH both sides) form source/drain region (not shown) in the substrate.Such as, for N-shaped device, can implant n-type impurity as P, As etc.; For p-type device B etc., can implanted with p-type impurity.After ion implantation, annealing can also be carried out as spike annealing, to activate the ion of injection.
Here it is pointed out that the method forming source/drain region is not limited to ion implantation.Can selective etch be passed through, remove the part that soi layer 1000-3 is positioned at groove both sides.Then, source/drain region can be formed by the semiconductor layer (not shown) that epitaxial growth is other.Epitaxially grown while, can carry out in-situ doped.The semiconductor layer of growth can comprise the material (such as, SiGe or Si:C) being different from soi layer 1000-3, thus can to channel region CH stress application, with enhance device performance.
According to an advantageous example, can silicidation be passed through, directly form source and drain contacts in groove both sides.Particularly, as shown in figure 13, such as by deposit on substrate, a metal level 1020 can be formed.Metal level 1020 can comprise Ni, Ti, Co or its alloy, present in an amount at least sufficient to under soi layer 1000-3 fully react to generate metal silicide.Afterwards, annealing can be carried out as rapid thermal annealing (RTA), make metal level 1020 and soi layer 1000-3 (particularly, silicon wherein) there is silicification reaction, thus obtain metal silicide 1022, and unnecessary metal level 1020 can be removed, as shown in figure 14.This metal silicide 1022 is self-aligned to the source/drain region formed in soi layer 1000-3, and therefore can from the contact site when source/drain region.Subsequently, as shown in figure 15, such as, can pass through BOE or dilute hydrofluoric acid solution, remove shielding layer 1018.
In this case, damage the metal silicide 1022 of formation in order to avoid etching overlong time when removing shielding layer 1018, before carrying out silicidation, can as shown in figure 12, part removes shielding layer 1018.Figure 13 shows the situation structure after part removes shielding layer 1018 being formed metal level 1020.
In the example in figure 14, metal silicide 1022 is depicted as the whole thickness extending soi layer 1000-3.But the disclosure is not limited thereto.Such as, metal silicide 1022 can be formed at the top of soi layer 1000-3 near surface, and does not extend to the bottom of soi layer 1000-3.
Then, grid can be formed inside side wall 1016 in the trench stacking.Particularly, as shown in figure 16, in the structure shown in Figure 15, gate dielectric layer 1026 and grid conductor layer 1030 can be formed successively.Gate dielectric layer 1026 can comprise high-K gate dielectric as HfO 2, thickness is such as about grid conductor layer 1030 can comprise metal gate conductor as Ti, Ni etc.In addition, between gate dielectric layer 1026 and substrate, such as can pass through thermal oxidation or deposit, form an interfacial oxide layer 1024, thickness is about work function regulating course 1028 can be comprised, as TiN between high-K gate dielectric layer and the few conductor of metal.Subsequently, planarization can be carried out as CMP, to expose source and drain contacts 1022.Can find out, grid are stacking has substantially the same height with source and drain contacts 1022.This contributes to the making of follow-up interconnection structure.
Like this, the semiconductor device according to this embodiment is just obtained.The grid that this semiconductor device can comprise in the groove that is embedded in and formed in substrate are stacking.Grid are stacking can comprise gate dielectric layer 1026 and grid conductor layer 1030 (and optional interfacial oxide layer 1024 and work function regulating course 1028).The part CH being in the stacking below of grid in substrate can be used as the channel region of this device.This semiconductor device also comprise source/drain region that the stacking both sides of grid (more specifically, both sides, channel region) in the substrate formed and formed in the substrate with the source and drain contacts 1022 of source/drain region.Source and drain contacts 1022 can comprise the metal silicide formed through silicidation by the substrate portions of groove both sides.
Although it is pointed out that here in the above description for SOI substrate, technology of the present disclosure goes for other various substrates.In addition, in embodiment described above, it is stacking that the groove of formation is used for forming grid wherein, but technology of the present disclosure goes for the various application needing to be formed groove.
In the above description, the ins and outs such as composition, etching for each layer are not described in detail.But it will be appreciated by those skilled in the art that and by various technological means, the layer of required form, region etc. can be formed.In addition, in order to form same structure, those skilled in the art can also design the not identical method with method described above.In addition, although respectively describing each embodiment above, this is not also meaning that the measure in each embodiment can not advantageously be combined.
Above embodiment of the present disclosure is described.But these embodiments are only used to the object illustrated, and are not intended to limit the scope of the present disclosure.The scope of the present disclosure is by claims and equivalents thereof.Do not depart from the scope of the present disclosure, those skilled in the art can make multiple substituting and amendment, and these substitute and amendment all should fall within the scope of the present disclosure.

Claims (15)

1. form a method for groove in the substrate, comprising:
Substrate forms hard mask layer;
Hard mask layer is formed etching stopping and determines layer;
Respectively etching stopping is determined that layer and hard mask layer carry out composition, with the pattern that the groove formed with will be formed is corresponding wherein;
Determine that layer and hard mask layer are for mask, etch substrate with the etching stopping of composition, to form groove wherein, wherein, to etching stopping, the etching of substrate is determined that layer etches simultaneously; And
Detect instruction etching stopping and determine that layer is etched into the signal of terminal, to determine the stopping to substrate etching.
2. method according to claim 1, wherein, substrate comprises silicon, and etching stopping determines that layer comprises amorphous silicon.
3. method according to claim 2, wherein, hard mask layer comprises nitride.
4. method according to claim 3, also comprises:
Substrate is formed the first pad oxide skin(coating), and wherein hard mask layer is formed on this first pad oxide skin(coating); And/or
Hard mask layer is formed the second pad oxide skin(coating), and wherein etching stopping determines that layer is formed on this second pad oxide skin(coating).
5. manufacture a method for semiconductor device, comprising:
According to the method such as according to any one of claim 1-4, form groove in the substrate;
Form side wall on the sidewalls of the trench;
Fill shielding layer in the trench;
Groove both sides formation source/drain region in the substrate; And
Remove the shielding layer of filling in groove, and it is stacking to form grid in the trench.
6. method according to claim 5, wherein, formation source/drain region after and removal shielding layer before, the method also comprises:
Part substrate being positioned to groove both sides carries out silicidation, to form the contact site with source/drain region.
7. method according to claim 5, wherein, substrate comprises semiconductor-on-insulator SOI substrate, and SOI substrate comprises the base substrate, buried insulating layer and the soi layer that stack gradually, and wherein the S0I layer thickness of beneath trenches is about 2-20nm.
8. method according to claim 5, wherein, forms side wall and comprises:
The fluted substrate of formation forms oxide skin(coating);
Form nitride layer on the oxide layer; And
Anisotropic etching is carried out to nitride layer, to form side wall.
9. method according to claim 5, wherein, the thickness of side wall is about 3-50nm.
10. method according to claim 5, wherein, shielding layer comprises oxide.
11. methods according to claim 5, wherein, form source/drain region and comprise:
Ion implantation is carried out to substrate.
12. methods according to claim 5, wherein, carry out silicidation and comprise:
Substrate forms metal level; And
Anneal, make metal level and substrate generation silicification reaction.
13. methods according to claim 12, wherein, before formation metal level, the method also comprises:
Part removes shielding layer.
14. methods according to claim 12, wherein, metal level comprises Ni, Ti, Co or its alloy.
15. methods according to claim 5, wherein, grid are stacking comprises high-K gate dielectric and metal gate conductor.
CN201310412253.5A 2013-09-11 2013-09-11 Trench forming method and semiconductor device manufacturing method Pending CN104425351A (en)

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