WO2015035691A1

WO2015035691A1 - Ditch groove forming method and semiconductor component preparation method

Info

Publication number: WO2015035691A1
Application number: PCT/CN2013/086126
Authority: WO
Inventors: 唐兆云; 闫江; 李峻峰
Original assignee: 中国科学院微电子研究所
Priority date: 2013-09-11
Filing date: 2013-10-29
Publication date: 2015-03-19
Also published as: CN104425351A

Abstract

Disclosed are a ditch groove forming method and a semiconductor preparation method. An example method can comprise: forming a hard mask layer on a substrate; forming an etching stop determination layer on the head mask layer; patterning on the etching stop determination layer and the hard mask layer respectively to form an image corresponding to a ditch groove to be formed therein; using the etching stop determination layer and the hard mask layer with a pattern as a mask, and etching the substrate so as to form the ditch groove therein, wherein the substrate and the etching stop determination layer are etched simultaneously; and detecting a signal instructing that the etching stop determination layer is etched to an end point so as to determine to stop etching the substrate.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present application claims priority to Chinese Patent Application No. 201310412253.5, filed on Sep. 11, 2013, entitled,,,,,,,,,,, The entire contents are incorporated herein by reference. Technical field

The present disclosure relates to the field of semiconductors, and more particularly to a trench forming method and a semiconductor device manufacturing method.

Background technique

In many applications it is desirable to form IHJ-in trenches in the substrate. However, as devices continue to be miniaturized, it is difficult to effectively control the formation of such trenches, particularly their depth and depth uniformity.

Summary of the invention

It is an object of the present disclosure to at least partially provide a trench formation method and a semiconductor device fabrication method to better control the depth and depth uniformity of the trenches formed.

According to an aspect of the present disclosure, there is provided a method of forming a trench in a substrate, comprising: forming a hard mask layer on a substrate; forming an etch stop determining layer on the hard mask layer; respectively etching Stopping the determining layer and the hard mask layer to pattern a pattern corresponding to the trench to be formed therein; etching the substrate by patterning the etch stop determining layer and the hard mask layer as a mask, Forming a trench therein, wherein etching the substrate simultaneously etches the etch stop determining layer; and detecting a signal indicating that the etch stop determining layer is etched to the end point to determine etching of the substrate stop.

According to another aspect of the present disclosure, there is provided a method of fabricating a semiconductor device, comprising: forming a trench in a substrate according to the above method; forming a sidewall on a sidewall of the trench; filling a trench in the trench Forming source/drain regions on both sides of the trench in the substrate; and removing the shadowing layer filled in the trench and forming a gate stack in the trench.

According to an exemplary embodiment of the present invention, an etch stop determining layer is formed on the hard mask layer. By detecting a signal indicating that the etch stop determines that the layer is etched to the end point, the stop of etching the substrate can be determined Stop. In this way, the depth uniformity of the resulting trench can be improved. DRAWINGS

The above and other objects, features and advantages of the present disclosure will become more apparent from

1-6 are schematic diagrams showing various stages in a process of forming a trench in a substrate, in accordance with an embodiment of the present disclosure;

7-17 are schematic diagrams showing stages in a process of fabricating a semiconductor device based on trenches in accordance with another embodiment of the present disclosure. detailed description

Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. However, it should be understood that the description is only illustrative, and is not intended to limit the scope of the disclosure. In addition, descriptions of well-known structures and techniques are omitted in the following description in order to avoid unnecessarily obscuring the concept of the present disclosure.

Various structural schematics in accordance with embodiments of the present disclosure are shown in the drawings. The figures are not drawn to scale, and some details are exaggerated for clarity of presentation and some details may be omitted. The various regions, the shapes of the layers, and the relative sizes and positional relationships therebetween are merely exemplary, and may vary in practice due to manufacturing tolerances or technical limitations, and may be Areas/layers with different shapes, sizes, and relative positions can be additionally designed as needed.

In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, the layer/element may be located directly on the other layer/element, or a central layer may be present between them. element. In addition, if a layer/element is "on" another layer/element, the layer/element may be "under" the other layer/element when the orientation is reversed.

In accordance with an embodiment of the present disclosure, a method of forming a trench in a substrate is provided. According to the method, a hard mask layer is formed on the substrate, and the hard mask layer can serve as a mask when the substrate is subsequently etched. In order to enhance the control of the substrate etching, particularly the control of the etching depth and the depth uniformity, an etch stop determining layer may be formed on the hard mask layer. The material of the etch stop determining layer can be selected to be etched with the substrate. In this way, the layer can be etched to the end point by detecting the indication of the etch stop. The signal (ie, substantially completely etched away) is used to determine the cessation of the substrate etch. For example, the etch rate of each of the layer and the substrate can be determined according to the depth of the trench to be etched and the etch stop (for example, if the materials of the two are the same, their etch rates can be substantially the same) Etching stops determining the thickness of the layer.

Before the substrate is etched, the etch stop determining layer and the hard mask layer may be separately patterned to form a pattern corresponding to the trench to be formed therein. Thus, they can then be used as a mask to etch the substrate to form corresponding trenches therein.

After the trench is thus formed, a semiconductor device such as a field effect transistor (FET) can be further fabricated based on the trench-formed substrate. According to an example, a gate stack can be formed within the trench. To this end, a spacer can be formed on the sidewall of the trench, which then acts as a gate spacer. In order to avoid the influence of the source/drain formation process on the gate stack, the source/drain regions may be formed first, and then the gate stack is formed. For example, a masking layer can be filled in the trench to mask the trench (and the portion of the substrate below it, which then acts as a channel region). Subsequently, source/drain regions may be formed on both sides of the trench in the substrate, for example, by ion implantation or the like. Next, the masking layer can be removed and a gate stack formed in the trench. The gate stack can be in a variety of suitable forms, such as a stack of high-k gate dielectrics and metal gate conductors (and optionally a work function adjustment layer sandwiched between them).

According to an advantageous example, in order to avoid manufacturing difficulties of the source/drain contact portions (especially in the case where the device is continuously miniaturized), after the source/drain regions are formed, the portions of the substrate on both sides of the trench may be silicided. Processing to form a contact with the source/drain regions. Because of the presence of a masking layer (typically a dielectric material) in the trench, this silicidation does not substantially affect the trench (and the underlying substrate portion). Thereby, the contacts are self-aligned to the source/drain regions on both sides of the trench. Moreover, the formation of such contacts does not require etching and filling of the contact holes, simplifying the process.

The present disclosure can be presented in various forms, some of which are described below.

As shown in Figure 1, a substrate 1000 is provided. The substrate 1000 may be a suitable substrate in various forms, such as a bulk semiconductor substrate such as Si, Ge, etc., a compound semiconductor substrate such as SiGe, GaAs, GaSb, AlAs, InAs, InP, GaN, SiC, InGaAs, InSb, InGaSb Etc., a semiconductor-on-insulator (SOI), etc. Here, an SOI substrate and a silicon-based material will be described as an example. However, it should be noted that this disclosure is not limited to this.

Specifically, the SOI substrate 1000 may include a stacked base substrate 1000-1, a buried insulating layer 1000-2 and SOI layer 1000-3. For example, the base substrate 1000-1 may include bulk silicon. The buried insulating layer 1000-2 may include an oxide such as silicon oxide having a thickness of, for example, about 500 A to 4000 A, typically such as 1450A. The SOI layer 1000-3 may comprise crystalline silicon having a thickness of, for example, about 400 A to 3000 A, typically 500 A.

In the substrate 1000, a shallow trench isolation (STI) 1002 for defining an active region is also formed. STI 1002, for example, can include an oxide and extend into buried insulating layer 1000-2 to ensure efficient electrical isolation. A person skilled in the art can think of various ways to form such an STI, and details are not described herein again. Further, on the surface of the substrate 1000, a pad oxide layer 1004 may be formed. The pad oxide layer 1004 can be formed, for example, by thermal oxidation or deposition, and can have a thickness of about 50 A - 300 A, typically 120 A.

Then, as shown in FIG. 2, a hard mask layer 1006 can be formed on the substrate 1000 (or on the pad oxide layer 1004), such as by deposition, such as low pressure chemical vapor deposition (LPCVD). For example, the hard mask layer 1006 may comprise a nitride (e.g., silicon nitride) or an oxynitride (e.g., silicon oxynitride) having a thickness of about 100-2000 A, typically 600 A.

As described above, in order to improve the control of the etching, the etch stop determining layer 1010 may be formed on the hard mask layer 1006, for example, by deposition. In this example, the etch stop determining layer 1010 includes the same silicon material as the substrate, such as amorphous silicon. However, the present disclosure is not limited thereto, and the etching stop determination layer

1010 may also include other materials than the substrate. In addition, in order to improve the bonding between the hard mask layer 1006 and the etch stop determining layer 1010, a pad oxide layer 1008 may be formed (eg, by deposition) on the hard mask layer 1006, and the thickness may be approximately 50A - 300 A, typically 100 A, is then formed on the pad oxide layer 1008 to form an etch stop determining layer 1010.

Here, the etching stop determination layer can be determined according to the etching scheme of the subsequent etching scheme for the substrate (specifically, the SOI layer 1000-3) and the etching stop of the etching stop determining layer 1010 and the depth to be etched. 1010 thickness. In this example, since the SOI layer 1000-3 and the etch stop determining layer 1010 are both silicon materials (one is crystalline silicon and one is amorphous silicon), their etching rates can be selected by selecting an appropriate etching scheme. Roughly the same. In this case, the thickness of the etch stop determining layer 1010 can be set to be substantially the same as the depth to be etched.

Next, etching can be performed. Specifically, as shown in FIG. 3, a photoresist 1012 may be formed on the etch stop determining layer 1010, and the photoresist 1012 may be patterned by photolithography to form therein. An opening G1 corresponding to the groove to be formed. Then, using the patterned photoresist 1012 as a mask, the etch stop determining layer 1010 and the hard mask layer 1006 may be selectively etched, such as reactive ion etching (RIE), to transfer the pattern of the opening G1. Thereto, thereby forming an opening G2 therein. In this example, the pad oxide layers 1004 and 1008 are also etched to also form the opening G2 therein. Then, the photoresist 1012 can be removed, as shown in FIG.

Next, as shown in FIG. 6, the patterned etch stop determining layer 1010 and the hard mask layer 1006 may be used as a mask, and the substrate (specifically, the SOI layer 1000-3) is etched, such as RIE, to A groove G3 is formed therein. Here, the timing at which the etching of the substrate is stopped may be determined based on the etch stop determining the signal that the layer 1010 is etched to the end point. For example, the etching of the substrate may be stopped as soon as the end point signal is detected; or, after the end point signal is detected, a certain degree of over etching may be performed. Those skilled in the art will be able to devise various schemes for the detection of the endpoint signal. For example, it can be determined whether the etching stop determination layer 1010 has been etched by detecting the etching product (for example, when the nitrogen-containing product is detected, it can be judged that the etching has reached the hard mask layer 1006, and thus the judgment is inscribed The etch stop determining layer 1010 has been etched).

According to an example, after etching, the remaining SOI layer 1000-3 under the trench has a thickness of about 2-20 nm. This portion of the SOI layer below the trench can then act as the channel region CH of the device. Subsequently, the pad oxide layer 1008, the hard mask layer 1006, and the pad oxide layer 1004 may be removed.

Thus, the groove G3 is formed in the substrate (specifically, the SOI layer 1000-3). Since the etching stop condition of the trench G3 can be effectively controlled, the depth of the trench G3 and its depth uniformity can be effectively controlled.

Various structures can be fabricated based on such a groove G3 formed in the substrate. Hereinafter, an example of manufacturing a semiconductor device such as a FET, in which a gate stack can be formed in the trench G3, will be described.

In accordance with the gate stack to be formed in the trench, a gate spacer can be formed on the sidewall of the trench. Specifically, as shown in FIG. 7, an oxide layer 1014 (eg, by in-situ vapor phase epitaxy (ISSG)) and a nitride layer 1016 (eg, by deposition) may be sequentially formed on the substrate on which the trench is formed. The oxide layer 1014 may have a thickness of about 50 A to 200 A, typically such as germanium; and the nitride layer 1016 may have a thickness of about 80 A to 300 A, typically 150 A. Thereafter, as shown in FIG. 8, the nitride layer 1016 may be anisotropically etched such as RIE to form sidewall spacers. It should be noted here that, according to another example, such an oxide layer 1014 may not be formed, but only the nitride layer 1016 may be formed. In the case of forming the oxide layer 1014, well implantation and threshold voltage adjustment implantation may optionally be performed after the formation of the oxide layer 1014 and before the formation of the nitride layer 1016.

Subsequently, the mask can be filled in the trench. Specifically, as shown in FIG. 9, a structure thickened by a high aspect ratio deposition process (HARP) or a high density plasma (HDP) may be formed on the structure shown in FIG. The shielding material 1018 of the groove. The masking material 1018 can comprise an oxide. Then, as shown in Fig. 10, a planarization process such as chemical mechanical polishing (CMP) can be performed. This planarization process can be a stop layer for the SOI layer 1000-3 (in this example, silicon). Thus, the masking layer 1018 remains in the trench and exposes portions of the SOI layer 1000-3 on both sides of the trench to facilitate subsequent source/drain processing.

Then, as shown in Fig. 11, for example, source/drain regions (not shown) may be formed on both sides of the trench in the substrate (particularly on both sides of the channel region CH) by ion implantation. For example, for n-type devices, can n-type impurities be injected? , As, etc.; For p-type device B, etc., p-type impurities can be implanted. After the ion implantation, annealing such as spike annealing may also be performed to activate the implanted ions.

It should be noted here that the method of forming the source/drain regions is not limited to ion implantation. A portion of the SOI layer 1000-3 on both sides of the trench can be removed by selective etching. Then, the source/drain regions can be formed by epitaxially growing an additional semiconductor layer (not shown). In-situ doping can be performed while epitaxial growth. The grown semiconductor layer may include a material different from the SOI layer 1000-3 (e.g., SiGe or Si: C) so that stress can be applied to the channel region CH to enhance device performance.

According to an advantageous example, the source/drain contacts can be formed directly on both sides of the trench by silicidation. Specifically, as shown in Fig. 13, a metal layer 1020 may be formed on the substrate, for example, by deposition. The metal layer 1020 may comprise Ni, Ti, Co or alloys thereof in an amount sufficient to sufficiently react with the underlying SOI layer 1000-3 to form a metal silicide. Thereafter, annealing, such as rapid thermal annealing (RTA), may be performed to cause a metallization reaction between the metal layer 1020 and the SOI layer 1000-3 (specifically, silicon therein) to obtain a metal silicide 1022, and the excess metal layer 1020 may be removed. , as shown in Figure 14. This metal silicide 1022 is self-aligned to the source/drain regions formed in the SOI layer 1000-3, and thus can be from the contact portion of the source/drain regions. Subsequently, as shown in Fig. 15, the shielding layer 1018 can be removed, for example, by BOE or by diluting the hydrofluoric acid solution.

In this case, in order to avoid damage to the formed metal silicide 1022 when the etching time is too long to remove the shielding layer 1018, before the silicidation treatment, as shown in FIG. Layer 1018. FIG. 13 shows a case where the metal layer 1020 is formed on the structure after the mask layer 1018 is partially removed.

In the example of Fig. 14, metal silicide 1022 is shown as extending the entire thickness of SOI layer 1000-3. However, the present disclosure is not limited thereto. For example, the metal silicide 1022 may be formed on the upper portion of the SOI layer 1000-3 near the surface without extending to the bottom of the SOI layer 1000-3.

Next, a gate stack can be formed inside the sidewalls 1016 in the trench. Specifically, as shown in FIG. 16, the gate dielectric layer 1026 and the gate conductor layer 1030 may be sequentially formed on the structure shown in FIG. The gate dielectric layer 1026 may include a high-k gate dielectric such as Hf0 ₂ having a thickness of, for example, about 15 A -40 A; the gate conductor layer 1030 may include a metal gate conductor such as Ti, Ni, or the like. In addition, an interfacial oxide layer 1024 having a thickness of about 6 A -15 A may be formed between the gate dielectric layer 1026 and the substrate, for example, by thermal oxidation or deposition. A work function adjusting layer 1028, such as TiN, may be included between the high K gate dielectric layer and the metal less conductor. Subsequently, a planarization process such as CMP may be performed to expose the source/drain contact portion 1022. It can be seen that the gate stack has substantially the same height as the source/drain contacts 1022. This facilitates the fabrication of subsequent interconnect structures.

Thus, the semiconductor device according to this embodiment is obtained. The semiconductor device can include a gate stack embedded within a trench formed in the substrate. The gate stack can include a gate dielectric layer 1026 and a gate conductor layer 1030 (and optionally an interfacial oxide layer 1024 and a work function adjustment layer 1028). A portion of the substrate under the gate stack can be used as the channel region of the device. The semiconductor device further includes source/drain regions formed on both sides of the gate stack (more specifically, both sides of the channel region) in the substrate, and source/drain contacts 1022 formed in the substrate with source/drain regions. The source/drain contact portion 1022 may include a metal silicide formed by silicidation of a substrate portion on both sides of the trench.

It should be noted here that although the SOI substrate is exemplified in the above description, the technology of the present disclosure can be applied to other various substrates. Additionally, in the embodiments described above, the trenches are formed to form a gate stack therein, but the techniques of the present disclosure may be applied to various applications requiring trench formation.

In the above description, detailed descriptions of the technical details such as patterning and etching of the respective layers have not been made. However, it should be understood by those skilled in the art that layers, regions, and the like of a desired shape can be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method that is not exactly the same as the method described above. In addition, although the respective embodiments have been described above, this does not mean that the measures in the respective embodiments are not advantageously used in combination. The embodiments of the present disclosure have been described above. However, the examples are for illustrative purposes only and are not intended to limit the scope of the disclosure. The scope of the disclosure is defined by the appended claims and their equivalents. Numerous alternatives and modifications may be made by those skilled in the art without departing from the scope of the present disclosure.

Claims

Claim

A method of forming a trench in a substrate, comprising:

Forming a hard mask layer on the substrate;

Forming an etch stop determining layer on the hard mask layer;

Etching the etch stop determining layer and the hard mask layer respectively to form a pattern corresponding to the trench to be formed therein;

Etching the substrate to form a trench therein by patterning the etch stop determining layer and the hard mask layer as a mask, wherein etching the substrate simultaneously etching the etch stop determining layer; as well as

A signal indicative of the etch stop determining layer being etched to the end point is detected to determine the stop of the substrate etch.

2. The method according to claim 1, wherein the substrate comprises silicon, and the etch stop determining layer comprises amorphous silicon.

3. The method of claim 2, wherein the hard mask layer comprises a nitride.

4. The method of claim 3, further comprising:

Forming a first pad oxide layer on the substrate, wherein a hard mask layer is formed on the first pad oxide layer; and/or

A second pad oxide layer is formed on the hard mask layer, wherein an etch stop determining layer is formed on the second pad oxide layer.

5. A method of fabricating a semiconductor device, comprising:

A method of forming a trench in a substrate according to any one of claims 1 to 4;

Forming a sidewall on the sidewall of the trench;

Filling the trench with a shielding layer;

Forming source/drain regions on both sides of the trench in the substrate;

The shadowing layer filled in the trench is removed and a gate stack is formed in the trench.

6. The method according to claim 5, wherein, after forming the source/drain regions and before removing the masking layer, the method further comprises:

A portion of the substrate on both sides of the trench is silicided to form a contact portion with the source/drain regions.

7. The method of claim 5, wherein the substrate comprises a semiconductor-on-insulator SOI The substrate, the SOI substrate includes a base substrate, a buried insulating layer, and an SOI layer which are sequentially stacked, wherein the SOI layer under the trench has a thickness of about 2-20 nm.

8. The method of claim 5, wherein forming the sidewall spacers comprises:

Forming an oxide layer on the substrate on which the trench is formed;

Forming a nitride layer on the oxide layer;

The nitride layer is anisotropically etched to form sidewall spacers.

9. The method of claim 5, wherein the sidewall spacer has a thickness of about 3-50 nm.

10. The method of claim 5, wherein the masking layer comprises an oxide.

11. The method of claim 5, wherein forming the source/drain regions comprises:

The substrate is ion implanted.

12. The method of claim 5, wherein performing the silicidation process comprises: forming a metal layer on the substrate;

Annealing is performed to cause a silicidation reaction between the metal layer and the substrate.

13. The method according to claim 12, wherein before the forming of the metal layer, the method further comprises:

Partially remove the masking layer.

14. The method according to claim 12, wherein the metal layer comprises Ni, Ti, Co or an alloy thereof.

15. The method of claim 5, wherein the gate stack comprises a high K gate dielectric and a metal gate conductor.