WO2015035691A1 - Méthode de formation de rainure et méthode de préparation de composant semi-conducteur - Google Patents

Méthode de formation de rainure et méthode de préparation de composant semi-conducteur Download PDF

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Publication number
WO2015035691A1
WO2015035691A1 PCT/CN2013/086126 CN2013086126W WO2015035691A1 WO 2015035691 A1 WO2015035691 A1 WO 2015035691A1 CN 2013086126 W CN2013086126 W CN 2013086126W WO 2015035691 A1 WO2015035691 A1 WO 2015035691A1
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layer
substrate
trench
forming
hard mask
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PCT/CN2013/086126
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English (en)
Chinese (zh)
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唐兆云
闫江
李峻峰
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中国科学院微电子研究所
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Publication of WO2015035691A1 publication Critical patent/WO2015035691A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3085—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H01L22/26—Acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection, in-situ thickness measurement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66553—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using inside spacers, permanent or not

Definitions

  • the present disclosure relates to the field of semiconductors, and more particularly to a trench forming method and a semiconductor device manufacturing method.
  • IHJ-in trenches In many applications it is desirable to form IHJ-in trenches in the substrate. However, as devices continue to be miniaturized, it is difficult to effectively control the formation of such trenches, particularly their depth and depth uniformity.
  • a method of forming a trench in a substrate comprising: forming a hard mask layer on a substrate; forming an etch stop determining layer on the hard mask layer; respectively etching Stopping the determining layer and the hard mask layer to pattern a pattern corresponding to the trench to be formed therein; etching the substrate by patterning the etch stop determining layer and the hard mask layer as a mask, Forming a trench therein, wherein etching the substrate simultaneously etches the etch stop determining layer; and detecting a signal indicating that the etch stop determining layer is etched to the end point to determine etching of the substrate stop.
  • a method of fabricating a semiconductor device comprising: forming a trench in a substrate according to the above method; forming a sidewall on a sidewall of the trench; filling a trench in the trench Forming source/drain regions on both sides of the trench in the substrate; and removing the shadowing layer filled in the trench and forming a gate stack in the trench.
  • an etch stop determining layer is formed on the hard mask layer.
  • the stop of etching the substrate can be determined Stop. In this way, the depth uniformity of the resulting trench can be improved.
  • 1-6 are schematic diagrams showing various stages in a process of forming a trench in a substrate, in accordance with an embodiment of the present disclosure
  • FIGS. 7-17 are schematic diagrams showing stages in a process of fabricating a semiconductor device based on trenches in accordance with another embodiment of the present disclosure. detailed description
  • a layer/element when a layer/element is referred to as being "on" another layer/element, the layer/element may be located directly on the other layer/element, or a central layer may be present between them. element. In addition, if a layer/element is "on” another layer/element, the layer/element may be "under” the other layer/element when the orientation is reversed.
  • a method of forming a trench in a substrate is provided.
  • a hard mask layer is formed on the substrate, and the hard mask layer can serve as a mask when the substrate is subsequently etched.
  • an etch stop determining layer may be formed on the hard mask layer. The material of the etch stop determining layer can be selected to be etched with the substrate. In this way, the layer can be etched to the end point by detecting the indication of the etch stop. The signal (ie, substantially completely etched away) is used to determine the cessation of the substrate etch.
  • the etch rate of each of the layer and the substrate can be determined according to the depth of the trench to be etched and the etch stop (for example, if the materials of the two are the same, their etch rates can be substantially the same) Etching stops determining the thickness of the layer.
  • the etch stop determining layer and the hard mask layer may be separately patterned to form a pattern corresponding to the trench to be formed therein. Thus, they can then be used as a mask to etch the substrate to form corresponding trenches therein.
  • a semiconductor device such as a field effect transistor (FET) can be further fabricated based on the trench-formed substrate.
  • FET field effect transistor
  • a gate stack can be formed within the trench.
  • a spacer can be formed on the sidewall of the trench, which then acts as a gate spacer.
  • the source/drain regions may be formed first, and then the gate stack is formed.
  • a masking layer can be filled in the trench to mask the trench (and the portion of the substrate below it, which then acts as a channel region).
  • source/drain regions may be formed on both sides of the trench in the substrate, for example, by ion implantation or the like.
  • the masking layer can be removed and a gate stack formed in the trench.
  • the gate stack can be in a variety of suitable forms, such as a stack of high-k gate dielectrics and metal gate conductors (and optionally a work function adjustment layer sandwiched between them).
  • the portions of the substrate on both sides of the trench may be silicided. Processing to form a contact with the source/drain regions. Because of the presence of a masking layer (typically a dielectric material) in the trench, this silicidation does not substantially affect the trench (and the underlying substrate portion). Thereby, the contacts are self-aligned to the source/drain regions on both sides of the trench. Moreover, the formation of such contacts does not require etching and filling of the contact holes, simplifying the process.
  • a masking layer typically a dielectric material
  • a substrate 1000 is provided.
  • the substrate 1000 may be a suitable substrate in various forms, such as a bulk semiconductor substrate such as Si, Ge, etc., a compound semiconductor substrate such as SiGe, GaAs, GaSb, AlAs, InAs, InP, GaN, SiC, InGaAs, InSb, InGaSb Etc., a semiconductor-on-insulator (SOI), etc.
  • SOI semiconductor-on-insulator
  • an SOI substrate and a silicon-based material will be described as an example. However, it should be noted that this disclosure is not limited to this.
  • the SOI substrate 1000 may include a stacked base substrate 1000-1, a buried insulating layer 1000-2 and SOI layer 1000-3.
  • the base substrate 1000-1 may include bulk silicon.
  • the buried insulating layer 1000-2 may include an oxide such as silicon oxide having a thickness of, for example, about 500 A to 4000 A, typically such as 1450A.
  • the SOI layer 1000-3 may comprise crystalline silicon having a thickness of, for example, about 400 A to 3000 A, typically 500 A.
  • a shallow trench isolation (STI) 1002 for defining an active region is also formed.
  • STI 1002 for example, can include an oxide and extend into buried insulating layer 1000-2 to ensure efficient electrical isolation.
  • a person skilled in the art can think of various ways to form such an STI, and details are not described herein again.
  • a pad oxide layer 1004 may be formed on the surface of the substrate 1000.
  • the pad oxide layer 1004 can be formed, for example, by thermal oxidation or deposition, and can have a thickness of about 50 A - 300 A, typically 120 A.
  • a hard mask layer 1006 can be formed on the substrate 1000 (or on the pad oxide layer 1004), such as by deposition, such as low pressure chemical vapor deposition (LPCVD).
  • the hard mask layer 1006 may comprise a nitride (e.g., silicon nitride) or an oxynitride (e.g., silicon oxynitride) having a thickness of about 100-2000 A, typically 600 A.
  • the etch stop determining layer 1010 may be formed on the hard mask layer 1006, for example, by deposition.
  • the etch stop determining layer 1010 includes the same silicon material as the substrate, such as amorphous silicon.
  • the present disclosure is not limited thereto, and the etching stop determination layer
  • a pad oxide layer 1008 may be formed (eg, by deposition) on the hard mask layer 1006, and the thickness may be approximately 50A - 300 A, typically 100 A, is then formed on the pad oxide layer 1008 to form an etch stop determining layer 1010.
  • the etching stop determination layer can be determined according to the etching scheme of the subsequent etching scheme for the substrate (specifically, the SOI layer 1000-3) and the etching stop of the etching stop determining layer 1010 and the depth to be etched. 1010 thickness.
  • the SOI layer 1000-3 and the etch stop determining layer 1010 are both silicon materials (one is crystalline silicon and one is amorphous silicon), their etching rates can be selected by selecting an appropriate etching scheme. Roughly the same.
  • the thickness of the etch stop determining layer 1010 can be set to be substantially the same as the depth to be etched.
  • etching can be performed. Specifically, as shown in FIG. 3, a photoresist 1012 may be formed on the etch stop determining layer 1010, and the photoresist 1012 may be patterned by photolithography to form therein. An opening G1 corresponding to the groove to be formed. Then, using the patterned photoresist 1012 as a mask, the etch stop determining layer 1010 and the hard mask layer 1006 may be selectively etched, such as reactive ion etching (RIE), to transfer the pattern of the opening G1. Thereto, thereby forming an opening G2 therein. In this example, the pad oxide layers 1004 and 1008 are also etched to also form the opening G2 therein. Then, the photoresist 1012 can be removed, as shown in FIG.
  • RIE reactive ion etching
  • the patterned etch stop determining layer 1010 and the hard mask layer 1006 may be used as a mask, and the substrate (specifically, the SOI layer 1000-3) is etched, such as RIE, to A groove G3 is formed therein.
  • the timing at which the etching of the substrate is stopped may be determined based on the etch stop determining the signal that the layer 1010 is etched to the end point. For example, the etching of the substrate may be stopped as soon as the end point signal is detected; or, after the end point signal is detected, a certain degree of over etching may be performed.
  • Those skilled in the art will be able to devise various schemes for the detection of the endpoint signal.
  • the etching stop determination layer 1010 can be determined whether the etching stop determination layer 1010 has been etched by detecting the etching product (for example, when the nitrogen-containing product is detected, it can be judged that the etching has reached the hard mask layer 1006, and thus the judgment is inscribed The etch stop determining layer 1010 has been etched).
  • the remaining SOI layer 1000-3 under the trench has a thickness of about 2-20 nm. This portion of the SOI layer below the trench can then act as the channel region CH of the device. Subsequently, the pad oxide layer 1008, the hard mask layer 1006, and the pad oxide layer 1004 may be removed.
  • the groove G3 is formed in the substrate (specifically, the SOI layer 1000-3). Since the etching stop condition of the trench G3 can be effectively controlled, the depth of the trench G3 and its depth uniformity can be effectively controlled.
  • Various structures can be fabricated based on such a groove G3 formed in the substrate.
  • a semiconductor device such as a FET, in which a gate stack can be formed in the trench G3, will be described.
  • a gate spacer can be formed on the sidewall of the trench.
  • an oxide layer 1014 eg, by in-situ vapor phase epitaxy (ISSG)
  • a nitride layer 1016 eg, by deposition
  • the oxide layer 1014 may have a thickness of about 50 A to 200 A, typically such as germanium; and the nitride layer 1016 may have a thickness of about 80 A to 300 A, typically 150 A.
  • the nitride layer 1016 may be anisotropically etched such as RIE to form sidewall spacers.
  • such an oxide layer 1014 may not be formed, but only the nitride layer 1016 may be formed.
  • well implantation and threshold voltage adjustment implantation may optionally be performed after the formation of the oxide layer 1014 and before the formation of the nitride layer 1016.
  • the mask can be filled in the trench.
  • a structure thickened by a high aspect ratio deposition process (HARP) or a high density plasma (HDP) may be formed on the structure shown in FIG.
  • the masking material 1018 can comprise an oxide.
  • a planarization process such as chemical mechanical polishing (CMP) can be performed.
  • CMP chemical mechanical polishing
  • This planarization process can be a stop layer for the SOI layer 1000-3 (in this example, silicon).
  • the masking layer 1018 remains in the trench and exposes portions of the SOI layer 1000-3 on both sides of the trench to facilitate subsequent source/drain processing.
  • the method of forming the source/drain regions is not limited to ion implantation.
  • a portion of the SOI layer 1000-3 on both sides of the trench can be removed by selective etching.
  • the source/drain regions can be formed by epitaxially growing an additional semiconductor layer (not shown). In-situ doping can be performed while epitaxial growth.
  • the grown semiconductor layer may include a material different from the SOI layer 1000-3 (e.g., SiGe or Si: C) so that stress can be applied to the channel region CH to enhance device performance.
  • the source/drain contacts can be formed directly on both sides of the trench by silicidation.
  • a metal layer 1020 may be formed on the substrate, for example, by deposition.
  • the metal layer 1020 may comprise Ni, Ti, Co or alloys thereof in an amount sufficient to sufficiently react with the underlying SOI layer 1000-3 to form a metal silicide.
  • annealing such as rapid thermal annealing (RTA)
  • RTA rapid thermal annealing
  • This metal silicide 1022 is self-aligned to the source/drain regions formed in the SOI layer 1000-3, and thus can be from the contact portion of the source/drain regions. Subsequently, as shown in Fig. 15, the shielding layer 1018 can be removed, for example, by BOE or by diluting the hydrofluoric acid solution.
  • FIG. 13 shows a case where the metal layer 1020 is formed on the structure after the mask layer 1018 is partially removed.
  • metal silicide 1022 is shown as extending the entire thickness of SOI layer 1000-3.
  • the present disclosure is not limited thereto.
  • the metal silicide 1022 may be formed on the upper portion of the SOI layer 1000-3 near the surface without extending to the bottom of the SOI layer 1000-3.
  • a gate stack can be formed inside the sidewalls 1016 in the trench.
  • the gate dielectric layer 1026 and the gate conductor layer 1030 may be sequentially formed on the structure shown in FIG.
  • the gate dielectric layer 1026 may include a high-k gate dielectric such as Hf0 2 having a thickness of, for example, about 15 A -40 A; the gate conductor layer 1030 may include a metal gate conductor such as Ti, Ni, or the like.
  • an interfacial oxide layer 1024 having a thickness of about 6 A -15 A may be formed between the gate dielectric layer 1026 and the substrate, for example, by thermal oxidation or deposition.
  • a work function adjusting layer 1028 such as TiN, may be included between the high K gate dielectric layer and the metal less conductor. Subsequently, a planarization process such as CMP may be performed to expose the source/drain contact portion 1022. It can be seen that the gate stack has substantially the same height as the source/drain contacts 1022. This facilitates the fabrication of subsequent interconnect structures.
  • the semiconductor device can include a gate stack embedded within a trench formed in the substrate.
  • the gate stack can include a gate dielectric layer 1026 and a gate conductor layer 1030 (and optionally an interfacial oxide layer 1024 and a work function adjustment layer 1028).
  • a portion of the substrate under the gate stack can be used as the channel region of the device.
  • the semiconductor device further includes source/drain regions formed on both sides of the gate stack (more specifically, both sides of the channel region) in the substrate, and source/drain contacts 1022 formed in the substrate with source/drain regions.
  • the source/drain contact portion 1022 may include a metal silicide formed by silicidation of a substrate portion on both sides of the trench.
  • the SOI substrate is exemplified in the above description, the technology of the present disclosure can be applied to other various substrates. Additionally, in the embodiments described above, the trenches are formed to form a gate stack therein, but the techniques of the present disclosure may be applied to various applications requiring trench formation.

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Abstract

L'invention concerne une méthode de formation de rainure et une méthode de préparation de semi-conducteur. Une méthode illustrative peut comprendre les étapes suivantes : former une couche de masque dur sur un substrat ; former une couche de détermination d'arrêt de gravure sur la couche de masque dur ; appliquer un motif sur la couche de détermination d'arrêt de gravure et la couche de masque dur, respectivement, pour former une image correspondant à une rainure à former dedans ; utiliser la couche de détermination d'arrêt de gravure et la couche de masque dur avec un motif comme masque, et graver le substrat de façon à former la rainure dedans, le substrat et la couche de détermination d'arrêt de gravure étant gravés simultanément ; et détecter un signal indiquant que la couche de détermination d'arrêt de gravure est gravée jusqu'à un point final de façon à déterminer qu'il faut arrêter la gravure du substrat.
PCT/CN2013/086126 2013-09-11 2013-10-29 Méthode de formation de rainure et méthode de préparation de composant semi-conducteur WO2015035691A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201310412253.5A CN104425351A (zh) 2013-09-11 2013-09-11 沟槽形成方法和半导体器件制造方法
CN201310412253.5 2013-09-11

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WO2015035691A1 true WO2015035691A1 (fr) 2015-03-19

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