CN105428394B - 鳍部件的结构及其制造方法 - Google Patents
鳍部件的结构及其制造方法 Download PDFInfo
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- CN105428394B CN105428394B CN201510193452.0A CN201510193452A CN105428394B CN 105428394 B CN105428394 B CN 105428394B CN 201510193452 A CN201510193452 A CN 201510193452A CN 105428394 B CN105428394 B CN 105428394B
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Abstract
半导体器件包括:第一鳍部件,嵌入在设置在半导体衬底上方的隔离结构内,第一鳍部件具有第一侧壁和相对的第二侧壁以及从第一侧壁延伸至第二侧壁的顶面。该器件也包括:第二鳍部件,设置在隔离结构上方并且具有第三侧壁和第四侧壁。第三侧壁与第一鳍部件的第一侧壁对准。该器件也包括:栅极介电层,直接设置在第一鳍部件的顶面上以及第二鳍部件的第三侧壁和第四侧壁上;以及栅电极,设置在栅极介电层上方。本发明还涉及鳍部件的结构及其制造方法。
Description
技术领域
本发明涉及集成电路器件,更具体地,涉及鳍部件的结构及其制造方法。
背景技术
半导体集成电路(IC)工业已经经历了快速增长。在IC演化过程中,功能密度(即,每芯片面积的互连器件的数量)普遍增大,而几何尺寸(即,使用制造工艺可以构建的最小部件(或线))却已减小。这种按比例缩小工艺通常通过提高生产效率和降低相关成本来提供益处。
这种按比例缩小也增大了处理和制造IC的复杂性,并且为了实现这些进步,需要IC处理和制造中的类似发展。例如,已经引入诸如鳍式场效应晶体管(FinFET)的三维晶体管来替代平面晶体管。虽然现有的FinFET器件和制造FinFET器件的方法通常能够满足它们的预期目的,但是它们不是在所有方面都完全令人满意。例如,期望具有较小宽度的鳍部件。
发明内容
为了解决现有技术中存在的问题,本发明提供了一种器件,包括:第一鳍部件,嵌入在设置在半导体衬底上方的隔离结构内,所述第一鳍部件具有第一侧壁和相对的第二侧壁以及从所述第一侧壁延伸至所述第二侧壁的顶面;第二鳍部件,设置在所述隔离结构上方并且具有第三侧壁和第四侧壁,其中,所述第三侧壁与所述第一鳍部件的所述第一侧壁对准;栅极介电层,直接设置在所述第一鳍部件的所述顶面上以及所述第二鳍部件的所述第三侧壁和所述第四侧壁上;以及栅电极,设置在所述栅极介电层上方。
在上述器件中,其中,所述第四侧壁直接设置在所述隔离结构上方。
在上述器件中,其中,所述器件还包括:第三鳍部件,设置在所述隔离结构上方并且具有第五侧壁,其中,所述第五侧壁与所述第一鳍部件的所述第二侧壁对准。
在上述器件中,其中,所述器件还包括:第三鳍部件,设置在所述隔离结构上方并且具有第五侧壁,其中,所述第五侧壁与所述第一鳍部件的所述第二侧壁对准,其中,所述第一鳍部件由第一半导体材料形成,并且所述第二鳍部件和所述第三鳍部件均由不同于所述第一半导体材料的第二半导体材料形成。
在上述器件中,其中,所述器件还包括:第三鳍部件,设置在所述隔离结构上方并且具有第五侧壁,其中,所述第五侧壁与所述第一鳍部件的所述第二侧壁对准,其中,所述第一鳍部件由第一半导体材料形成,并且所述第二鳍部件和所述第三鳍部件均由不同于所述第一半导体材料的第二半导体材料形成,其中,所述第二半导体材料包括单晶外延半导体材料。
在上述器件中,其中,所述器件还包括:第三鳍部件,设置在所述隔离结构上方并且具有第五侧壁,其中,所述第五侧壁与所述第一鳍部件的所述第二侧壁对准,其中,所述第二鳍部件与所述第三鳍部件间隔开,从而使得所述第二鳍部件与所述第三鳍部件彼此不物理接触。
在上述器件中,其中,所述器件还包括:第三鳍部件,设置在所述隔离结构上方并且具有第五侧壁,其中,所述第五侧壁与所述第一鳍部件的所述第二侧壁对准,其中,所述栅极介电层直接设置在所述第三鳍部件的所述第五侧壁上。
在上述器件中,其中,所述第二鳍部件具有与所述第三鳍部件相同的宽度,所述宽度小于所述第一鳍部件的宽度。
在上述器件中,其中,所述第二鳍部件包括平行于第二部分的第一部分,其中,所述第一部分的半导体材料与所述第二部分中的半导体材料不同。
在上述器件中,其中,所述第二鳍部件包括平行于第二部分的第一部分,其中,所述第一部分的半导体材料与所述第二部分中的半导体材料不同,其中,所述第一部分的宽度与所述第二部分的宽度的总和小于所述第一鳍部件的宽度。
根据本发明的另一方面,提供了一种半导体器件,包括:第一半导体鳍部件,位于衬底上方;凹进的第一半导体鳍部件,嵌入在设置在所述衬底上方的隔离结构内;第二半导体鳍部件,设置在所述隔离结构上方并且具有第三侧壁和第四侧壁,其中,所述第三侧壁与所述第一半导体鳍部件的第一侧壁对准,所述第四侧壁直接设置在所述隔离结构上方;第三半导体鳍部件,设置在所述隔离结构上方并且具有第五侧壁和第六侧壁,其中,所述第五侧壁与第一半导体鳍部件的第二侧壁对准,所述第六侧壁直接设置在所述隔离结构上方;栅极堆叠件,设置在所述衬底上方,所述栅极堆叠件包裹在所述第一半导体鳍部件上方;以及另一栅极堆叠件,设置在所述衬底上方,所述另一栅极堆叠件包裹在所述第二半导体鳍部件和所述第三半导体鳍部件上方。
在上述半导体器件中,其中,所述第一半导体鳍部件由第一半导体材料形成,并且所述第二半导体鳍部件和所述第三半导体鳍部件均由不同于所述第一半导体材料的第二半导体材料形成。
在上述半导体器件中,其中,所述第二半导体鳍部件与所述第三半导体鳍部件间隔开,从而使得所述第二半导体鳍部件与所述第三半导体鳍部件彼此不物理接触。
在上述半导体器件中,其中,所述栅极堆叠件的栅极介电层直接设置在所述凹进的第一半导体鳍部件的顶面上、所述第二半导体鳍部件的所述第三侧壁和所述第四侧壁上、以及所述第三半导体鳍部件的所述第五侧壁和所述第六侧壁上。
在上述半导体器件中,其中,所述第二半导体鳍部件具有与所述第三半导体鳍部件相同的宽度,所述宽度小于所述第一半导体鳍部件的宽度。
在上述半导体器件中,其中,所述第二半导体鳍部件包括平行于第二部分的第一部分,其中,所述第一部分的半导体材料与所述第二部分中的半导体材料不同。
在上述半导体器件中,其中,所述半导体器件还包括:源极/漏极部件,位于所述衬底上方,并且位于所述栅极堆叠件旁边。
根据本发明的又一方面,提供了一种用于制造半导体器件的方法,所述方法包括:在衬底上方形成第一鳍部件;在所述第一鳍部件之间形成隔离区,其中,所述第一鳍部件的上部位于所述隔离区之上;在所述第一鳍部件的上部上方外延生长半导体材料层;在具有所述半导体材料层的所述第一鳍部件的部分上方形成伪栅极堆叠件;使所述伪栅极堆叠件旁边的所述第一鳍部件凹进以形成源极/漏极(S/D)凹槽;在所述S/D凹槽上方形成S/D部件;去除所述伪栅极堆叠件以暴露具有所述半导体材料层的所述第一鳍部件;使所述半导体材料层凹进以暴露所述第一鳍部件的顶面并且留下沿着所述第一鳍部件的侧壁的所述半导体材料层;以及选择性地去除所述第一鳍部件的上部,同时使得所述半导体材料层保持完整以形成第二鳍部件和第三鳍部件。
在上述方法中,其中,所述方法还包括:在所述衬底上方形成高k/金属栅极(HK/MG)堆叠件,所述HK/MG堆叠件包裹在所述第二鳍部件和所述第三鳍部件上方。
在上述方法中,其中,在所述衬底上方形成所述第一鳍部件包括:在所述衬底上方形成芯轴部件;在所述芯轴部件上方沉积材料层;各向异性地蚀刻所述材料层以形成沿着所述芯轴部件的侧壁的间隔件;以及选择性地去除所述芯轴部件,同时使得所述间隔件保持完整以形成所述第一鳍部件。
附图说明
当结合附图进行阅读时,从以下详细描述可最佳理解本发明。应该注意,根据工业中的标准实践,各个部件未按比例绘制。实际上,为了清楚的讨论,各个部件的尺寸可以任意地增大或减小。
图1至图4A-图4B是根据一些实施例的示例性半导体器件的截面图。
图5是根据一些实施例的示例性半导体器件的图解立体图。
图6是沿着图5中的线A-A截取的示例性半导体器件的截面图。
图7是根据一些实施例的示例性半导体器件的图解立体图。
图8至图9、图10A至图10B和图11A至图11B是沿着图7中的线B-B截取的示例性半导体器件的截面图。
图12是根据一些实施例的用于制造半导体器件的示例性方法的流程图。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的许多不同实施例或实例。下面描述了部件和布置的具体实例以简化本发明。当然,这些仅仅是实例,而不旨在限制本发明。例如,在以下描述中,在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例,并且也可以包括在第一部件和第二部件之间可以形成额外的部件,从而使得第一部件和第二部件可以不直接接触的实施例。此外,本发明可在各个实例中重复参考标号和/或字符。该重复是为了简单和清楚的目的,并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且,为便于描述,在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等的空间相对术语,以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外,空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上),而本文使用的空间相对描述符可以同样地作相应的解释。
本发明针对但不以其他方式限制于FinFET器件。例如,FinFET器件可以是包括P型金属氧化物半导体(PMOS)FinFET器件和N型金属氧化物半导体(NMOS)FinFET器件的互补金属氧化物半导体(CMOS)器件。以下公开内容将继续以FinFET实例来说明本发明的各个实施例。然而,应该理解,除非特别声明,本申请不应限制于特定类型的器件。
图1至图11是根据一些示例实施例的在半导体器件200的制造中的中间阶段的截面图和立体图。图1示出了初始结构的截面图。初始结构包括衬底210。衬底210可以是块状硅衬底。可选地,衬底210可以包括:元素半导体,诸如晶体结构的硅或锗;化合物半导体,诸如硅锗、碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟;或它们的组合。可能的衬底210也包括绝缘体上硅(SOI)衬底。使用注氧隔离(SIMOX)、晶圆接合和/或其他合适的方法制造SOI衬底。
一些示例性衬底210也包括绝缘层。绝缘层包括任何合适的材料,包括氧化硅、蓝宝石和/或它们的组合。示例性绝缘层可以是埋氧层(BOX)。通过诸如注入(例如,SIMOX)、氧化、沉积和/或其他合适的工艺的任何合适的工艺形成绝缘体。在一些示例性FinFET前体200中,绝缘层是绝缘体上硅衬底的部件(例如,层)。
衬底210也可以包括各种掺杂区。掺杂区可以掺杂有诸如硼或BF2的p型掺杂剂;诸如磷或砷的n型掺杂剂;或它们的组合。可以以P阱结构、N阱结构、双阱结构或使用凸起结构在衬底210上直接形成掺杂区。衬底210还可以包括各种有源区,诸如配置为用于N型金属氧化物半导体晶体管器件的区域和配置为用于P型金属氧化物半导体晶体管器件的区域。
在衬底210上方形成多个芯轴部件220。在一些实施例中,通过以下步骤形成芯轴部件220:沉积诸如介电材料(例如,氧化硅、氮化硅)的芯轴材料层;在芯轴材料层上方形成图案化的光刻胶层;以及将图案化的光刻胶层用作蚀刻掩模来蚀刻芯轴材料层,从而形成芯轴部件220。可以通过包括热氧化、化学汽相沉积(CVD)工艺、等离子体增强CVD(PECVD)、原子层沉积(ALD)和/或本领域已知的其他方法的各种方法来沉积芯轴材料。示例性光刻工艺包括:在衬底上面(例如,在硅层上)形成光刻胶层(抗蚀剂),将光刻胶曝光成一图案,实施曝光后烘烤工艺,以及显影光刻胶以形成包括光刻胶的掩蔽元件。然后掩蔽元件用于蚀刻芯轴材料以形成芯轴部件220。蚀刻工艺是湿蚀刻、干蚀刻和/或它们的组合。
在芯轴部件220的侧壁上形成多个第一间隔件230。在一个实施例中,第一间隔件230的形成包括:在衬底210和芯轴部件220上沉积第一间隔件材料层,以及之后对第一间隔件材料层实施各向异性蚀刻,从而形成第一间隔件230。在本实施例中,第一间隔件材料层可以包括第一半导体材料,诸如锗(Ge)、硅(Si)、砷化镓(GaAs)、砷化铝镓(AlGaAs)、硅锗(SiGe)、磷砷化镓(GaAsP)、锑化镓(GaSb)、锑化铟(InSb)、砷化铟镓(InGaAs)、砷化铟(InAs)或其他合适的材料。可以通过诸如CVD沉积技术(例如,汽相外延(VPE)和/或超高真空CVD(UHV-CVD))、分子束外延和/或其他合适的工艺的外延生长工艺沉积第一间隔件材料层。然后通过使用诸如具有氯基化学物质的DRIE(深反应离子蚀刻)的机制实施各向异性干蚀刻。其他干蚀刻剂气体包括CF4、NF3、SF6和He。通过控制第一间隔件材料层的厚度,第一间隔件230形成为具有第一宽度w1。在本实施例中,第一间隔件230的第一宽度w1设计为第一鳍部件的宽度,第一鳍部件将在之后描述。
图2示出了通过去除芯轴部件220形成第一沟槽240而第一间隔件230是完整的。在本实施例中,可以通过包括选择性湿蚀刻、选择性干蚀刻和/或它们的组合的选择性蚀刻来去除芯轴部件220。剩余的第一间隔件230称为第一鳍部件245并且具有第一宽度w1。
图3示出了通过用介电层填充沟槽240以及然后回蚀刻介电层以暴露第一鳍部件245的上部,而在两个邻近的第一鳍部件245之间形成隔离部件250。隔离部件250可以包括氧化硅、氮化硅、碳化硅或其他合适的材料。在本实施例中,通过选择性蚀刻回蚀刻介电层,并且因此第一鳍部件245的暴露的上部具有第一宽度w1。第一鳍部件245的上部具有高度h,高度h设计为将形成的第二鳍部件的高度。
图4A示出了衬底210具有第一区260和第二区270。在第一区260中,第二半导体材料层310包裹在第一鳍部件245的暴露的上部上方。而在第二区270中,第一硬掩模280覆盖衬底210(包括第一鳍部件245)。第二半导体材料层310可以包括Ge、Si、GaAs、AlGaAs、SiGe、GaAsP、GaSb、InSb、InGaAs、InAs或其他合适的材料。在本实施例中,第二半导体材料层310不同于第一鳍部件245。例如,第一鳍部件245是Si,而第二半导体材料层310是SiGe。在一个实施例中,第二半导体材料层310包括单晶外延半导体材料。第二半导体材料层310形成为具有沿着第一鳍部件245的侧壁的第二宽度w2。在一个实施例中,第二宽度w2小于第一宽度w1。在一个实施例中,第二宽度w2是第一宽度w1的一半。作为实例,第一宽度w1为约32nm,而第二宽度w2为约16nm。第一硬掩模280可以包括诸如氧化硅或氮化硅的介电材料。第一硬掩模280也可以包括图案化的光刻胶层。
图4B示出,在第一区260中,在第二半导体材料层310上方形成具有第三宽度w3的第三半导体材料层320。在一个实施例中,第二宽度w2和第三宽度w3的总和小于第一宽度w1。第三半导体材料层320不同于第二半导体材料层310。贯穿说明书,当声称第三半导体材料层320的组分不同于第二半导体材料层310的组分时,这表明第三半导体材料层320和第二半导体材料层310的任何一个层具有另一层中没有的元素,和/或出现在第三半导体材料层320和第二半导体材料层310中的一种或多种元素在第三层320和第二层310的其中一层中的原子百分比与在另一层中的相同元素的原子百分比不同。第二半导体材料层310和第三半导体材料层320与第一鳍部件245不同。
图5示出,在一些实施例中,衬底210具有源极/漏极区410和栅极区420。在一些实施例中,源极/漏极区410是源极区,而另一个源极/漏极区410是漏极区。源极/漏极区410由栅极区420分隔开。
在衬底210中的栅极区420上方形成一个或多个伪栅极堆叠件510,包括包裹在第一鳍部件245的部分上方。在实施高温热工艺(诸如在源极/漏极形成期间的热工艺)之后,伪栅极堆叠件510之后将由高k(HK)和金属栅极(MG)替代。伪栅极堆叠件510可以包括伪栅极介电层520和多晶硅层530。
沿着伪栅极堆叠件510的侧壁形成栅极间隔件540。栅极间隔件540可以包括诸如氧化硅、氮化硅、碳化硅、氮氧化硅或它们的组合的介电材料。用于栅极间隔件540的典型的形成方法包括在栅极堆叠件上方沉积栅极间隔件介电材料以及然后各向异性地回蚀刻栅极间隔件介电材料。回蚀刻工艺可以包括多步蚀刻以获得蚀刻选择性、灵活性和期望的过蚀刻控制。
图6示出了沿着图5中的S/D区410中的线A-A截取的半导体器件200的截面图。使第一鳍部件245凹进(以及使第二半导体材料层310凹进)以形成S/D沟槽605。在S/D沟槽605中的凹进的第一鳍部件245上形成S/D部件610。S/D部件610可以包括Ge、Si、GaAs、AlGaAs、SiGe、GaAsP、或其他合适的材料。如图6所示,在用S/D部件610填充S/D沟槽605之后,S/D部件610的顶层的进一步外延生长水平地扩展,并且可以开始形成小平面,诸如金刚石形小平面。可以在外延工艺期间原位掺杂S/D部件610。例如,在一个实施例中,S/D部件610包括掺杂有硼的外延生长的SiGe层。在另一实施例中,S/D部件610包括掺杂有碳的外延生长的Si外延层。在又另一实施例中,S/D部件610包括掺杂有磷的外延生长的Si外延层。在一个实施例中,未原位掺杂S/D部件610,实施注入工艺(即,结注入工艺)以掺杂S/D部件610。
图7示出了可以在衬底210上(包括伪栅极堆叠件510之间)形成层间介电(ILD)层710。ILD层710可以包括氧化硅、氮化硅、具有低于热氧化硅的介电常数(k)的介电材料(因此,称为低k介电材料层)或其他合适的介电材料层。ILD层710包括单层或多层。可以实施化学机械抛光(CMP)工艺以去除过量的ILD层710并且平坦化ILD层710和伪栅极堆叠件510的顶面。
图8示出了去除伪栅极堆叠件510以形成栅极沟槽810。在一个实施例中,在第一区260中,第一鳍部件245的上部和第二半导体材料层310暴露于栅极沟槽810中。而在第二区270中,第一鳍部件245的上部暴露于栅极沟槽810中。在本实施例中,通过基本不蚀刻第一鳍部件245和第二半导体材料层310的选择性蚀刻工艺来去除伪栅极堆叠件510。在一个实施例中,第一鳍部件245具有第二半导体材料层310和第三半导体材料层320,因此蚀刻工艺去除伪栅极堆叠件510和第三半导体材料层320以形成栅极沟槽810。
图9示出,在第一区260中,使第二半导体材料层310凹进以暴露第一鳍部件245的顶面,同时第二硬掩模825保护第二区270。因此剩余的第二半导体材料层310形成沿着第一鳍部件245的侧壁的第二间隔件820。在一个实施例中,使第二半导体材料层310各向异性地凹进,并且第二间隔件820具有第二宽度w2。第二硬掩模825在许多方面类似于以上结合图4A讨论的第一硬掩模280。
图10A示出,在第一区260中,使第一鳍部件245凹进,而第二间隔件820保持完整。第二区270由第二硬掩模825保护。在本实施例中,使第一鳍部件245凹进,从而使得第一鳍部件245的顶面与第二间隔件820的底面在同一水平处。凹进的第一鳍部件245嵌入在设置在半导体衬底上方的隔离结构250内,凹进的第一鳍部件245具有第一侧壁830和相对的第二侧壁832以及从第一侧壁830延伸至第二侧壁832的顶面834。
为了清楚的目的以更好地说明本发明的概念,第一区260中的凹进的第一鳍部件245称为嵌入式第一鳍部件245E,并且在嵌入式第一鳍部件245E的每侧的第二间隔件820称为第二鳍部件820A和第三鳍部件820B。
第二鳍部件820A和第三鳍部件820B设置在隔离结构250上方。第二鳍部件820A具有第三侧壁835和第四侧壁836。第三侧壁835与嵌入式第一鳍部件245E的第一侧壁830对准,而第四侧壁836直接设置在隔离部件250上方。第三鳍部件820B具有第五侧壁837和第六侧壁838。第五侧壁837与嵌入式第一鳍部件245E的第二侧壁832对准,而第六侧壁838直接设置在隔离部件250上方。如之前所述,第二鳍部件820A和第三鳍部件820B均具有高度h和第二宽度w2。在第二鳍部件820A和第三鳍部件820B之间形成间距840。间距840具有第一宽度w1。因此,第二鳍部件820A与第三鳍部件820B间隔开,从而使得第二鳍部件820A和第三鳍部件820B彼此不物理接触。
图10B示出了当第一鳍部件245具有第二半导体材料层310和第三半导体材料层320并且未通过以上参照图8讨论的蚀刻工艺去除它们时的可选实施例。在该实施例中,通过基本不蚀刻第一鳍部件245和第三半导体材料层320的选择性蚀刻工艺去除伪栅极堆叠件510。因此,当形成第二鳍部件820A和第三鳍部件820B时,第二鳍部件820A和第三鳍部件820B的每个均具有与第三半导体层320的第二部分平行的第二半导体层310的第一部分。
图11A示出在衬底210上方形成高k/金属栅极(HK/MG)920,其包裹在第一区中的第二鳍部件820A和第三鳍部件820B以及第二区中的第一鳍部件245上方。HK/MG 920包括栅极介电层922和位于栅极电介质上方的栅电极924。栅极介电层922直接设置在嵌入式第一鳍部件245E的顶面834上、第二鳍部件820A的第三侧壁835和第四侧壁836上、以及第三鳍部件820B的第五侧壁837和第六侧壁838上。栅电极924设置在栅极介电层922上方。
栅极介电层922可以包括界面层(IL)和设置在IL上的HK介电层。IL可以包括氧化物、HfSiO和氮氧化物。HK介电层可以包括LaO、AlO、ZrO、TiO、Ta2O5、Y2O3、SrTiO3(STO)、BaTiO3(BTO)、BaZrO、HfLaO、HfSiO、LaSiO、AlSiO、HfTaO、HfTiO、(Ba,Sr)TiO3(BST)、Al2O3、Si3N4、氮氧化硅(SiON)或其他合适的材料。
栅电极924可以包括单层或可选地包括多层结构,诸如具有功函数以增强器件性能的金属层(功函金属层)、衬垫层、润湿层、粘合层以及金属、金属合金或金属硅化物的导电层的各种组合。MG电极924可以包括Ti、Ag、Al、TiAlN、TaC、TaCN、TaSiN、Mn、Zr、TiN、TaN、Ru、Mo、Al、WN、Cu、W、任何合适的材料或它们的组合。可以实施CMP工艺以去除过量的MG电极924。
在第一区260中,HK/MG 920称为HK/MG 920A。MG电极924填充第二鳍部件820A和第三鳍部件820B之间的间距并且连接第二鳍部件820A和第三鳍部件820B。在第二区中,HK/MG920包裹在第一鳍部件245上方,称为HK/MG 920B。为了满足半导体器件200的性能需求,在一个实施例中,一个HK/MG 920A接近另一HK/MG 920A,并且在另一实施例中,一个HK/MG920A接近一个HK/MG 920B。
图11B示出了第二鳍部件820A和第三鳍部件820B包括第二半导体材料层310和第三半导体材料层320的实施例。在这种情况下,高k/金属栅极(HK/MG)920形成在衬底210上方,包裹在第一区中的第二鳍部件820A和第三鳍部件820B上方以及第二区中的第一鳍部件245上方。第一区260中的HK/MG 920称为HK/MG 920C。
为了满足半导体器件200的性能需求,HK/MG 920可以具有HK/MG920A、920B和920C之间的各种组合。在一个实施例中,一个HK/MG 920A接近另一HK/MG 920A。在另一实施例中,一个HK/MG 920A接近一个HK/MG 920B。在又另一实施例中,一个HK/MG 920C接近另一HK/MG920C。在又另一实施例中,一个HK/MG 920C接近另一HK/MG 920B。
本发明也提供了用于制造半导体器件的各种方法。图12是用于制造本实施例中的图11A和图11B中的半导体器件200的方法1000的流程图。参照图12和图1,方法1000开始于步骤1002,提供具有芯轴部件220和沿着芯轴部件220的侧壁的第一间隔件230的衬底210。
参照图12和图2,方法1000进行至步骤1004,去除芯轴部件220以形成沟槽240。通过选择性地去除芯轴部件220但基本不蚀刻第一间隔件230的蚀刻工艺来去除芯轴部件220。选择性蚀刻可以包括选择性湿蚀刻、选择性干蚀刻和/或它们的组合。第一间隔件230称为第一鳍部件245。
参照图12和图3,方法1000进行至步骤1006,用隔离部件250填充沟槽240并且使隔离部件250凹进以暴露第一鳍部件245的上部。通过诸如CVD的合适的技术形成隔离部件250,并且通过包括选择性湿蚀刻、选择性干蚀刻和/或它们的组合的选择性蚀刻回蚀刻隔离部件250。
参照图12和图4A至图4B,方法1000进行至步骤1008,外延生长第二半导体材料层310以包裹在第一区260中的第一鳍部件245的上部上方。在一个实施例中,形成第一硬掩模280以覆盖第二区270。可以通过沉积、图案化和蚀刻工艺形成第一硬掩模280。外延工艺可以包括CVD(VPE和/或UHV-CVD)、分子束外延和/或其他合适的工艺。在一个实施例中,通过另一外延生长工艺在第二半导体材料层310上方沉积第三半导体材料层320。然后,通过合适的蚀刻工艺去除第一硬掩模280。
参照图12和图5,方法1000进行至步骤1010,在栅极区420中的第一鳍部件245的部分上方形成伪栅极堆叠件510和栅极间隔件540。通过任何合适的一个或多个工艺形成伪栅极堆叠件510。例如,可以通过包括沉积、光刻图案化和蚀刻工艺的工序形成伪栅极堆叠件510。沉积工艺包括CVD、物理汽相沉积(PVD)、ALD、其他合适的方法和/或它们的组合。蚀刻工艺包括干蚀刻、湿蚀刻和/或其他蚀刻方法。
参照图12和图6,方法1000进行至步骤1012,使S/D区410中的第一鳍部件245以及第二半导体材料层310选择性地凹进以形成S/D沟槽605。凹进工艺可以包括干蚀刻工艺、湿蚀刻工艺和/或它们的组合。凹进工艺也可以包括选择性湿蚀刻或选择性干蚀刻。湿蚀刻溶液包括四甲基氢氧化铵(TMAH)、HF/HNO3/CH3COOH溶液或其他合适的溶液。干和湿蚀刻工艺具有可以调节的蚀刻参数,诸如所使用的蚀刻剂、蚀刻温度、蚀刻溶液浓度、蚀刻压力、源功率、RF偏置电压、RF偏置功率、蚀刻剂流速和其他合适的参数。例如,湿蚀刻溶液可以包括NH4OH、KOH(氢氧化钾)、HF(氢氟酸)、TMAH(四甲基氢氧化铵)、其他合适的湿蚀刻溶液或它们的组合。干蚀刻工艺包括使用氯基化学物质的偏置等离子体蚀刻工艺。其他干蚀刻剂气体包括CF4、NF3、SF6和He。也可以使用诸如DRIE(深反应离子蚀刻)的机制各向异性地实施干蚀刻。
再次参照图12和图6,方法1000进行至步骤1014,在S/D沟槽605中形成S/D部件610。可以通过诸如CVD(VPE和/或UHV-CVD)、分子束外延和/或其他合适的工艺的外延生长工艺形成S/D部件610。在一个实施例中,可以在外延工艺期间实施原位掺杂工艺。在另一实施例中,实施注入工艺(即,结注入工艺)以掺杂S/D部件610。可以实施一个或多个退火工艺以活化掺杂剂。退火工艺包括快速热退火(RTA)和/或激光退火工艺。
参照图12和图7,方法1000进行至步骤1016,在衬底210上方形成ILD层710。可以通过CVD、PVD、ALD、旋涂和/或其他合适的工艺沉积ILD层710。可以实施CMP工艺以去除过量的ILD层710并且平坦化ILD层710和伪栅极堆叠件510的顶面。
参照图12和图8,方法1000进行至步骤1018,去除伪栅极堆叠件510以形成栅极沟槽810。在一个实施例中,通过选择性湿蚀刻或选择性干蚀刻去除伪栅极堆叠件510。在另一实施例中,通过光刻图案化和蚀刻工艺去除伪栅极堆叠件510。
参照图12和图9,方法1000进行至步骤1020,使第二半导体材料层310凹进以形成第二间隔件820。在本实施例中,通过各向异性和选择性干蚀刻使第二半导体材料层310凹进,该选择性干蚀刻选择性地去除第二半导体材料层310的部分以暴露第一鳍部件245的顶面但是不横向蚀刻沿着第一鳍部件245的侧壁的第二半导体材料层310以及第一鳍部件245。
参照图12和图10A至图10B,方法1000进行至步骤1022,使第一鳍部件245的上部选择性地凹进以形成间距840以及第二鳍部件820A和第三鳍部件820B。在一个实施例中,通过基本不蚀刻第二鳍部件820A和第三鳍部件820B的选择性干蚀刻工艺使第一鳍部件245的上部凹进。
参照图12和图11A至图11B,方法1000进行至步骤1024,在衬底210上方形成HK/MG920,其包裹在第一区260中的第二鳍部件820A和第三鳍部件820B以及第二区270中的第一鳍部件245上方。通过诸如ALD、CVD、热氧化或臭氧氧化、其他合适的技术或它们的组合的合适的方法在栅极沟槽810上方沉积栅极介电层922。可以通过ALD、PVD、CVD或其他合适的工艺形成MG电极924。可以实施另一CMP工艺以去除过量的栅极介电层922和MG电极924。
在方法1000之前、期间和之后可以提供额外的步骤,并且对于方法1000的额外的实施例,可以替代、消除或移动一些描述的步骤。
半导体器件200可以包括可以通过随后的处理形成的额外的部件。例如,在衬底210上方形成各种接触件/通孔/线和多层互连部件(例如,金属层和层间电介质)。例如,多层互连包括诸如传统的通孔或接触件的垂直互连件以及诸如金属线的水平互连件。各种互连部件可以采用包括铜、钨和/或硅化物的各种导电材料。在一个实例中,镶嵌和/或双镶嵌工艺用于形成铜相关的多层互连结构。
基于以上所述,可以看出,本发明提供了位于半导体器件的相应区域中的具有不同宽度和半导体材料的第一、第二和第三鳍结构以及它们的制造方法。第一鳍部件具有较大的宽度并且与衬底接触,而第二鳍部件具有较小的宽度并且通过介电层与衬底隔离。具有第一、第二和第三鳍部件的半导体器件展示出高性能和低电流泄漏,尤其是对于诸如静态随机存取存储器(SRAM)器件和短沟道(SC)逻辑器件的小尺寸器件。该方法提供了稳健的小尺寸鳍部件形成工艺。
本发明提供了半导体器件的许多不同的实施例。半导体器件包括:第一鳍部件,嵌入在设置在半导体衬底上方的隔离结构内,第一鳍部件具有第一侧壁和相对的第二侧壁以及从第一侧壁延伸至第二侧壁的顶面。该器件也包括:第二鳍部件,设置在隔离结构上方并且具有第三侧壁和第四侧壁。第三侧壁与第一鳍部件的第一侧壁对准。该器件也包括:栅极介电层,直接设置在第一鳍部件的顶面上以及第二鳍部件的第三侧壁和第四侧壁上;以及栅电极,设置在栅极介电层上方。
在另一实施例中,一种半导体器件包括:第一半导体鳍部件,位于衬底上方;凹进的第一半导体鳍部件,嵌入在设置在衬底上方的隔离结构内。该器件也包括:第二半导体鳍部件,设置在隔离结构上方并且具有第三侧壁和第四侧壁。第三侧壁与第一半导体鳍部件的第一侧壁对准,并且第四侧壁直接设置在隔离结构上方。该器件也包括:第三半导体鳍部件,设置在隔离结构上方并且具有第五侧壁和第六侧壁。第五侧壁与第一半导体鳍部件的第二侧壁对准,并且第六侧壁直接设置在隔离结构上方。该器件也包括:栅极堆叠件,设置在衬底上方,栅极堆叠件包裹在第一半导体鳍部件上方。该器件也包括:另一栅极堆叠件,设置在衬底上方,另一栅极堆叠件包裹在第二半导体鳍部件和第三半导体鳍部件上方。
在又另一实施例中,一种用于制造半导体器件的方法包括:在衬底上方形成第一鳍部件,在第一鳍部件之间形成隔离区,第一鳍部件的上部位于隔离区之上,在第一鳍部件的上部上方外延生长半导体材料层,在具有半导体材料层的第一鳍部件的部分上方形成伪栅极堆叠件,使伪栅极堆叠件旁边的第一鳍部件凹进以形成源极/漏极(S/D)凹槽,在S/D凹槽上方形成S/D部件,去除伪栅极堆叠件以暴露具有半导体材料层的第一鳍部件,使半导体材料层凹进以暴露第一鳍部件的顶面并且留下沿着第一鳍部件的侧壁的半导体材料层,以及选择性地去除第一鳍部件的上部,同时半导体材料层保持完整以形成第二鳍部件和第三鳍部件。
上面概述了若干实施例的特征,使得本领域技术人员可以更好地理解本发明的方面。本领域技术人员应该理解,他们可以容易地使用本发明作为基础来设计或修改用于实施与本文所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到,这种等同构造并不背离本发明的精神和范围,并且在不背离本发明的精神和范围的情况下,本文中他们可以做出多种变化、替换以及改变。
Claims (15)
1.一种半导体器件,包括:
第一鳍部件,嵌入在设置在半导体衬底上方的隔离结构内,所述第一鳍部件具有第一侧壁和相对的第二侧壁以及从所述第一侧壁延伸至所述第二侧壁的顶面;
第二鳍部件,设置在所述隔离结构上方并且具有第三侧壁和第四侧壁,其中,所述第三侧壁与所述第一鳍部件的所述第一侧壁对准,所述第四侧壁直接设置在所述隔离结构上方,其中,所述第一鳍部件的宽度大于所述第二鳍部件的宽度;
第三鳍部件,设置在所述隔离结构上方并且具有第五侧壁和第六侧壁,其中,所述第五侧壁与所述第一鳍部件的所述第二侧壁对准,所述第六侧壁直接设置在所述隔离结构上方,其中,所述第一鳍部件的宽度大于所述第三鳍部件的宽度;
栅极介电层,直接设置在所述第一鳍部件的所述顶面上以及所述第二鳍部件的所述第三侧壁和所述第四侧壁上;以及
栅电极,设置在所述栅极介电层上方,
其中,所述第二鳍部件包括平行于第二部分的第一部分,其中,所述第一部分的半导体材料与所述第二部分中的半导体材料不同。
2.根据权利要求1所述的半导体器件,其中,所述第一鳍部件由第一半导体材料形成,并且所述第二鳍部件和所述第三鳍部件的半导体材料均不同于所述第一半导体材料。
3.根据权利要求2所述的半导体器件,其中,所述第二鳍部件和所述第三鳍部件的半导体材料包括单晶外延半导体材料。
4.根据权利要求1所述的半导体器件,其中,所述第二鳍部件与所述第三鳍部件间隔开,从而使得所述第二鳍部件与所述第三鳍部件彼此不物理接触。
5.根据权利要求1所述的半导体器件,其中,所述栅极介电层直接设置在所述第三鳍部件的所述第五侧壁上。
6.根据权利要求1所述的半导体器件,其中,所述第二鳍部件具有与所述第三鳍部件相同的宽度,所述宽度小于所述第一鳍部件的宽度。
7.一种半导体器件,包括:
第一半导体鳍部件,位于衬底上方;
凹进的第一半导体鳍部件,嵌入在设置在所述衬底上方的隔离结构内,所述凹进的第一半导体鳍部件具有第一侧壁和第二侧壁;
第二半导体鳍部件,设置在所述隔离结构上方并且具有第三侧壁和第四侧壁,其中,所述第三侧壁与所述第一侧壁对准,所述第四侧壁直接设置在所述隔离结构上方;
第三半导体鳍部件,设置在所述隔离结构上方并且具有第五侧壁和第六侧壁,其中,所述第五侧壁与所述第二侧壁对准,所述第六侧壁直接设置在所述隔离结构上方,其中,所述凹进的第一半导体鳍部件的宽度大于所述第二半导体鳍部件的宽度和所述第三半导体鳍部件的宽度;
栅极堆叠件,设置在所述衬底上方,所述栅极堆叠件包裹在所述第一半导体鳍部件上方;以及
另一栅极堆叠件,设置在所述衬底上方,所述另一栅极堆叠件包裹在所述第二半导体鳍部件和所述第三半导体鳍部件上方,
其中,所述第二半导体鳍部件包括平行于第二部分的第一部分,其中,所述第一部分的半导体材料与所述第二部分中的半导体材料不同。
8.根据权利要求7所述的半导体器件,其中,所述第一半导体鳍部件由第一半导体材料形成,并且所述第二半导体鳍部件和所述第三半导体鳍部件的半导体材料均不同于所述第一半导体材料。
9.根据权利要求7所述的半导体器件,其中,所述第二半导体鳍部件与所述第三半导体鳍部件间隔开,从而使得所述第二半导体鳍部件与所述第三半导体鳍部件彼此不物理接触。
10.根据权利要求7所述的半导体器件,其中,所述另一栅极堆叠件的栅极介电层直接设置在所述凹进的第一半导体鳍部件的顶面上、所述第二半导体鳍部件的所述第三侧壁和所述第四侧壁上、以及所述第三半导体鳍部件的所述第五侧壁和所述第六侧壁上。
11.根据权利要求7所述的半导体器件,其中,所述第二半导体鳍部件具有与所述第三半导体鳍部件相同的宽度,所述宽度小于所述第一半导体鳍部件的宽度。
12.根据权利要求7所述的半导体器件,还包括:
源极/漏极部件,位于所述衬底上方,并且位于所述栅极堆叠件旁边。
13.一种用于制造半导体器件的方法,所述方法包括:
在衬底上方形成第一鳍部件;
在所述第一鳍部件之间形成隔离区,其中,所述第一鳍部件的上部位于所述隔离区之上;
在所述第一鳍部件的上部上方外延生长第一半导体材料层和不同于所述第一半导体层的第二半导体材料层;
在具有所述第一半导体材料层和所述第二半导体材料层的所述第一鳍部件的部分上方形成伪栅极堆叠件;
使所述伪栅极堆叠件旁边的所述第一鳍部件凹进以形成源极/漏极(S/D)凹槽;
在所述源极/漏极凹槽上方形成源极/漏极部件;
去除所述伪栅极堆叠件以暴露具有所述第一半导体材料层和所述第二半导体材料层的所述第一鳍部件;
使所述第一半导体材料层和所述第二半导体材料层凹进以暴露所述第一鳍部件的顶面并且留下沿着所述第一鳍部件的侧壁的所述第一半导体材料层和所述第二半导体材料层;以及
选择性地去除所述第一鳍部件的上部,同时使得所述第一半导体材料层和所述第二半导体材料层保持完整以形成第二鳍部件和第三鳍部件,其中,所述第一鳍部件的宽度大于所述第二鳍部件的宽度和所述第三鳍部件的宽度。
14.根据权利要求13所述的用于制造半导体器件的方法,还包括:
在所述衬底上方形成高k/金属栅极(HK/MG)堆叠件,所述高K/金属栅极堆叠件包裹在所述第二鳍部件和所述第三鳍部件上方。
15.根据权利要求13所述的用于制造半导体器件的方法,其中,在所述衬底上方形成所述第一鳍部件包括:
在所述衬底上方形成芯轴部件;
在所述芯轴部件上方沉积材料层;
各向异性地蚀刻所述材料层以形成沿着所述芯轴部件的侧壁的间隔件;以及
选择性地去除所述芯轴部件,同时使得所述间隔件保持完整以形成所述第一鳍部件。
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CN109950311B (zh) * | 2017-12-20 | 2022-02-15 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构及其形成方法 |
US20220052159A1 (en) * | 2020-08-14 | 2022-02-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Forming Source And Drain Features In Semiconductor Devices |
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US6762448B1 (en) * | 2003-04-03 | 2004-07-13 | Advanced Micro Devices, Inc. | FinFET device with multiple fin structures |
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US20070090416A1 (en) * | 2005-09-28 | 2007-04-26 | Doyle Brian S | CMOS devices with a single work function gate electrode and method of fabrication |
US8264032B2 (en) | 2009-09-01 | 2012-09-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Accumulation type FinFET, circuits and fabrication method thereof |
US9484462B2 (en) | 2009-09-24 | 2016-11-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fin structure of fin field effect transistor |
US8362568B2 (en) * | 2009-08-28 | 2013-01-29 | International Business Machines Corporation | Recessed contact for multi-gate FET optimizing series resistance |
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US8723272B2 (en) | 2011-10-04 | 2014-05-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET device and method of manufacturing same |
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US8664060B2 (en) * | 2012-02-07 | 2014-03-04 | United Microelectronics Corp. | Semiconductor structure and method of fabricating the same |
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US8987835B2 (en) * | 2012-03-27 | 2015-03-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET with a buried semiconductor material between two fins |
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