CN109037046B - Metal gate, semiconductor device and manufacturing method thereof - Google Patents

Metal gate, semiconductor device and manufacturing method thereof Download PDF

Info

Publication number
CN109037046B
CN109037046B CN201710429096.7A CN201710429096A CN109037046B CN 109037046 B CN109037046 B CN 109037046B CN 201710429096 A CN201710429096 A CN 201710429096A CN 109037046 B CN109037046 B CN 109037046B
Authority
CN
China
Prior art keywords
layer
metal
barrier layer
work function
function setting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201710429096.7A
Other languages
Chinese (zh)
Other versions
CN109037046A (en
Inventor
江涛
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Tianjin Corp
Original Assignee
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Tianjin Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Manufacturing International Shanghai Corp, Semiconductor Manufacturing International Tianjin Corp filed Critical Semiconductor Manufacturing International Shanghai Corp
Priority to CN201710429096.7A priority Critical patent/CN109037046B/en
Publication of CN109037046A publication Critical patent/CN109037046A/en
Application granted granted Critical
Publication of CN109037046B publication Critical patent/CN109037046B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/495—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

The invention provides a metal grid, a semiconductor device and a manufacturing method thereof.A oxygen-rich layer is arranged on the upper surface layer of at least one of a metal barrier layer and a work function setting metal layer, and oxygen in the oxygen-rich layer reacts with electrode metal in a metal electrode layer to form an oxide layer so as to prevent the electrode metal in the metal electrode layer from diffusing towards the direction of a semiconductor substrate, so that the reliability of the device is improved, the failure rate of the device is reduced, and the yield of integrated circuit products is improved; furthermore, a relatively thick covering barrier layer is deposited by using an Extensa deposition system, so that the good control of the deposition process of the covering barrier layer is realized, the subsequent metal electrode layer has good gap filling capacity, and the electrode metal in the metal electrode layer is further prevented from diffusing towards the direction of the semiconductor substrate.

Description

Metal gate, semiconductor device and manufacturing method thereof
Technical Field
The invention relates to the technical field of integrated circuit manufacturing, in particular to a metal gate, a semiconductor device and a manufacturing method thereof.
Background
With the continuous development of integrated circuit manufacturing technology, the feature size of MOS transistors is getting smaller, and a gate stack structure of a high-K gate dielectric layer and a metal gate (abbreviated as a high-K metal gate, abbreviated as HKMG) is introduced into the MOS transistor, for example, into a pull-down transistor (PD NFET) of a static memory (SRAM) with a 28nm node, so as to reduce the parasitic capacitance of the gate of the MOS transistor and improve the device speed. However, it is found in practical production that the HKMG SRAM product often suffers from failures in MBIST (memory built-in self test), and the hit rate of the failures per batch is close to 100%, obviously seriously affecting the yield of the integrated circuit product.
Disclosure of Invention
The invention aims to provide a metal gate, a semiconductor device and a manufacturing method thereof, which can reduce the failure rate of the device and improve the yield of integrated circuit products.
In order to achieve the above object, the present invention provides a method for manufacturing a metal gate, including the steps of:
forming a metal barrier layer on a semiconductor substrate;
forming a work function setting metal layer on the metal barrier layer;
forming a metal electrode layer for manufacturing the metal gate on the work function setting metal layer;
and the upper surface layer of at least one of the metal barrier layer and the work function setting metal layer is an oxygen-enriched layer.
Optionally, before forming the work function setting metal layer on the metal barrier layer, introducing oxygen into the metal barrier layer to change an upper surface layer of the metal barrier layer into an oxygen-rich layer; after forming a work function setting metal layer on the metal barrier layer, an upper surface of the work function setting metal layer becomes an oxygen-rich layer by introducing oxygen into the work function setting metal layer.
Optionally, the metal barrier layer is a single layer or a stacked layer, and when the metal barrier layer is a stacked layer, oxygen is introduced into the metal barrier layer by introducing oxygen into at least a top barrier layer of the metal barrier layer, which is adjacent to the work function setting metal layer, so that the top barrier layer serves as an oxygen-rich layer of the metal barrier layer.
Optionally, the upper surface layer of at least one of the metal barrier layer and the work function setting metal layer is an oxygen-rich layer by air break, oxygen plasma surface treatment, or oxygen ion implantation.
Optionally, when the metal barrier layer is a stack, an atomic layer deposition process is used to form a top barrier layer in the metal barrier layer, which is next to the work function setting metal layer.
Optionally, before forming a metal electrode layer for manufacturing the metal gate on the work function setting metal layer, a covering barrier layer is further formed on the work function setting metal layer.
Optionally, the thickness of the capping barrier layer is greater than the thickness of the work function setting metal layer.
Optionally, the blanket barrier layer is formed using an extensnsa deposition system.
Optionally, the method for manufacturing the metal gate further includes: forming a high-K gate dielectric layer on the semiconductor substrate before forming the metal barrier layer on the semiconductor substrate; and forming a wetting metal layer between the covering barrier layer and the metal electrode layer.
The invention also provides a metal gate, which comprises a metal barrier layer, a work function setting metal layer and a metal electrode layer which are sequentially arranged on a semiconductor substrate, wherein the upper surface layer of at least one of the metal barrier layer and the work function setting metal layer is an oxygen-rich layer, an oxide layer is formed at the interface of the top of the oxygen-rich layer, and the oxide layer is formed by the diffusion of metal in the metal electrode layer to the oxygen-rich layer and the reaction of the oxide layer and the oxygen-rich layer.
Optionally, the metal gate further includes a capping barrier layer between the work function setting metal layer and the metal electrode layer.
Optionally, the material of the capping barrier layer includes at least one of a metal nitride, a metal carbonitride, and a metal silicon nitride.
Optionally, the thickness of the capping barrier layer is greater than the thickness of the work function setting metal layer.
The invention also provides a manufacturing method of the semiconductor device, which comprises the following steps:
providing a semiconductor substrate;
by adopting the manufacturing method of the metal gate, the metal gate structure comprising the metal barrier layer, the work function setting layer and the metal electrode layer is formed on the surface of the semiconductor substrate.
Optionally, the semiconductor substrate includes a semiconductor base and an interlayer dielectric layer located on the surface of the semiconductor base, the interlayer dielectric layer has a gate opening therein, and the metal gate structure is filled in the gate opening.
The invention also provides a semiconductor device which comprises a semiconductor substrate and the metal gate positioned on the semiconductor substrate.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
1. in the metal barrier layer and the work function setting metal layer, the upper surface layer of at least one of the metal barrier layer and the work function setting metal layer is an oxygen-rich layer, and oxygen in the oxygen-rich layer reacts with electrode metal in the metal electrode layer to form an oxide layer so as to prevent the electrode metal in the metal electrode layer from diffusing towards the direction of the semiconductor substrate, so that the reliability of the device is improved, the failure rate of the device is reduced, and the yield of integrated circuit products is improved;
2. by increasing the thickness of the covering barrier layer on the work function setting metal layer, on one hand, a subsequent metal electrode layer has good gap filling capacity, and on the other hand, electrode metal in the metal electrode layer can be further prevented from diffusing towards the direction of the semiconductor substrate;
3. the blanket barrier layer is deposited using an Extensa deposition system to achieve good process control of blanket barrier layer deposition.
Drawings
FIG. 1A is a cross-sectional block diagram of a PD NFET of an SRAM;
FIG. 1B is a partial cross-sectional electron micrograph of a PD NFET of an SRAM;
FIG. 1C is a graph of threshold voltage test curves for PD NFET elements at various locations on a SRAM device wafer;
FIG. 2 is a flow chart of a method of fabricating a metal gate in accordance with an embodiment of the present invention;
FIG. 3 is a cross-sectional view of a device structure in a method of fabricating a metal gate in accordance with an embodiment of the present invention;
FIG. 4 is a flow chart of a method of fabricating a semiconductor device in accordance with an embodiment of the present invention;
fig. 5A to 5E are schematic cross-sectional views of device structures in a method of manufacturing a semiconductor device according to an embodiment of the present invention;
FIG. 6 is a test plot of threshold voltages of PD NFET cells at various locations on a wafer of an SRAM device in accordance with an embodiment of the present invention.
Detailed Description
Referring to fig. 1A, a process for forming a pull-down transistor (PD NFET) metal Gate of a 28nm static memory (SRAM) by a Gate-last process includes:
firstly, providing a semiconductor substrate (for example, bulk silicon) 100, forming a replacement gate structure (not shown) on the semiconductor substrate 100, and an interlayer dielectric layer 101 located on the semiconductor substrate 100 and covering the replacement gate structure;
then, taking the replacement gate structure as a stop layer, and performing Chemical Mechanical Polishing (CMP) on the interlayer dielectric layer 101 until the surface of the replacement gate structure is exposed;
then, removing the replacement gate structure, and forming a gate opening in the interlayer dielectric layer 101;
next, hafnium oxide (HfO) is sequentially deposited on the semiconductor substrate 100 and the surface of the gate opening2) Layer 102, titanium nitride (TiN) layer 103, tantalum nitride (TaN) layer 104, titanium aluminum (TiAl) layer 105, TiN layer 106, Ti layer 107, and Al layer 108; wherein, HfO2Layer 102 serves as a high-K gate dielectric layer, e.g., having a thickness of
Figure BDA0001316951070000041
The TiN Layer 103 is typically formed by a low pressure chemical vapor deposition process as an underlying metal barrier Layer (Cap Layer1) having a thickness of, for example, about
Figure BDA0001316951070000042
TaN Layer 104 as a top metal barrier Layer (Cap Layer2) can be formed by an atomic Layer deposition process to a thickness such as
Figure BDA0001316951070000043
The TiAl layer 105 is formed as an N-type work function setting metal layer (NWF layer) generally by a physical vapor deposition process, for example, to a thickness of
Figure BDA0001316951070000044
The TiN layer 106 is formed as a Barrier layer (Barrier layer) by a physical vapor deposition process, for example, to a thickness of
Figure BDA0001316951070000045
The Ti layer 107 is a Wetting layer (Wetting layer) having a thickness of, for example
Figure BDA0001316951070000046
Ti)107 and Al layer 108 as metal Electrode layers (electrodes) and have a thickness of, for example
Figure BDA0001316951070000047
Finally, the deposited Al layer 108 and the like are planarized again by Chemical Mechanical Polishing (CMP) until the surface of the interlayer dielectric layer 101 to form a high-K metal gate.
However, it has been found in practice that the static memory product formed by the above technical solution often suffers from failures in MBIST (memory built-in self test), and the hit rate of the failures by batch is close to 100%. After performing pfa (physical Failure analysis) Failure analysis in terms of physical and material, it was found that Ti layer 107 and TiN layer 106 in the high-K metal gate are missing at the corner of the active region (AA corner) of the PD NFET (mainly due to the very thin Ti layer 107, TiN layer 106, TiN layer 103, and TaN layer 104 relative to Al layer 108 and the low gap-filling capability), as shown by the area enclosed by the dashed circle in fig. 1B, through which aluminum in Al layer 108 diffuses into the active region, resulting in device Failure; in addition, the different degrees of aluminum diffusion of the PD NFETs at the center and edge of the static memory (SRAM) wafer also resulted in a large deviation of the threshold voltage (Vtstat) of the PD NFETs at the center and edge of the SRAM wafer, about 45mv, as shown in FIG. 1C.
The present invention will be described in more detail with reference to the accompanying drawings, which are included to illustrate embodiments of the present invention.
Referring to fig. 2, the present invention provides a method for manufacturing a metal gate, including the following steps:
s1: forming a metal barrier layer on a semiconductor substrate;
s2: forming a work function setting metal layer on the metal barrier layer;
s3: forming a covering barrier layer and a wetting metal layer on the work function setting metal layer;
s4: forming a metal electrode layer for manufacturing the metal gate on the infiltrated metal layer; and
e1: making the upper surface layer of the metal barrier layer an oxygen-rich layer, and/or, E2: and enabling the upper surface layer of the work function setting metal layer to be an oxygen-enriched layer.
Referring to fig. 3, in step S1, the semiconductor substrate 300 used may be any substrate known to those skilled in the art for carrying components of a semiconductor integrated circuit, such as a silicon-on-insulator (SOI), bulk silicon (bulk silicon), germanium (ge) substrate, silicon germanium (ge) substrate, gallium arsenide (gaas) substrate, or ge-on-insulator (ge) substrate. The semiconductor substrate 300 may have wells (wells), fins (fins), Shallow Trench Isolation (STI), and the like formed therein.
In step S1, first, an interface layer 301 may be formed on the surface of the semiconductor substrate 300 by a thermal growth process such as oxidation (RTO) or oxynitridation to a thickness of, for example, the interface layer 301
Figure BDA0001316951070000051
To enhance adhesion between the semiconductor substrate 300 and the subsequent high-K gate dielectric layer 302. Thereafter, a high-K gate dielectric layer 302 may be deposited on the interfacial layer 301 by a deposition process such as ordinary Chemical Vapor Deposition (CVD), plasma enhanced deposition (PE CVD), Metal Organic Chemical Vapor Deposition (MOCVD), Atomic Layer Deposition (ALD), etc., the high-K gate dielectric layer 302 having a dielectric constant K greater than about 4.0, preferably greater than 7.0.
In particular, the high-K gate dielectric layer 302 used in the present invention includes, but is not limited to, hafnium oxide (HfO)2) Hafnium oxynitride (HfON), hafnium silicate (HfSiO), hafnium silicon oxynitride (HfSiON), zirconium oxide (ZrO)2) Zirconium oxynitride (ZrON), siliconZirconium acid (ZrSiO), zirconium silicon oxynitride (ZrSiON), hafnium zirconium oxide (HfZrO)2) Hafnium zirconium oxynitride (HfZrON), hafnium zirconium silicate (HfZrSiO), hafnium zirconium silicon oxynitride (HfZrSiON), aluminum oxide (Al)2O3) Titanium oxide (TiO)2) Lanthanum oxide (La)2O3) Lanthanum aluminum oxide (LaAlO)3) Cerium oxide (CeO)2) Yttrium oxide (Y)2O3) Barium strontium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), strontium titanium oxide (SrTiO)3) Lead scandium tantalum oxide (PbScTaO), or a combination of two or more thereof. The physical thickness of the high-K gate dielectric layer 302 may be determined by the performance requirements of the device, for example, when used in a 28nm NMOS transistor, the thickness of the high-K gate dielectric layer 302 may be set to be
Figure BDA0001316951070000052
Next, a metal barrier layer 303 may be deposited on the surface of the high-K gate dielectric layer 302 by a deposition process such as general Chemical Vapor Deposition (CVD), Low Pressure Chemical Vapor Deposition (LPCVD), Metal Organic Chemical Vapor Deposition (MOCVD), Atomic Layer Deposition (ALD), etc., and the material of the metal barrier layer 303 may include at least one of metal nitride, metal carbonitride, and metal silicon nitride, wherein the metal element includes at least one of titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), and tantalum (Ta). The metal barrier layer 303 may improve adhesion between the subsequent work function setting metal layer 304 and the high-K gate dielectric layer 302, prevent the work function setting metal layer 304 from diffusing into the high-K gate dielectric layer 302, and may also have a thickness that allows the work function of the metal in the work function setting metal layer 304 to perform device turn-on.
The metal barrier layer 303 may be a single layer or a stacked layer, for example, in this embodiment, the metal barrier layer 303 is a stacked layer including two layers:
Figure BDA0001316951070000061
as the underlying barrier layer 303a,
Figure BDA0001316951070000062
as a top barrier layer 303b, wherein the bottom barrier layer 303a may be formed by a low pressure cvd (lpcvd) process to reduce adverse effects on the high-K gate dielectric layer 302; the top barrier layer 303b may be formed by an ALD process to ensure uniformity and consistency of the deposited surface and provide a good process window for the deposition of the subsequent workfunction setting metal layer 304.
After depositing the metallic barrier layer 303, step E1 may be optionally performed: and processing the upper surface layer of the metal barrier layer 303 to make the upper surface layer of the metal barrier layer 303 be an oxygen-rich layer. In this embodiment, the deposition formation of the interfacial layer 301, the high-K gate dielectric layer 302 and the metal barrier layer 303 is performed in a manner that does not interrupt the vacuum between depositions, and after the deposition of the metal barrier layer 303, the device is Air-disconnected (Air Break). Specifically, the semiconductor substrate 300 having the metal barrier layer 303 deposited thereon is taken out from the deposition chamber and the metal barrier layer 303 is exposed to air for a certain period of time (for example, a period of time longer than 1 minute) to introduce oxygen into the upper surface of the metal barrier layer 303, thereby forming an oxygen-rich layer 303c, the oxygen of the oxygen-rich layer 303c is capable of reacting with the metal such as aluminum in the subsequently formed metal electrode layer 307 to form an oxide, and an oxide layer is formed at the interface between the metal barrier layer 303 and the above work function setting metal layer 304, that is, at the interface on the top of the oxygen-rich layer 303c, thereby making it possible to block diffusion of the metal such as aluminum in the subsequently formed metal electrode layer 307 toward the semiconductor substrate 300. In other embodiments of the present invention, oxygen may be introduced into the upper surface layer of the metal barrier layer 303 by using a process such as oxygen plasma surface treatment or oxygen ion implantation, so as to precisely control the concentration and depth of the introduced oxygen, but the manufacturing cost may be increased. Optionally, when the metal barrier layer 303 is a stack, the oxygen-rich layer 303c is formed by introducing oxygen into or on at least a top barrier layer (e.g., 303b in fig. 3) of the metal barrier layer 303 next to the workfunction setting metal layer 304 to introduce oxygen into the metal barrier layer 303. It should be noted that, in the present invention, only the upper surface layer of the metal barrier layer 303 is converted into an oxygen-rich layer, instead of converting the metal barrier layer 303 into an oxygen-rich layer as a whole, so as to improve the blocking capability of the metal barrier layer 303 on the electrode metal diffused downward from the metal electrode layer on the basis of ensuring that the original property of the metal barrier layer 303 is not affected.
In step S2, the workfunction setting metal layer 304 may be deposited on the surface of the metal barrier layer 303 by a deposition process such as ordinary Chemical Vapor Deposition (CVD), plasma enhanced deposition (PECVD), Metal Organic Chemical Vapor Deposition (MOCVD), Atomic Layer Deposition (ALD), or the like. The work function of the work function setting metal layer 304 for the NMOS device is less than 4.2eV, and the metal element may include at least one of scandium (Sc), yttrium (Y), lanthanum (La), titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), and tantalum (Ta), and may further include aluminum (Al). The work function setting metal layer 304 may include at least one of metal carbide, metal nitride, pure metal, and alloy, such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, aluminum carbide, titanium-aluminum alloy. In this embodiment, the work function setting metal layer 304 is
Figure BDA0001316951070000071
TiAl of (2).
After depositing the workfunction setting metal layer 304, step E2 may optionally be performed: the upper surface of the work function setting metal layer 304 is processed to make the upper surface of the work function setting metal layer 304 an oxygen-rich layer. In this embodiment, the deposition formation process of the work function setting metal layer 304 is performed in a specific atmosphere such as argon, and after the deposition of the work function setting metal layer 304, the device is subjected to Air Break (Air Break). Specifically, the semiconductor substrate 300 having the work function setting metal layer 304 deposited thereon is taken out from the deposition chamber and the work function setting metal layer 304 is exposed to air for a certain period of time (for example, a period of time longer than 1 minute) to introduce oxygen into the upper surface of the work function setting metal layer 304, so that an oxygen-rich layer 304a is formed, the oxygen of the oxygen-rich layer 304a can react with the metal such as aluminum which is subsequently diffused from the formed metal electrode layer 307 to form an oxide, and an oxide layer is formed at the interface between the work function setting metal layer 304 and the overlying barrier layer 305, that is, at the interface on top of the oxygen-rich layer 304a, so that the diffusion of the metal such as aluminum in the subsequently formed metal electrode layer 307 toward the semiconductor substrate 300 can be blocked. In other embodiments of the present invention, oxygen may be introduced into the upper surface of the work function setting metal layer 304 by oxygen plasma surface treatment or oxygen ion implantation, so as to precisely control the concentration and depth of the introduced oxygen, but the manufacturing cost may be increased. In addition, in the present invention, only the upper surface layer of the work function setting metal layer 304 is converted into an oxygen-rich layer, instead of converting the entire work function setting metal layer 304 into an oxygen-rich layer, in order to improve the blocking capability of the electrode metal diffused downward from the metal electrode layer, while ensuring that the work function set by the work function setting metal layer 304 is not affected.
It should be noted that, in other embodiments of the present invention, steps E1 and E2 may be performed alternatively or both, and may be selected according to the performance requirement of the device. When only E2 is performed, the deposition formation of the interfacial layer 301, the high-K gate dielectric layer 302, the metal barrier layer 303, and the workfunction setting metal layer 304 may be performed in a manner that does not break the vacuum between depositions.
In step S3, the capping barrier layer 305 may be deposited on the surface of the work function setting metal layer 304 by a deposition process such as ordinary Chemical Vapor Deposition (CVD), Low Pressure Chemical Vapor Deposition (LPCVD), Metal Organic Chemical Vapor Deposition (MOCVD), Atomic Layer Deposition (ALD), etc., and the material of the capping barrier layer 305 may include at least one of metal nitride, metal carbonitride, and metal silicon nitride, wherein the metal element includes a metal element of group IVB and/or VB of the periodic table, for example, at least one of titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), and tantalum (Ta). In this embodiment, an extensensa deposition system is used to deposit the capping barrier layer 305 (for example, TiN, TaSiN, TiAlN, or TaAlN) to achieve good process control, so that the capping barrier layer 305 and the work function setting metal layer 304 are clustered together, thereby achieving a strong adhesion between the capping barrier layer 305 and the work function setting metal layer 304 and protecting the work function setting metal layer 304 from the surrounding environment; and acts as a diffusion barrier to oxygen in the oxygen-rich layer 304a while increasingThe thickness of the overlying barrier layer 305 (e.g., made of
Figure BDA0001316951070000081
Is improved to
Figure BDA0001316951070000082
) The thickness of the metal layer is larger than that of the work function setting metal layer 304 to obtain a good gap filling capability, so that the covering barrier layer 305 can be completely filled at the corner position of the active region of the semiconductor substrate 300, and the covering barrier layer 305 can be used as a good barrier layer for the diffusion of metal such as aluminum in the subsequent metal electrode layer 307. The Extensa system (Applied Materials, Inc of Santa, Clara, California) is a new type of dual magnet PVD system with flux shaping capability that provides unequalled step coverage and can control up to 10 or less particles at 0.12 μm or more, wherein the process gas can comprise an inert gas such as argon (Ar), helium (He), krypton (Kr), neon (Ne), xenon (Xe), or the like. In this embodiment, after forming the blanket barrier layer 305, a wetting metal layer 306 is formed on the blanket barrier layer 305 without breaking the vacuum between depositions. The wetting metal layer 306 can be used as an adhesive layer, which can improve the adhesion between the metal electrode layer 307 deposited subsequently and the layers below, and enhance the gap filling effect of the metal electrode layer 307. The wetting metal layer 306 is preferably a pure metal or an alloy containing the metal elements in the overlying barrier layer 305 to maximize adhesion. In other embodiments of the present invention, the step S3 can be omitted, i.e. the covering barrier layer 305 and the wetting metal layer 306 are omitted
In step S4, the present embodiment deposits a metal electrode layer 307 on the wetting metal layer 306 after depositing the wetting metal layer 306 without breaking the vacuum between depositions. The metal electrode layer 307 may be implemented by electroplating, ALD, CVD, or aluminum reflow, and the material thereof includes at least one of aluminum (Al), copper (Cu), nickel (Ni), chromium (Cr), tungsten (W), titanium (Ti), tantalum (Ta), silver (Ag), gold (Au), and platinum (Pt).
In view of the above, the method for manufacturing a metal Gate according to the present invention introduces oxygen in a manner of air break before and/or after deposition of the work function setting metal layer to block diffusion of the electrode metal in the metal electrode layer toward the semiconductor substrate, thereby improving reliability of the device and reducing failure rate, and can be used for manufacturing semiconductor devices using a Gate-first (Gate-first) process and a Gate-last (Gate-last) process, and is particularly suitable for manufacturing NMOS devices having nodes of 28nm and below. In the manufacturing process of forming a device by using a gate-first process, the manufacturing method of the metal gate of the present invention may be adopted to sequentially form a high-K gate dielectric layer 302, a metal barrier layer 303, a work function setting metal layer 304, a covering barrier layer 305, a wetting metal layer 306, and a metal electrode layer 307 on a semiconductor substrate, and then perform corresponding etching on these layers, so as to obtain a high-K metal gate structure. The following describes a method for manufacturing a semiconductor device according to the present invention in detail, taking a process for manufacturing a semiconductor device by combining a metal gate manufacturing method of the present invention with a gate last process as an example.
Referring to fig. 4, the method for manufacturing a semiconductor device of the present invention includes the following steps:
first (i.e., S0), providing a semiconductor substrate having a gate opening;
then, with the manufacturing method of a metal gate shown in fig. 2, a stacked structure including a metal barrier layer and a work function setting layer is formed on the gate opening and the surface of the semiconductor substrate, that is, a method including:
s1: forming a metal barrier layer on the surface of the semiconductor substrate and the surface of the grid opening;
s2: forming a work function setting metal layer on the metal barrier layer;
s3: forming a metal electrode layer for manufacturing a metal gate on the work function setting metal layer; and
e1: making the upper surface layer of the metal barrier layer an oxygen-rich layer, and/or, E2: and enabling the upper surface layer of the work function setting metal layer to be an oxygen-enriched layer.
Referring to fig. 5A to 5C, the process of providing the semiconductor substrate having the gate opening in step S0 includes:
first, referring to fig. 5A, a semiconductor substrate 500 is provided, and a replacement gate structure is formed on the semiconductor substrate 500, wherein the replacement gate structure includes a silicon dioxide gate dielectric layer 501a and a replacement gate electrode layer 501b sequentially disposed on the semiconductor substrate 500. The semiconductor substrate 500 may be selected from a bulk silicon substrate, Silicon On Insulator (SOI), or may also include other materials such as III-V compounds such as gallium arsenide. Device isolations such as wells (wells), Active Areas (AA), shallow trench isolation structures and the like can be formed in the semiconductor substrate 500, fins can also be formed on the surface of the semiconductor substrate 500 to improve the density and performance of the devices, and the replacement gate structures are located on the surfaces of the fins. The gate-replacement electrode layer 501b may be at least one of polycrystalline silicon (poly Si), germanium, silicon germanium, single crystal silicon, amorphous silicon, a metal (e.g., Al, Ti, Ta, etc.), an alloy, and a metal nitride (e.g., TiN, TaN, etc.). In this embodiment, the replacement gate electrode layer 501b is polysilicon.
Next, referring to fig. 5A, a sidewall 501c is formed on the sidewall of the replacement gate structure, and specifically, a sidewall material such as nitride, oxide, or oxynitride may be deposited on the surface of the replacement gate structure and the exposed interface layer thereof through a suitable deposition process, such as a Low Pressure Chemical Vapor Deposition (LPCVD) or a plasma enhanced deposition (PECVD) process, and then the sidewall material is etched to form the sidewall 501c covering the replacement gate structure.
Then, referring to fig. 5A, a drain region 501d and a source region 501e are formed in the semiconductor substrate 500 at two sides of the replacement gate structure and the sidewall 501 c. One process for forming the drain region 501d and the source region 501e includes: after the side wall 501c is formed, etching the side wall 501c and the semiconductor substrate 500 at two sides of the replacement gate structure by a dry etching process or a process combining dry etching and wet etching to form a source/drain trench in a U shape or a sigma shape; then, a selective epitaxy process is adopted to perform epitaxial growth on a semiconductor layer different from the material of the semiconductor substrate 500 in the source/drain trench, the epitaxially grown semiconductor layer is made of materials such as silicon germanium (SiGe), germanium (Ge), silicon (Si), silicon carbon (SiC), tin germanium (GeSn), tin silicon germanium (SiGeSn), tin silicon (SiSn) or III-V materials, and during the epitaxial growth of the semiconductor layer in the source/drain trench, the semiconductor layer can be subjected to in-situ ion doping, or after the epitaxial growth, the semiconductor layer is subjected to ion implantation and annealing activation to dope ions, so that the dope ions are diffused to the bottom of the semiconductor substrate 500 and the bottom of the sidewall 501c to form a raised drain region 501d and a raised source region 501e (in a U-shape or Σ -shape), and the top of the raised drain region 501d and raised source region 501e is usually higher than the top of the semiconductor substrate 500, thereby applying stress to the channel region under the replacement gate structure to increase carrier mobility and improve device performance. Another process for forming the drain region 501d and the source region 501e includes: taking the replacement gate structure and the sidewall 501c as masks, LDD (lightly doped drain) ion implantation, source-drain region heavy doping (S/D) ion implantation, and the like are directly performed in the semiconductor substrate 500 (i.e., an active region) on both sides of the replacement gate structure and the sidewall 501c, and the implanted ions are annealed and activated to form a drain region 501D and a source region 501e, and the top surfaces of the drain region 501D and the source region 501e formed by the process are flush with the top surface of the semiconductor substrate 500, as shown in fig. 5A.
In addition, after the drain region 501d and the source region 501e are formed, a metal silicide may be further formed on the surfaces of the drain region 501d and the source region 501e for subsequent electrical contact, so as to reduce contact resistance. The forming process of the metal silicide comprises the following steps: depositing metal layers of titanium (Ti), cobalt (Co), nickel (Ni) or tungsten (Wu) on the surfaces of the drain region 501d and the source region 501e, the side wall 501c and the replacement gate structure, annealing the metal layers to enable the metal layers to react with silicon and the like of the drain region 501d and the source region 501e to form metal silicide, and finally removing the unreacted metal layers.
Referring to fig. 5B, an interlayer dielectric layer 502 may be deposited on the semiconductor substrate 500, the replacement gate structure and the sidewall 501c by a deposition process such as a general Chemical Vapor Deposition (CVD), a plasma enhanced deposition (PECVD), a Metal Organic Chemical Vapor Deposition (MOCVD), an Atomic Layer Deposition (ALD), etc., and the replacement gate electrode layer 501B is used as a stop layer to perform a chemical mechanical polishing on the interlayer dielectric layer 502, so that the top surface of the interlayer dielectric layer 502 is flat. The interlayer dielectric layer 502 may be silicon oxide, silicon nitride, silicon oxynitride, or a low-K dielectric having a dielectric constant K of less than 3.0, such as silicon oxycarbide (SiCO), undoped silicate glass, doped silicon oxide (such as borophosphosilicate glass BPSG, fused silica glass FSG, phosphosilicate glass PSG, boron doped silica glass BSG), and/or other suitable dielectric materials
Referring to fig. 5C, the replacement gate electrode layer 501b is removed by a wet etching process, a dry etching process, or a process of first dry etching and then wet etching, so as to form a gate opening in the interlayer dielectric layer 502. If dry etching is used, a gas containing a halogen (e.g., CF) may be used4、SF6、NF3、Cl2HBr) having a higher lateral to longitudinal etch rate ratio (e.g., lateral etch rate/longitudinal etch rate greater than or equal to 0.5) such that the longitudinal etch rate is slower than the lateral etch rate, the longitudinal etch rate is slowed down to more easily control the longitudinal etch process such that the dry etch can controllably stop at the surface of silicon dioxide gate dielectric layer 501 a. In the case of wet etching, a tetramethylammonium hydroxide (TMAH) solution may be used for etching removal, or a mixed solution of nitric acid and hydrofluoric acid may be used for etching removal. In other embodiments of the present invention, the replacement gate structure may be completely removed, i.e., the replacement gate electrode layer 501b and the silicon dioxide gate dielectric layer 501a are removed.
Referring to fig. 5D, next, the manufacturing method of the metal gate shown in fig. 2 may be adopted, a high-K gate dielectric layer 503, a metal barrier layer 504, a work function setting metal layer 505, a covering barrier layer 506 and a metal electrode layer 507 are sequentially formed on the surfaces of the interlayer dielectric layer 502, the sidewall 501c and the gate opening, that is, the forming process of the high-K gate dielectric layer 503 may refer to the process of the high-K gate dielectric layer 302, the forming process of the metal barrier layer 504 may refer to the forming process of the metal barrier layer 303, the forming process of the work function setting metal layer 505 may refer to the forming process of the work function setting metal layer 304, the forming process of the covering barrier layer 506 may refer to the forming process of the covering barrier layer 305, the forming process of the metal electrode layer 507 may refer to the forming process of the metal electrode layer 307, and before and/or after the deposition of the work function setting metal layer 505, the Oxygen is formed to form the oxygen-rich layer 504a and/or the oxygen-rich layer 505a, and the detailed process is not repeated herein.
Referring to fig. 5E, after depositing the metal electrode layer 507, a chemical mechanical polishing process may be performed to planarize the top of the metal electrode layer 507 and the like until the surface of the interlayer dielectric layer 502, thereby completing the manufacturing of the semiconductor device.
Referring to fig. 5E, the present invention further provides a metal gate, which includes a metal barrier layer 504, a work function setting metal layer 505 and a metal electrode layer 507 sequentially disposed on a semiconductor substrate 500. And a covering barrier layer 506 sequentially disposed between the work function setting metal layer 505 and the metal electrode layer 507. At least one of the metal barrier layer 504 and the work function setting metal layer 505 has an oxygen-rich layer on its top surface, and an oxide layer (not shown) is formed on the interface of the top of the oxygen-rich layer, and the oxide layer is formed by the diffusion of the metal in the metal electrode layer to the oxygen-rich layer and the reaction with the oxygen-rich layer. In this embodiment, the upper surfaces of the metal barrier layer 504 and the work function setting metal layer 505 are both oxygen-rich layers, as shown by 504a and 505a in fig. 5E. The metal barrier layer 504 may be a single layer or a stacked layer, and the material thereof includes at least one of metal nitride, metal carbonitride, and metal silicon nitride. The work function setting metal layer 505 has a work function of less than 4.2eV and may include at least one of metal carbide, metal nitride, pure metal, and alloy. The material of the capping barrier layer 506 may include at least one of a metal nitride, a metal carbonitride, and a metal silicon nitride, and the material of the capping barrier layer 506 may be the same as or different from the metal barrier layer 504. Preferably, the thickness of the covering barrier layer 506 is greater than that of the work function setting metal layer 505, so that on one hand, a subsequent metal electrode layer has good gap filling capability, and on the other hand, electrode metal in the metal electrode layer can be further prevented from diffusing towards the direction of the semiconductor substrate. The material of the metal electrode layer 507 includes at least one of aluminum (Al), copper (Cu), nickel (Ni), chromium (Cr), tungsten (W), titanium (Ti), tantalum (Ta), silver (Ag), gold (Au), and platinum (Pt). In other embodiments of the present invention, the metal gate further comprises a wetting metal layer between the capping barrier layer 506 and the metal electrode layer 507, and the wetting metal layer is preferably a pure metal or an alloy containing the metal element in the capping barrier layer 506 to maximize the adhesion performance.
Referring to fig. 5E, the present invention further provides a semiconductor device, which includes a semiconductor substrate 500, and a high-K gate dielectric layer 503 and a metal gate sequentially located on the semiconductor substrate 500, and further includes a sidewall 501c located at two sides of the high-K gate dielectric layer 503 and the metal gate, and a drain region 501d and a source region 501E located at two sides of the high-K gate dielectric layer 503, the metal gate and the sidewall 501 c. The metal gate comprises a metal barrier layer 504, a work function setting metal layer 505, a covering barrier layer 506 and a metal electrode layer 507 which are sequentially arranged on the surface of the high-K gate dielectric layer 503, wherein the upper surface layer of at least one of the metal barrier layer 504 and the work function setting metal layer 505 is an oxygen-rich layer. The semiconductor device may be an SRAM device in which the workfunction setting metal layer 505 has a workfunction of less than 4.2 eV.
In addition, we also experimentally verify the technical effect of the technical solution of the present invention, specifically, compared to the process recipe (baseline recipe) of the SRAM device shown in fig. 1C, the new process recipe (new recipe) is only adjusted as follows: introducing oxygen in an air-break manner both before and after deposition of the work function setting metal layer; and the overlying barrier layer is thickened. Corresponding SRAM devices are manufactured according to the new process recipe, and FIG. 6 shows threshold voltage test curves of PD NFET elements at various positions on a wafer of the SRAM device manufactured by the invention, so that the deviation of the threshold voltage (Vtstat) of the PD NFET at the wafer center and the wafer edge of the SRAM device is greatly reduced to about 20 mv.
Therefore, in the manufacturing method of the semiconductor device, in the process of manufacturing the metal gate structure, the upper surface layer of at least one of the metal barrier layer and the work function setting metal layer is an oxygen-rich layer, so that metal diffusion of the metal gate electrode layer can be blocked, and the reliability of the device is greatly improved.
It will be apparent to those skilled in the art that various changes and modifications may be made in the invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims (12)

1. A method for manufacturing a metal gate electrode comprises the following steps:
forming a metal barrier layer on a semiconductor substrate;
forming a work function setting metal layer on the metal barrier layer;
forming a covering barrier layer on the work function setting metal layer, wherein the thickness of the covering barrier layer is respectively greater than that of the work function setting metal layer and that of the metal barrier layer, and the covering barrier layer covers the surface of the work function setting metal layer and is clustered with the work function setting metal layer;
forming a metal electrode layer for manufacturing the metal grid on the covering barrier layer;
wherein, in the metal barrier layer and the work function setting metal layer, the upper surface layer of at least one of the metal barrier layer and the work function setting metal layer is an oxygen-enriched layer; the semiconductor substrate is provided with a gate opening, the metal barrier layer, the work function setting metal layer and the covering barrier layer sequentially cover the inner surface of the gate opening, and the metal electrode layer is filled in the gate opening.
2. The method of manufacturing a metal gate according to claim 1, wherein an upper surface of the metal barrier layer is changed to an oxygen-rich layer by introducing oxygen into the metal barrier layer before forming the work function setting metal layer on the metal barrier layer;
after forming a work function setting metal layer on the metal barrier layer, an upper surface of the work function setting metal layer becomes an oxygen-rich layer by introducing oxygen into the work function setting metal layer.
3. The method of manufacturing a metal gate according to claim 2, wherein the metal barrier layer is a single layer or a stacked layer, and when the metal barrier layer is a stacked layer, the top barrier layer is made to serve as an oxygen-rich layer of the metal barrier layer by introducing oxygen into at least a top barrier layer of the metal barrier layer which is next to the work function setting metal layer.
4. The method according to any one of claims 1 to 3, wherein an upper surface layer of at least one of the metal barrier layer and the work function setting metal layer is an oxygen-rich layer by air break, oxygen plasma surface treatment, or oxygen ion implantation.
5. The method of manufacturing a metal gate of claim 3, wherein when the metal barrier layer is a stack, an atomic layer deposition process is used to form a top barrier layer of the metal barrier layer next to the work function setting metal layer.
6. The method of claim 1, wherein the capping barrier layer is formed using an Extensa deposition system.
7. The method of claim 1, further comprising: forming a high-K gate dielectric layer on the semiconductor substrate before forming the metal barrier layer on the semiconductor substrate; and forming a wetting metal layer between the covering barrier layer and the metal electrode layer.
8. A metal gate comprises a metal barrier layer, a work function setting metal layer, a covering barrier layer and a metal electrode layer which are sequentially arranged on a semiconductor substrate; the semiconductor substrate is provided with a gate opening, the metal barrier layer, the work function setting metal layer and the covering barrier layer sequentially cover the inner surface of the gate opening, and the metal electrode layer is filled in the gate opening; the metal barrier layer and the work function setting metal layer are characterized in that the upper surface layer of at least one of the metal barrier layer and the work function setting metal layer is an oxygen-rich layer, an oxide layer is formed on the interface of the top of the oxygen-rich layer, and the oxide layer is formed by the metal in the metal electrode layer diffusing to the oxygen-rich layer and reacting with the oxygen-rich layer; the thickness of the covering barrier layer is respectively larger than that of the work function setting metal layer and the metal barrier layer, and the covering barrier layer covers the surface of the work function setting metal layer and is clustered with the work function setting metal layer.
9. The metal gate of claim 8, wherein the material of the capping barrier layer comprises at least one of a metal nitride, a metal carbonitride, and a metal silicon nitride.
10. A method of manufacturing a semiconductor device, comprising:
providing a semiconductor substrate with a gate opening;
forming a metal gate structure including a metal barrier layer, a work function setting layer, a capping barrier layer, and a metal electrode layer on the surface of the semiconductor substrate, the metal gate structure being filled in the gate opening, by using the method of manufacturing a metal gate according to any one of claims 1 to 7.
11. The method of manufacturing a semiconductor device according to claim 10, wherein the semiconductor substrate includes a semiconductor base and an interlayer dielectric layer on a surface of the semiconductor base, the interlayer dielectric layer having the gate opening therein.
12. A semiconductor device comprising a semiconductor substrate and a metal gate according to any one of claims 8 to 9 on the semiconductor substrate.
CN201710429096.7A 2017-06-08 2017-06-08 Metal gate, semiconductor device and manufacturing method thereof Active CN109037046B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201710429096.7A CN109037046B (en) 2017-06-08 2017-06-08 Metal gate, semiconductor device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201710429096.7A CN109037046B (en) 2017-06-08 2017-06-08 Metal gate, semiconductor device and manufacturing method thereof

Publications (2)

Publication Number Publication Date
CN109037046A CN109037046A (en) 2018-12-18
CN109037046B true CN109037046B (en) 2021-04-02

Family

ID=64629222

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710429096.7A Active CN109037046B (en) 2017-06-08 2017-06-08 Metal gate, semiconductor device and manufacturing method thereof

Country Status (1)

Country Link
CN (1) CN109037046B (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109950134B (en) * 2019-03-19 2022-01-21 中国科学院上海高等研究院 Structure with oxide thin film and preparation method thereof
CN112582333A (en) * 2019-09-27 2021-03-30 中芯长电半导体（江阴）有限公司 Rewiring layer and preparation method thereof

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102097382A (en) * 2009-12-15 2011-06-15 中芯国际集成电路制造(上海)有限公司 Method for manufacturing semiconductor device
CN103311281A (en) * 2012-03-14 2013-09-18 中国科学院微电子研究所 Semiconductor device and manufacturing method thereof
CN105609420A (en) * 2014-11-18 2016-05-25 台湾积体电路制造股份有限公司 Selective growth for high-aspect ration metal fill
CN105990347A (en) * 2015-01-30 2016-10-05 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102097382A (en) * 2009-12-15 2011-06-15 中芯国际集成电路制造(上海)有限公司 Method for manufacturing semiconductor device
CN103311281A (en) * 2012-03-14 2013-09-18 中国科学院微电子研究所 Semiconductor device and manufacturing method thereof
CN105609420A (en) * 2014-11-18 2016-05-25 台湾积体电路制造股份有限公司 Selective growth for high-aspect ration metal fill
CN105990347A (en) * 2015-01-30 2016-10-05 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof

Also Published As

Publication number Publication date
CN109037046A (en) 2018-12-18

Similar Documents

Publication Publication Date Title
US11031482B2 (en) Gate electrode having a capping layer
US9059313B2 (en) Replacement gate having work function at valence band edge
US8507991B2 (en) Semiconductor device and method of manufacturing the same
JP4002868B2 (en) Dual gate structure and method of manufacturing integrated circuit having dual gate structure
US9281373B2 (en) Semiconductor device having tungsten gate electrode and method for fabricating the same
US7531399B2 (en) Semiconductor devices and methods with bilayer dielectrics
US11018232B2 (en) Semiconductor device and fabrication method thereof
US8673758B2 (en) Structure of metal gate and fabrication method thereof
US10199228B2 (en) Manufacturing method of metal gate structure
CN106960847B (en) Method for manufacturing memory device
US20080105920A1 (en) Semiconductor devices and fabrication process thereof
US7511338B2 (en) Semiconductor device and manufacturing method of the same
US20080146012A1 (en) Novel method to adjust work function by plasma assisted metal incorporated dielectric
CN109037046B (en) Metal gate, semiconductor device and manufacturing method thereof
CN107546121B (en) Semiconductor device and manufacturing method thereof
CN109119335B (en) Work function layer, metal gate, semiconductor device and manufacturing method thereof
TWI509702B (en) Metal gate transistor and method for fabricating the same
TWI446456B (en) Metal gate transistor and method for fabricating the same
US9449829B1 (en) Semiconductor process
TWI490949B (en) Metal gate transistor and method for fabricating the same
TWI811991B (en) Semiconductor device and method for fabricating the same
US11855186B2 (en) Semiconductor device and manufacturing method thereof
WO2024023603A1 (en) Isolation pillar structures for stacked device structures
CN114121626A (en) Method for manufacturing semiconductor element
TW201320336A (en) Metal oxide semiconductor transistor and manufacturing method thereof

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant