CN107910298A - The production method of semiconductor CMOS device - Google Patents
The production method of semiconductor CMOS device Download PDFInfo
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- CN107910298A CN107910298A CN201711110992.3A CN201711110992A CN107910298A CN 107910298 A CN107910298 A CN 107910298A CN 201711110992 A CN201711110992 A CN 201711110992A CN 107910298 A CN107910298 A CN 107910298A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
Abstract
The invention discloses a kind of production method of semiconductor CMOS device, including：The N-type separated by shallow channel isolation area and a part of p-type MOSFET are formed on substrate；Removing false gate stack in N-type and p-type MOSFET, to form respective gate openings, exposes substrate surface；Interfacial oxide layer, high-K gate dielectric layer and the first Metal gate layer are sequentially formed at N-type MOSFET and the respective gate openings of p-type MOSFET；Is utilized by isotropic plasma doping Doped ions in the first Metal gate layer to another, Doped ions is only distributed only in the first Metal gate layer into line mask by one in N-type and p-type MOSFET respectively；The second Metal gate layer is formed to fill gate openings on the first Metal gate layer after doping；And carry out annealing and spread Doped ions and accumulate in the upper interface of high-K gate dielectric layer and lower interface, and interface, lower interface are respectively formed electric dipole by interfacial reaction on this.This method technique is simple, overcomes the defects of ion implanting.
Description
Technical field
The disclosure belongs to technical field of semiconductors, is related to a kind of production method of semiconductor CMOS device.
Background technology
In the CMOS applications of integrated N-type and p-type MOSFET, in order to obtain suitable threshold voltage, N-type MOSFET's has
Imitating work function should be near the conduction band bottom of Si (4.1eV or so), and the effective work function of p-type MOSFET should be in the top of valence band of Si
Nearby (5.2eV or so).
Existing processing method is to select different metal gates and high K grid to be situated between respectively for N-type MOSFET and p-type MOSFET
The combination of matter is to realize required threshold voltage.As a result, it is desirable to bimetal gate and double high-K gate dielectrics are formed on a single die.
During the making of semiconductor devices, respective light is performed for the metal gate and high-K gate dielectric of N-type and p-type MOSFET respectively
Carve and etching step, the method technique for the semiconductor devices for so causing to include bimetal gate and double grid medium for making are answered
It is miscellaneous, be not suitable for batch production, further cause with high costs.In addition in the prior art, by using the side of ion implanting
Method is doped in the first Metal gate layer and adjusts distribution of the Doped ions in gate stack by subsequent annealing process, with
Adjust the threshold voltage of MOSFET, still, the method for existing ion implanting be doped there are its it is intrinsic the shortcomings that, including：
Ion implanting shadow effect；The problem of energy contamination problem and low production efficiency in small energy injection.
The content of the invention
(1) technical problems to be solved
Present disclose provides a kind of production method of semiconductor CMOS device, admirably solves the technology that the above is run into
Problem.
(2) technical solution
According to one aspect of the disclosure, there is provided a kind of production method of semiconductor CMOS device, including：On substrate
A part of the N-type MOSFET separated by shallow channel isolation area and p-type MOSFET are formed, including：Source/drain in substrate
The false gate stack of area, on substrate orientation between source/drain region and the grid curb wall around false gate stack；Remove N-type
False gate stack reveals the surface of substrate to form respective gate openings on the inside of grid curb wall in MOSFET and p-type MOSFET
Go out；Interfacial oxide layer, high-K gate dielectric layer and are sequentially formed at N-type MOSFET and the respective gate openings of p-type MOSFET
One Metal gate layer；One in N-type MOSFET and p-type MOSFET is sheltered respectively, another is utilized isotropic
Plasma doping Doped ions in the first Metal gate layer, and control the energy of plasma so that Doped ions only divide
Cloth in the first Metal gate layer, and according to desired threshold voltage control ion implanting dosage；The first metal after doping
The second Metal gate layer is formed in grid layer to fill gate openings；And carry out annealing and spread Doped ions and accumulate in height
At upper interface between K gate dielectric layers and the first Metal gate layer and the lower bound between high-K gate dielectric layer and interfacial oxide layer
At face, and interface, lower interface are respectively formed electric dipole by interfacial reaction on this.
In some embodiments of the present disclosure, the energy of plasma doping is between 0.1keV-20keV.
In some embodiments of the present disclosure, the dosage of ion implanting is between 1E13-5E15cm-2Between.
In some embodiments of the present disclosure, the Doped ions of N-type MOSFET are N type dopant, which is energy
Enough reduce the dopant of effective work function；The Doped ions of p-type MOSFET are P-type dopant, which is to increase
The dopant of effective work function.
In some embodiments of the present disclosure, N type dopant includes：Phosphorus and hydride of arsenic, fluoride, are following material
In one kind or its combination：Phosphine, arsine, phosphorus pentafluoride, phosphorus trifluoride, arsenic pentafluoride or arsenic trifluoride；And/or p-type doping
Agent includes：Hydride, fluoride or the chloride of boron, are one kind in following material or its combination：B2H6、B4H10、B6H10、
B10H14、B18H22、BF3Or BCl3。
In some embodiments of the present disclosure, the material of high-K gate dielectric layer is one kind of following material or its combination：
ZrO2、ZrON、ZrSiON、HfZrO、HfZrON、HfON、HfO2, HfAlO, HfAlON, HfSiO, HfSiON, HfLaO or
HfLaON；And/or first Metal gate layer material be following material in one kind or its combination：TiN, TaN, MoN, WN, TaC or
TaCN；And/or second Metal gate layer include multiple layer metal material, wherein against the first Metal gate layer metal material select oxygen uptake
The good metal of performance, including：At least one of Ti, TiAl, Ta；Followed by potential barrier barrier metal, including：TiN, TaN,
One or both of Ta, MoN, A1N, WN；It is finally filling metal, including：One or both of W, Al, TiAl, Mo.
In some embodiments of the present disclosure, the thickness of high-K gate dielectric layer is between 1.5nm-5nm；And/or first gold medal
Belong to the thickness of grid layer between 1nm-10nm.
In some embodiments of the present disclosure, the condition that carrying out annealing spreads Doped ions is：Annealing temperature is
350 DEG C -450 DEG C, annealing time 20min-90min.
In some embodiments of the present disclosure, a part of N-type MOSFET and p-type MOSFET further include：Silicification area, forms
In the surface of respective source/drain region；And interlayer dielectric layer, it is covered in top, the grid curb wall outer surface of respective source/drain region
The top of surrounding and false gate stack；The vacation gate stack includes：False gate medium and false grid conductor, and thrown using chemical machinery
The surface of light planarization interlayer dielectric layer and the top surface of the false grid conductor of exposure.
In some embodiments of the present disclosure, after high-K gate dielectric layer is formed, before the first Metal gate layer is formed also
Include the following steps：Made annealing treatment after the making of high-K gate dielectric layer is completed, to improve the quality of high-K gate dielectric layer.
(3) beneficial effect
It can be seen from the above technical proposal that the production method for the semiconductor CMOS device that the disclosure provides, has following
Beneficial effect：
(1) ion injection method is instead of in first layer metal using isotropic plasma doping (PLAD) method
The doping of N type dopant and P-type dopant is carried out in grid respectively, the doping of preferable dopant isotropic distribution can be obtained,
It is inferior to overcome ion implanting shadow effect existing for ion implanting, the energy contamination in small energy injection, low production efficiency
Defect；
(2) by regulating and controlling the species and PLAD energy and dosage of dopant, it is possible to realize to p-type MOSFET and N-type
The threshold voltage adjustments of MOSFET, without using the various combination of metal gate and gate medium respectively, therefore eliminate corresponding
Deposition step and mask and etch step, technique and be easy to produce in batches it is achieved thereby that simplifying, reduce cost.
Brief description of the drawings
Fig. 1 is the flow chart according to the production method of embodiment of the present disclosure semiconductor CMOS device.
Fig. 2A-Fig. 2 G partly lead for each step is corresponding in the manufacturing process according to embodiment of the present disclosure semiconductor CMOS device
The schematic cross-section of body structure.
Fig. 2A be after the completion of grid technique cmos device source/drain region, false gate stack, grid curb wall and interlayer dielectric layer etc.
Partial structure diagram.
Fig. 2 B are the structure diagram that the false gate stack of etching N-type and p-type MOSFET form respective gate openings respectively.
Fig. 2 C are to sequentially form interfacial oxide layer, high K grid at N-type and the respective gate openings of p-type MOSFET respectively
Structure diagram after dielectric layer and the first Metal gate layer.
Fig. 2 D are the active area that p-type MOSFET is blocked using mask, and PLAD is used in the first Metal gate layer of N-type MOSFET
Method doped N-type dopant process schematic.
Fig. 2 E are the active area that N-type MOSFET is blocked using mask, and PLAD is used in the first Metal gate layer of p-type MOSFET
Method doped p-type dopant process schematic.
After Fig. 2 F is remove mask, the structure of the second Metal gate layer of covering is formed on the first Metal gate layer after doping
Schematic diagram.
Fig. 2 G are using interlayer dielectric layer as stop-layer, carry out the structure diagram after surface planarisation.
【Symbol description】
101- substrates；102- shallow channel isolation areas；
The false gate mediums of 103a- first；The false gate mediums of 103b- second；
The false grid conductors of 104a- first；The false grid conductors of 104b- second；
105a- first grid side walls；105b- second grid side walls；
The first source/drain regions of 106a-；The second source/drain regions of 106b-；
The first silicification areas of 107a-；The second silicification areas of 107b-；
108- interlayer dielectric layers；
The first interfacial oxide layers of 109a-；109b- second contact surface oxide skin(coating)s；
110,110a, 110b- high-K gate dielectric layer；The first Metal gate layer of 111,111a, 111b-；
112- the second photoresist masks；113- the first photoresist masks；
The second Metal gate layer of 114,114a, 114b-.
Embodiment
Present disclose provides a kind of production method of semiconductor CMOS device, mixed by using isotropic plasma
Miscellaneous (PLAD) method instead of ion injection method and carry out N type dopant and P-type dopant respectively in first layer metal grid
Doping, and regulate and control the species and PLAD energy and dosage of dopant, reach the mesh of regulation and control N-type and p-type MOSFET effective work functions
, it is low to overcome ion implanting shadow effect existing for ion implanting, the energy contamination in small energy injection, production efficiency
The defects of；And eliminate it is existing deposited respectively using the various combination of metal gate and gate medium, the step of mask and etching
Suddenly, it is achieved thereby that simplifying technique and being easy to produce in batches, cost is reduced.
In the disclosure, term " semiconductor structure " refers to the lining formed after each step of experience making semiconductor devices
Bottom and all layers formed on substrate or region.Term " source/drain region " refers to both source region and drain regions of MOSFET,
And indicated using an identical reference numeral.Term " P-type dopant " refers to can increase effectively for p-type MOSFET
The dopant of work function.Term " N type dopant " refers to the dopant that can reduce effective work function for p-type MOSFET.
In order to distinguish, " the first source/drain region " in specification refers to the source/drain region of N-type MOSFET, and " the second source/drain region " refers to P
The source/drain region of type MOSFET；It is similar, " silicification area ", " false gate medium ", " false grid conductor ", " false gate stack ", " gate electrode side
First, second before wall " and " photoresist mask " is to correspond to N-type MOSFET, p-type MOSFET respectively.
It describe hereinafter many specific details of the disclosure, such as the structure of device, material, size, processing work
Skill and technology, to be more clearly understood that the disclosure.But just as the skilled person will understand, it can not press
The disclosure is realized according to these specific details.Unless hereinafter particularly point out, the various pieces in semiconductor devices can be with
It is made of material well known to those skilled in the art, or the material with similar functions of exploitation in the future can be used.
For the purpose, technical scheme and advantage of the disclosure are more clearly understood, below in conjunction with specific embodiment, and reference
Attached drawing, is further described the disclosure.
In first exemplary embodiment of the disclosure, there is provided a kind of production method of semiconductor CMOS device.
Fig. 1 is the flow chart according to the production method of embodiment of the present disclosure semiconductor CMOS device.
With reference to shown in Fig. 1, the production method of the semiconductor CMOS device of the disclosure, including：
Step S102：A part of N-type MOSFET and p-type MOSFET in semiconductor CMOS device, bag are formed on substrate
Include：Source/drain region in substrate, on substrate false gate stack of the orientation between source/drain region, the grid around false gate stack
Side wall and interlayer dielectric layer；
In this step, semiconductor CMOS device architecture has been completed a part for rear grid technique cmos device.In substrate
A part of N-type MOSFET and p-type MOSFET is formed on 101, is separated by shallow channel isolation area 102 therebetween, wherein, N
The part of type MOSFET includes：First false gate stack, is formed on substrate 101, including：First vacation gate medium 103a and
One false grid conductor 104a；First grid side wall 105a, is centered around around the first false gate stack；First source/drain region 106a, positioned at lining
In bottom 101, the both sides of the first false gate stack are distributed in, and including extending at least partially into below the first false gate medium 103a
Extension area；First silicification area 107a, is formed at the surface of the first source/drain region 106a；The part of p-type MOSFET includes：The
Two false gate stacks, are formed on substrate 101, including：The false grid conductor 104b of second vacation gate medium 103b and second；Second grid
Side wall 105b, is centered around around the second false gate stack；Second source/drain region 106b, in substrate 101, is distributed in the second false grid
The both sides of lamination, and including extending at least partially into the extension area below the second false gate medium 103b；Second silicification area
107b, is formed at the surface of the second source/drain region 106b；And interlayer dielectric layer 108, it is covered in N-type MOSFET and p-type MOSFET
Source/drain active area on and grid curb wall outer surface around.
Fig. 2A be after the completion of grid technique cmos device source/drain region, false gate stack, grid curb wall and interlayer dielectric layer etc.
Partial structure diagram.In the present embodiment, with reference to shown in Fig. 2A, in substrate 101 (for example, silicon substrate or other semiconductors lining
Bottom) on include the active area for being respectively used to N-type MOSFET and p-type MOSFET that is separated by shallow channel isolation area 102.In N-type
The active area of MOSFET, formed includes the false grid conductors of the first vacation gate medium 103a (for example, silica) and first on the substrate 101
The false gate stack of the first of 104a (for example, polysilicon, alpha-Si).The first false gate stack is by first grid side wall 105a (examples
Such as, silicon nitride) surround.The first source/drain region 106a of N-type MOSFET is formd in the substrate 101.First source/drain region 106a
In the both sides of the first false gate stack, and can include extending at least partially into the extension below the first false gate medium 103a
Area.The first silicification area 107a (for example, nickle silicide) is yet forms both on the surface of the first source/drain region 106a, to reduce the first source/drain
The series resistance and contact resistance of area 106a.In the active area of p-type MOSFET, formed includes the second false grid on the substrate 101 is situated between
The false gate stack of the second of the vacation grid conductor 104b of matter 103b (for example, silica) and second (for example, polysilicon, alpha-Si).Should
Second false gate stack is surrounded by second grid side wall 105b (for example, silicon nitride).Form p-type MOSFET's in the substrate 101
Second source/drain region 106b.Second source/drain region 106b can include at least in part positioned at the both sides of the second false gate stack
Extend to the extension area below the second false gate medium 103b.The second silicification area is yet forms both on the surface of the second source/drain region 106b
107b (for example, nickle silicide), to reduce the series resistance and contact resistance of the second source/drain region 106b.
The semiconductor structure further includes the interlayer dielectric layer 108 (for example, silicon nitride, silica) of covering active area.Pass through
Chemically-mechanicapolish polish (CMP), planarize the surface of interlayer dielectric layer 108 and expose the false grid of the first vacation grid conductor 104a and second and lead
The top surface of body 104b, has obtained structure as shown in Figure 2 A.The interlayer dielectric layer 108 is not only protected in a subsequent step
Active area, also serves as hard mask.
Step S104：It is respective to be formed on the inside of grid curb wall to remove false gate stack in N-type MOSFET and p-type MOSFET
Gate openings, expose the surface of substrate；
In this step, by the use of interlayer dielectric layer 108 as hard mask, using the means of dry etching or wet etching by N
False gate stack in type MOSFET and p-type MOSFET removes, and forms gate openings in respective active area, makes the surface of substrate
Expose.
Fig. 2 B are the structure diagram that the false gate stack of etching N-type and p-type MOSFET form respective gate openings respectively.
In the present embodiment, with reference to shown in Fig. 2 B, using interlayer dielectric layer 108 as hard mask, by dry etching, as ion beam milling etches,
Plasma etching, reactive ion etching, laser ablation, or by wherein using the wet etching of etchant solutions, selectivity
Ground removes the false grid conductor 104b of the first vacation grid conductor 104a and second, and further optionally removes the first false gate medium
The false gate medium 103b of 103a and second, in the active area of N-type MOSFET and the active area of p-type MOSFET forming grid respectively opens
Mouthful, and the surface of exposure substrate 101, as shown in Figure 2 B.
Step S106：Sequentially formed at N-type MOSFET and the respective gate openings of p-type MOSFET interfacial oxide layer,
High-K gate dielectric layer and the first Metal gate layer；
Fig. 2 C are to sequentially form interfacial oxide layer, high K grid at N-type and the respective gate openings of p-type MOSFET respectively
Structure diagram after dielectric layer and the first Metal gate layer.In the present embodiment, with reference to shown in Fig. 2 C, pass through chemical oxidation or additional
Thermal oxide, form the first boundary on the exposed surface of the substrate 101 at N-type and the respective gate openings of p-type MOSFET respectively
Face oxide skin(coating) 109a (for example, silica) and second contact surface oxide skin(coating) 109b.Pass through known depositing operation, such as atomic layer
Deposition (ALD), chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), physical vapour deposition (PVD) (PVD), splash
Penetrate, 110 and first Metal gate layer 111 of high-K gate dielectric layer is sequentially formed on the surface of semiconductor structure, corresponds to N-type at this time
110 or first Metal gate layer 111 of high-K gate dielectric layer with p-type MOSFET is same layer material, using primary depositing technique
Realize, avoid and perform respective deposition and follow-up for the metal gate and high-K gate dielectric of N-type and p-type MOSFET respectively
Photoetching and etching step.110 and first Metal gate layer 111 of high-K gate dielectric layer is located on the bottom and side wall in gate openings, but
The respective gate openings of unfilled N-type and p-type MOSFET.
In the present embodiment, high-K gate dielectric layer 110 is more than SiO by dielectric constant2Suitable material form, such as can be
Selected from ZrO2、ZrON、ZrSiON、HfZrO、HfZrON、HfON、HfO2, HfAlO, HfAlON, HfSiO, HfSiON, HfLaO and
One kind of HfLaON.First Metal gate layer 111 is made of the suitable material that can be used for being formed metal gate, such as can be selected from
One kind of TiN, TaN, MoN, WN, TaC and TaCN.In an example, high-K gate dielectric layer 110 is, for example, thickness about 1.5nm-
The HfO of 5nm2Layer, the first Metal gate layer 111 are, for example, the TiN layer of thickness about 1nm-10nm.
Preferably, can also include between the step of forming high-K gate dielectric layer 110 and forming the first Metal gate layer 111
Following steps：Annealed (postdeposition annealing) after the deposition of high-K gate dielectric layer 110 is completed, to change
The quality of kind high-K gate dielectric layer 110, this first Metal gate layer 111 for being conducive to subsequently form obtain uniform thickness.
Step S108：One in N-type MOSFET and p-type MOSFET is sheltered respectively, to another using it is each to
Plasma doping (PLAD) method of same sex Doped ions in the first Metal gate layer, and the energy of plasma is controlled, make
Obtain Doped ions to be only distributed only in the first Metal gate layer, and the dosage of ion implanting is controlled according to desired threshold voltage；
Fig. 2 D are the active area that p-type MOSFET is blocked using mask, and PLAD is used in the first Metal gate layer of N-type MOSFET
Method doped N-type dopant process schematic.Fig. 2 E are the active area that N-type MOSFET is blocked using mask, in p-type
The process schematic of the method doped p-type dopant of PLAD is used in the first Metal gate layer of MOSFET.
With reference to shown in Fig. 2 D and Fig. 2 E, the present embodiment is first to be sheltered p-type MOSFET, to N-type MOSFET first
Metal gate layer carries out the doping of N type dopant, then removes the mask on p-type MOSFET, N-type MOSFET is sheltered,
Carry out the doping of P-type dopant in the first Metal gate layer to p-type MOSFET again.
First, by containing figuratum second photoresist mask comprising exposed and developed photoetching process, formation
112, to block the active area of the active area of p-type MOSFET and exposure N-type MOSFET.Using second photoresist mask
112 carry out PLAD doping, and N type dopant is carried out using PLAD in the first Metal gate layer 111 of the active area of N-type MOSFET
Doping, as shown in Figure 2 D, N type dopant is represented with hollow triangle.
Typical N type dopant can be selected from the hydride of P, the hydride of fluoride and As, fluoride, such as following material
One kind or its combination in material：PH3、PF3、PF5、AsH3、AsF3Or AsF5, but not limited to this.
In the present embodiment, the energy of ion implanting is controlled so that the Doped ions of injection are only distributed only over the first metal gate
In layer 111, without entering high-K gate dielectric layer 110.Control the energy and dosage of PLAD so that the first Metal gate layer 111 has
Suitable doping concentration, to obtain desired threshold voltage.In certain embodiments, the energy of ion implanting is about 0.1keV-
20keV；In certain embodiments, the dosage of ion implanting is about 1E13-5E15cm-2。
After the doping, the second photoresist mask 112 is removed by being ashed or dissolving.
Then, by containing figuratum first photoresist mask comprising exposed and developed photoetching process, formation
113, to block the active area of the active area of N-type MOSFET and exposure p-type MOSFET.Using first photoresist mask
113 carry out PLAD doping, and P-type dopant is carried out using PLAD in the first Metal gate layer 111 of the active area of p-type MOSFET
Doping, as shown in Figure 2 E, P-type dopant is represented with black triangle.
Typical P-type dopant can be selected from hydride, fluoride and the chloride of boron, such as B2H6、B4H10、B6H10、
B10H14、B18H22And BF3And BCl3In one kind or its combination, but not limited to this.
In the present embodiment, the energy of ion implanting is controlled so that the metal ion of injection is only distributed only over the first metal gate
In layer 111, without entering high-K gate dielectric layer 110.Control the dosage of ion implanting so that the first Metal gate layer 111, which has, to be closed
Suitable doping concentration, to obtain desired threshold voltage.In one embodiment, the energy of ion implanting is about 0.1keV-
20keV, dosage are about 1E13-5E15cm-2.After the doping, the first photoresist mask is removed by being ashed or dissolving
113。
Step S110：The second Metal gate layer is formed to fill gate openings on the first Metal gate layer after doping；
After Fig. 2 F is remove mask, the structure of the second Metal gate layer of covering is formed on the first Metal gate layer after doping
Schematic diagram.Fig. 2 G are using interlayer dielectric layer as stop-layer, carry out the structure diagram after surface planarisation.
It should be noted that the first Metal gate layer after using plasma doping is in N-type MOSFET and p-type MOSFET
The corresponding Doped ions in part are different, can play opposite effect to effective work function respectively, and are mainly taken off in attached drawing Fig. 2 F
The technique for showing the second Metal gate layer of deposition, therefore the first Metal gate layer is still marked with 111, and surface planarisation work is being carried out below
After skill, since the second Metal gate layer in N-type MOSFET and p-type MOSFET, the first Metal gate layer and high-K gate dielectric layer are being tied
Separation on structure, therefore in fig 2g, split to represent, the high-K gate dielectric layer of corresponding N-type MOSFET is expressed as：110a,
Second Metal gate layer is expressed as：114a, the first Metal gate layer are expressed as：111a；The high-K gate dielectric layer table of corresponding p-type MOSFET
It is shown as：110b, the second Metal gate layer are expressed as：114b, the first Metal gate layer are expressed as：111b；Wherein, only the first metal gate
Component in the 111a and 111b of layer is different, comprising the Doped ions to effective work function with opposite regulating and controlling effect, because thing
The high-K gate dielectric layer 110a and 110b that reason mode is kept apart, and the second Metal gate layer 114a and 114b include same material
Material.
With reference to shown in Fig. 2 F and Fig. 2 G, in this step, the mode for forming the second Metal gate layer 114 is known deposition work
Skill, as atomic layer deposition (ALD), chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), physical vapor are sunk
Product (PVD), sputtering etc..The thickness of second Metal gate layer 114 is sufficiently thick so as to can at least fill up gate openings, such as Fig. 2 F institutes
Show.This step S110 is further included：Using interlayer dielectric layer 108 as stop-layer, the step of carrying out surface planarisation, such as passing through
Learn the surface of mechanical polishing planarizing semiconductor structures.
In the present embodiment, the second Metal gate layer 114 is made of low-resistance suitable material that can be used for being formed metal gate.
Preferably, the multiple layer metal composition of the second Metal gate layer 114 includes：Wherein against the metal selection oxygen uptake of the first Metal gate layer
The good metal of energy, is such as selected from Ti, and one or both of TiAl, Ta are formed；Followed by potential barrier barrier metal, TiN such as is selected from,
One or both of TaN, Ta, MoN, AlN, WN are formed；It is finally filling metal, is such as selected from W, Al, TiAl, one kind in Mo
Or two kinds of even a variety of compositions, but each composition metal of the second Metal gate layer 114 is not limited only to above-mentioned material.
In the present embodiment, the step of surface planarisation, includes：Remove the second Metal gate layer 114, successively from top to bottom
One Metal gate layer 111 and high-K dielectric layer 110 are located at the part outside gate openings so that the second Metal gate layer 114, the first gold medal
Belong to remainder that grid layer 111 and high-K gate dielectric layer 110 are located inside gate openings respectively as N-type MOSFET and p-type
The gate stack of MOSFET.After the plain step of surface, the 114 (ginseng of the second Metal gate layer in same layer, connection originally
According to shown in Fig. 2 F) kept apart by interlayer dielectric layer 108, it is distributed in respectively among N-type MOSFET and p-type MOSFET, with reference to figure
Shown in 2G, it is distinguish between with different reference numerals, wherein, 114a is the second Metal gate layer of N-type MOSFET, and 114b is p-type
The second Metal gate layer of MOSFET.
In the present embodiment, the gate stack of the N-type MOSFET shown in fig 2g includes the second Metal gate layer 114a, the first gold medal
Belong to grid layer 111a and high-K gate dielectric layer 110a, the gate stack of p-type MOSFET includes the second Metal gate layer 114b, the first metal gate
Layer 111b and high-K gate dielectric layer 110b.Although the gate stack of N-type MOSFET and p-type MOSFET are formed by identical Rotating fields,
The PLAD Doped ions of opposite types are included in the first Metal gate layer of the two, opposite adjusting is played to effective work function and is made
With.
Step S112：Carrying out annealing spreads Doped ions and accumulates in high-K gate dielectric layer and the first Metal gate layer
Between upper interface at and the lower interface between high-K gate dielectric layer and interfacial oxide layer, and on this interface, under
Interface forms electric dipole by interfacial reaction；
After the gate stack for completing N-type MOSFET and p-type MOSFET in step s 110, the annealing of this step S112 is carried out
Step.
In the present embodiment, after contacting and interconnecting known to completion, above-mentioned semiconductor structure is at inert atmosphere (such as N2)
Or weak reducing atmosphere (such as N2And H2Mixed atmosphere) in anneal.In an example, anneal, move back in stove
Fiery temperature is about 350 DEG C -450 DEG C, and annealing time is about 20-90 minutes.Annealing is driven the Doped ions of injection to spread and is built up
At the upper interface of high-K gate dielectric layer 110a and 110b and lower interface, and further in high-K gate dielectric layer 110a and 110b
Upper and lower interface forms electric dipole.Here, the upper interface of high-K gate dielectric layer 110a and 110b refers to its first with top
Interface between Metal gate layer 111a and 111b, the lower interface of high-K gate dielectric layer 110a and 110b refer to that it is corresponded to and lower section
Interface between first interfacial oxide layer 109a and second contact surface oxide skin(coating) 109b.
The annealing changes the distribution of Doped ions.On the one hand, built up in the upper interface of high-K gate dielectric 110a and 110b
Doped ions both changed the property of metal gate, also dipole is formed in interface, so as to advantageously have adjusted CMOSFET's
Effective work function.On the other hand, the Doped ions built up in the lower interface of high-K gate dielectric 110a and 110b also form suitable pole
The electric dipole of property, so as to advantageously further adjust the effective work function of corresponding CMOSFET.
In conclusion present disclose provides a kind of production method of semiconductor CMOS device, using isotropic grade from
Daughter doping (PLAD) method instead of that ion injection method carries out N type dopant respectively in first layer metal grid and p-type is mixed
Miscellaneous dose of doping, can obtain the doping of preferable dopant isotropic distribution, overcome ion implanting existing for ion implanting
Shadow effect, the energy contamination in small energy injection, under low production efficiency the defects of；In addition, the kind by regulating and controlling dopant
Class and PLAD energy and dosage, it is possible to the threshold voltage adjustments to p-type MOSFET and N-type MOSFET are realized, without dividing
Not Shi Yong metal gate and gate medium various combination, therefore eliminate corresponding deposition step and mask and etch step so that
Realize simplified technique and be easy to produce in batches, reduce cost.
It should be noted that do not describe all details of MOSFET hereinbefore, such as source/drain region contacts, adds
Interlevel dielectric layer and conductive channel formation.The standard CMOS process of above-mentioned part is formed known to those skilled in the art
And how to be applied in the MOSFET of above-described embodiment, therefore this is no longer described in detail.It should also be noted that, carried in embodiment
The direction term arrived, such as " on ", " under ", "front", "rear", "left", "right" etc., are only the directions of refer to the attached drawing, are not used for
Limit the protection domain of the disclosure.Through attached drawing, identical element is represented by same or like reference numeral.It may lead
When cause understanding of this disclosure causes to obscure, conventional structure or construction will be omitted.And the shape and size of each component are not in figure
Reflect actual size and ratio, and only illustrate the content of the embodiment of the present disclosure.In addition, in the claims, it should not will be located at and include
Any reference symbol between number is configured to limitations on claims.
Unless there are known entitled phase otherwise meaning, the numerical parameter in this specification and appended claims are approximations, energy
Enough required characteristic changings according to as obtained by content of this disclosure.Specifically, it is all to be used in specification and claim
The numeral of the middle content for representing composition, reaction condition etc., it is thus understood that be that the term for being subject to " about " is repaiied in all situations
Decorations.Under normal circumstances, the implication of its expression refers to include by specific quantity ± 10% change in certain embodiments, at some
± 5% change in embodiment, ± 1% change in certain embodiments, in certain embodiments ± 0.5% change.
Furthermore word "comprising" or " comprising " do not exclude the presence of element or step not listed in the claims.Positioned at member
Word "a" or "an" before part does not exclude the presence of multiple such elements.Specification and the sequence used in claim
The word of numerical example such as " first ", " second ", " the 3rd ", to modify corresponding element, itself is not meant to that the element has
Any ordinal number, does not represent a certain element and the order in the order or manufacture method of another element yet, those ordinal numbers make
With only be used for enable with certain name an element be able to make clear differentiation with another element with identical name.
Particular embodiments described above, has carried out further in detail the purpose, technical solution and beneficial effect of the disclosure
Describe in detail bright, it should be understood that the foregoing is merely the specific embodiment of the disclosure, be not limited to the disclosure, it is all
Within the spirit and principle of the disclosure, any modification, equivalent substitution, improvement and etc. done should be included in the guarantor of the disclosure
Within the scope of shield.
Claims (10)
1. a kind of production method of semiconductor CMOS device, including：
A part of the N-type MOSFET separated by shallow channel isolation area and p-type MOSFET are formed on substrate, including：It is located at
Source/drain region in substrate, on substrate false gate stack of the orientation between source/drain region and the gate electrode side around false gate stack
Wall；
Removing false gate stack in N-type MOSFET and p-type MOSFET, to form respective gate openings on the inside of grid curb wall, makes lining
Expose on the surface at bottom；
Sequentially formed at N-type MOSFET and the respective gate openings of p-type MOSFET interfacial oxide layer, high-K gate dielectric layer and
First Metal gate layer；
One in N-type MOSFET and p-type MOSFET is sheltered respectively, isotropic plasma is utilized to another
Doped ions in the first Metal gate layer are entrained in, and control the energy of plasma so that Doped ions are only distributed only over first
In Metal gate layer, and according to the dosage of desired threshold voltage control ion implanting；
The second Metal gate layer is formed to fill gate openings on the first Metal gate layer after doping；And
Carrying out annealing spreads Doped ions and accumulates in the upper interface between high-K gate dielectric layer and the first Metal gate layer
And the lower interface between high-K gate dielectric layer and interfacial oxide layer, and interface, lower interface pass through interface on this
Reaction is respectively formed electric dipole.
2. production method according to claim 1, wherein, the energy of the plasma doping is between 0.1keV-20keV
Between.
3. production method according to claim 1, wherein, the dosage of the ion implanting is between 1E13-5E15cm-2It
Between.
4. production method according to claim 1, wherein：
The Doped ions of the N-type MOSFET are N type dopant, which is that can reduce the doping of effective work function
Agent；
The Doped ions of the p-type MOSFET are P-type dopant, which is that can increase the doping of effective work function
Agent.
5. production method according to claim 4, wherein：
The N type dopant includes：Phosphorus and hydride of arsenic, fluoride, are one kind in following material or its combination：Phosphine,
Arsine, phosphorus pentafluoride, phosphorus trifluoride, arsenic pentafluoride or arsenic trifluoride；And/or
The P-type dopant includes：Hydride, fluoride or the chloride of boron, are one kind in following material or its combination：
B2H6、B4H10、B6H10、B10H14、B18H22、BF3Or BCl3。
6. production method according to claim 1, wherein：
The material of the high-K gate dielectric layer is one kind of following material or its combination：ZrO2、ZrON、ZrSiON、HfZrO、
HfZrON、HfON、HfO2, HfAlO, HfAlON, HfSiO, HfSiON, HfLaO or HfLaON；And/or
The material of first Metal gate layer is one kind or its combination in following material：TiN, TaN, MoN, WN, TaC or
TaCN；And/or
Second Metal gate layer includes multiple layer metal material, wherein the metal material against the first Metal gate layer selects oxygen uptake
The good metal of energy, including：At least one of Ti, TiAl, Ta；Followed by potential barrier barrier metal, including：TiN, TaN, Ta,
One or both of MoN, AlN or WN；It is finally filling metal, including：One or both of W, Al, TiAl or Mo.
7. production method according to claim 1, wherein：
The thickness of the high-K gate dielectric layer is between 1.5nm-5nm；And/or
The thickness of first Metal gate layer is between 1nm-10nm.
8. production method according to claim 1, wherein, the condition for carrying out annealing and spreading Doped ions
For：Annealing temperature is 350 DEG C -450 DEG C, annealing time 20min-90min.
9. production method according to claim 1, wherein, a part of the N-type MOSFET and p-type MOSFET are also wrapped
Include：Silicification area, is formed at the surface of respective source/drain region；And interlayer dielectric layer, be covered in respective source/drain region top,
Around grid curb wall outer surface and false gate stack top；The vacation gate stack includes：False gate medium and false grid conductor, and
Utilize the surface of chemically mechanical polishing planarization interlayer dielectric layer and the top surface of the false grid conductor of exposure.
10. according to claim 1 to 9 any one of them production method, wherein, after high-K gate dielectric layer is formed, formed
Following steps are further included before first Metal gate layer：Made annealing treatment after the making of high-K gate dielectric layer is completed, to improve height
The quality of K gate dielectric layers.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109817585A (en) * | 2019-03-18 | 2019-05-28 | 上海新微技术研发中心有限公司 | Metal oxide semiconductor device and method for manufacturing the same |
| CN111554679A (en) * | 2020-04-09 | 2020-08-18 | 中国科学院微电子研究所 | SOI FinFET device and manufacturing method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101930913A (en) * | 2009-06-26 | 2010-12-29 | 中芯国际集成电路制造(上海)有限公司 | Generating method of metal gate electrode |
| CN103855006A (en) * | 2012-11-30 | 2014-06-11 | 中国科学院微电子研究所 | Manufacturing method of semiconductor device |
| CN106298527A (en) * | 2015-06-01 | 2017-01-04 | 中芯国际集成电路制造(上海)有限公司 | Pmos transistor and forming method thereof |
-
2017
- 2017-11-09 CN CN201711110992.3A patent/CN107910298A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101930913A (en) * | 2009-06-26 | 2010-12-29 | 中芯国际集成电路制造(上海)有限公司 | Generating method of metal gate electrode |
| CN103855006A (en) * | 2012-11-30 | 2014-06-11 | 中国科学院微电子研究所 | Manufacturing method of semiconductor device |
| CN106298527A (en) * | 2015-06-01 | 2017-01-04 | 中芯国际集成电路制造(上海)有限公司 | Pmos transistor and forming method thereof |
Non-Patent Citations (1)
| Title |
|---|
| 刘爱国: "《低温等离子体表面强化技术》", 30 September 2015, 哈尔冰工业出版社 * |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109817585A (en) * | 2019-03-18 | 2019-05-28 | 上海新微技术研发中心有限公司 | Metal oxide semiconductor device and method for manufacturing the same |
| CN111554679A (en) * | 2020-04-09 | 2020-08-18 | 中国科学院微电子研究所 | SOI FinFET device and manufacturing method thereof |
| CN111554679B (en) * | 2020-04-09 | 2023-03-31 | 中国科学院微电子研究所 | SOI FinFET device and manufacturing method thereof |
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