CN105097555B - Finfet and manufacturing method thereof - Google Patents

Finfet and manufacturing method thereof Download PDF

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CN105097555B
CN105097555B CN201510574924.7A CN201510574924A CN105097555B CN 105097555 B CN105097555 B CN 105097555B CN 201510574924 A CN201510574924 A CN 201510574924A CN 105097555 B CN105097555 B CN 105097555B
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layer
ridge
grid
doping
semiconductor fin
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CN105097555A (en
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朱慧珑
许淼
梁擎擎
尹海洲
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/66803—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
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    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7856—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with an non-uniform gate, e.g. varying doping structure, shape or composition on different sides of the fin, or different gate insulator thickness or composition on opposing fin sides

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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)

Abstract

A FinFET and a method of manufacturing the same are disclosed. The method of fabricating a FinFET includes: forming a doped punch-through blocking layer inside the semiconductor substrate; forming a semiconductor fin by utilizing the part of the semiconductor substrate, which is positioned above the doped punch-through stopping layer; forming a gate stack across the semiconductor fin, the gate stack including a gate dielectric and a gate conductor, and the gate dielectric separating the gate conductor and the semiconductor fin; forming a gate spacer surrounding the gate conductor; and forming a source region and a drain region in portions of the semiconductor fin on both sides of the gate stack. The doped punch-through prevention layer separates the semiconductor fin from the semiconductor substrate, so that a leakage current path between the source region and the drain region through the semiconductor substrate can be disconnected.

Description

FinFET and its manufacture method
The application is sending out for entitled " FinFET and its manufacture method " that on November 30th, 2012 is submitted to Patent Office of the People's Republic of China The divisional application of bright patent application No.201210507134.3.
Technical field
The present invention relates to semiconductor technology, more particularly, to FinFET and preparation method thereof.
Background technology
As the size of semiconductor device is less and less, short-channel effect is further obvious.In order to suppress short-channel effect, carry The FinFET formed in SOI wafer or bulk semiconductor substrate is gone out.FinFET is included in the fin (fin) of semi-conducting material Intermediate formation channel region, and fin two ends formed source/drain region.Gate electrode surrounds ditch in two sides of channel region Road area (i.e. double-gate structure), so as to form inversion layer on each side of raceway groove.As whole channel region can be controlled by grid, Therefore, it is possible to play a part of to suppress short-channel effect.
In batch production, compared with using SOI wafer, using Semiconductor substrate manufacture FinFET cost efficiencys more Height, so as to widely used.However, the height of semiconductor fin is difficult to control in the FinFET using Semiconductor substrate, and The conductive path via Semiconductor substrate is likely to form between source region and drain region, so as to produce the problem of leakage current.
In semiconductor fin doping break-through trapping layer (punch-through-stopper layer) formed below, can be with Reduce the leakage current between source region and drain region.However, the ion implanting performed to form break-through trapping layer partly may led Undesirable dopant is introduced in the channel region of body fin.The additional doping cause to exist in the channel region of FinFET with Machine doping content fluctuates.
Due to the height change and random doping fluctuation of concentration of semiconductor fin, the threshold voltage of FinFET is undesirably sent out Raw change at random.
The content of the invention
The purpose of the present invention is to reduce the leakage current between source region and drain region in the FinFET based on Semiconductor substrate, and And reduce the change at random of threshold voltage.
According to an aspect of the present invention, there is provided a kind of method of manufacture FinFET, including：In the inside shape of Semiconductor substrate Into doping break-through trapping layer；The part above doping break-through trapping layer is located at using Semiconductor substrate and forms semiconductor fin；Shape Stack into the grid across semiconductor fin, grid stacking includes gate-dielectric and grid conductor, and gate-dielectric is by grid Pole conductor and semiconductor fin separate；Form the grid curb wall around grid conductor；And stack positioned at grid in semiconductor fin Source region and drain region are formed in the part of both sides.
According to a further aspect in the invention, there is provided a kind of FinFET, including：Semiconductor substrate；In Semiconductor substrate Doping break-through trapping layer；Semiconductor fin on doping break-through trapping layer；Grid across semiconductor fin are stacked, the grid Stacking includes gate-dielectric and grid conductor, and grid conductor and semiconductor fin are separated by gate-dielectric；And position In source region and the drain region at semiconductor fin two ends, wherein doping break-through trapping layer and semiconductor fin are by Semiconductor substrate shape Into.
In the FinFET of the present invention, semiconductor fin and Semiconductor substrate are separated using doping break-through trapping layer, from And the drain current path between source region and drain region via Semiconductor substrate can be disconnected.During the FinFET is formed, can To avoid the undesirable doping to semiconductor fin using top protection layer and/or side wall protective layer, such that it is able to reduce threshold The change at random of threshold voltage.In a preferred embodiment, the source region for being formed in stress layer and drain region can be to half Channel region in conductor fin applies suitable stress to provide the mobility of carrier.In another or further preferred reality Apply in example, grid stacking is formed using rear grid technique, so as to obtain high-quality gate-dielectric and desired work function.
Description of the drawings
By description referring to the drawings to the embodiment of the present invention, the above-mentioned and other purposes of the present invention, feature and Advantage will be apparent from, in the accompanying drawings：
Fig. 1-11 shows each stage of the method for the manufacture semiconductor device of first embodiment of the invention Semiconductor structure schematic diagram.
Figure 12-13 shows a part of stage of the method for manufacture semiconductor device according to the second embodiment of the present invention Semiconductor structure schematic diagram.
Figure 14-16 shows a part of stage of the method for manufacture semiconductor device according to the third embodiment of the invention Semiconductor structure schematic diagram.
Figure 17-20 shows a part of stage of the method for manufacture semiconductor device according to the fourth embodiment of the invention Semiconductor structure schematic diagram.
Figure 21-22 shows a part of stage of the method for manufacture semiconductor device according to the fifth embodiment of the invention Semiconductor structure schematic diagram.
Figure 23 shows a part of stage of the method for manufacture semiconductor device according to the sixth embodiment of the invention The schematic diagram of semiconductor structure.
Specific embodiment
The present invention is more fully described hereinafter with reference to accompanying drawing.In various figures, identical element is attached using what is be similar to Icon is remembered to represent.For the sake of clarity, the various pieces in accompanying drawing are not necessarily to scale.
For brevity, the semiconductor structure that can be obtained after several steps described in a width figure.
It should be appreciated that in the structure of outlines device, when by a floor, a region referred to as positioned at another floor, another area When domain " above " or " top ", can refer to above another layer, another region, or its with another layer, it is another Other layers or region are included between individual region also.Also, if device is overturn, this layer, a region will be positioned at another Layer, another region " below " or " lower section ".
If in order to describe located immediately at another layer, another region above scenario, herein will be using " directly ... above " or " ... adjoin above and therewith " form of presentation.
In this application, term " semiconductor structure " refers to whole half formed in each step of manufacture semiconductor device The general designation of conductor structure, including all layers or region that have been formed.Describe hereinafter many specific thin of the present invention Section, the structure of such as device, material, size, handling process and technology, to be more clearly understood that the present invention.But as ability The technical staff in domain it will be appreciated that as, the present invention can not be realized according to these specific details.
Unless hereinafter particularly pointed out, the various pieces of FinFET can be by material well known to those skilled in the art Constitute.Semi-conducting material for example includes Group III-V semiconductor, such as GaAs, InP, GaN, SiC, and IV races quasiconductor, such as Si, Ge.Grid conductor can be formed by conductive various materials are capable of, such as metal level, doped polysilicon layer or including metal level With the stacked gate conductor or other conductive materials of doped polysilicon layer, for example, TaC, TiN, TaTbN, TaErN, TaYbN, TaSiN, HfSiN, MoSiN, RuTax, NiTax, MoNx, TiSiN, TiCN, TaAlC, TiAlN, TaN, PtSix, Ni3The combination of Si, Pt, Ru, Ir, Mo, HfRu, RuOx and the various conductive materials.Gate-dielectric can be by SiO2Or dielectric Constant is more than SiO2Material constitute, such as including oxide, nitride, oxynitride, silicate, aluminate, titanate, its In, oxide for example includes SiO2、HfO2、ZrO2、Al2O3、TiO2、La2O3, nitride is for example including Si3N4, silicate is for example Including HfSiOx, aluminate for example includes LaAlO3, titanate is for example including SrTiO3, oxynitride is for example including SiON.And And, gate-dielectric not only can be formed by material well known to those skilled in the art, it would however also be possible to employ the use developed in the future In the material of gate-dielectric.
The present invention can be presented in a variety of manners, some of them example explained below.
Reference picture 1-11 describes the example flow of the method for the manufacture semiconductor device of first embodiment of the invention, Wherein, the interception position of the top view and sectional view of semiconductor structure is shown in Figure 10 a-11a, in Fig. 1-9,10b-11b In illustrate semiconductor fin width ascender line A-A intercept semiconductor structure sectional view, show in Figure 10 c-11c Go out semiconductor fin A length directions ascender line B-B intercept semiconductor structure sectional view.
As shown in figure 1, by known depositing operation, such as electron beam evaporation (EBM), chemical vapor deposition (CVD), atom Layer deposition (ALD), sputtering etc., form top protection layer 102 in Semiconductor substrate 101 (such as Si substrates) and (for example, nitrogenize Silicon).In one example, top protection layer 102 is, for example, the silicon nitride layer that thickness is about 50-100nm.As will hereafter retouch State, semiconductor fin will be formed in Semiconductor substrate 101.
Then, for example by being spin-coated on top protection layer 102 formation photoresist layer PR1, and by including Exposed and developed photoetching process forms photoresist layer PR1 for limiting the shape (for example, band) of semiconductor fin Pattern.
Using photoresist layer PR1 as mask, by dry etching, such as ion beam milling etching, plasma etching, reaction Ion(ic) etching, laser ablation, or by using the wet etching of etchant solutions, remove the exposed portion of top protection layer 102 Point, and Semiconductor substrate 101 is further etched to predetermined depth, as shown in Figure 2.By the time for controlling etching, can be with Etch depth in control Semiconductor substrate 101, so as to opening is formed in Semiconductor substrate 101, and limits between opening Determine ridge.Top protection layer 102 is located on the top surface of ridge.
Then, by dissolving in a solvent or being ashed removal photoresist layer PR1.By above-mentioned known deposition work Skill, forms the first insulating barrier 103 (for example, silicon oxide), on the surface of semiconductor structure with filling semiconductor substrate 101 Opening.In one example, made using suitable depositing operation (such as high density plasma CVD HDP-CVD) Obtain thickness of first insulating barrier 103 in the part in opening the part on top protection layer 102 is located at more than the first insulating barrier 103 Thickness.In another example, the first insulating barrier 103 is located at the thickness of the part on top protection layer 102 may be too big, can With the surface by the additional smooth semiconductor structure of chemically mechanical polishing (CMP), so as to reduce the thickness of the part, or with Top protection layer 102 removes the part completely as stop-layer.
Using top protection layer 102 as hard mask, by selective etch process (for example, reactive ion etching), The first insulating barrier of etch-back 103, as shown in Figure 3.The etching not only removes the first insulating barrier 103 and is located on top protection layer 102 Part, and reduce the thickness of the part that the first insulating barrier 103 is located in opening.The time of control etching so that first is exhausted Edge layer 103 is located at the part in opening and is used as sealing coat, and limits the depth of opening.The top of the opening exposure ridge Side, and the depth being open should be substantially equal to the height of the semiconductor fin that will be formed.
Then, by above-mentioned known depositing operation, conformal nitride layer (example is formed on the surface of semiconductor structure Such as, silicon nitride).In one example, the thickness of the nitride layer is about 10-20nm.
By anisotropic etch process (for example, reactive ion etching), nitride layer is removed in the first insulating barrier 103 Exposed surface on the part that extends laterally so that nitride layer is located at the vertical component on the side of ridge and retains, so as to Side wall protective layer 104 is formed, as shown in Figure 4.As a result, top protection layer 102, the top of ridge are coated with the top of ridge Side be coated with side wall protective layer 104, the side of the bottom of ridge is adjoined with the first insulating barrier 103.
Then, using top protection layer 102 and side wall protective layer 104 as hard mask, by selective etch process (for example, reactive ion etching), the first insulating barrier of etch-back 103, as shown in Figure 5.The etching reduces the first insulating barrier 103 Thickness, and expose a part for the side of the bottom of ridge.The time of control etching so that the exposure of the bottom of ridge The height h (i.e. the reduction amount of the thickness of the first insulating barrier 103) of side is predetermined value.
Then, conformal doping is formed on the surface of a semiconductor substrate using conformal doping (conformal doping) Oxidant layer 105, as shown in Figure 6.Dopant layer 105 includes top protection layer 102, side wall protective layer 104, first insulating barrier 103 The surface layer comprising dopant in the exposed side of the bottom of surface and ridge.
Different dopants can be adopted for different types of FinFET.Can be adulterated using p-type in N-type FinFET Agent, such as B, can use N type dopant, such as P, As in p-type FinFET.Dopant layer 105 will be used for forming doping wears Logical trapping layer so that the doping type and source region of break-through trapping layer and the doping type in drain region are conversely, such that it is able to disconnect source region Drain current path and drain region between.
Then, by above-mentioned known depositing operation, 106 (example of the second insulating barrier is formed on the surface of semiconductor structure Such as, silicon oxide).Using top protection layer 102 and side wall protective layer 104 as hard mask, by selective etch process (example Such as, reactive ion etching), the second insulating barrier of etch-back 106, as shown in Figure 7.The etching reduces the thickness of the second insulating barrier 106 Degree.The time of control etching so that the top surface of the second insulating barrier 106 is at least above the bottom of side wall protective layer 104, so as to Second insulating barrier 106 at least covers part of the dopant layer 105 on the side of ridge.
Then, by selective etch process (for example, reactive ion etching), relative to the second insulating barrier 106, remove Top protection layer 102 and side wall protective layer 104, as shown in Figure 8.The etching also removes dopant layer 105 and protects positioned at top Part on the surface of layer 102 and side wall protective layer 104.
Then, using thermal annealing, the part that dopant layer 105 is located on the side of ridge is pushed home into until even It is logical, so as to doping break-through trapping layer 107 is formed in the ridge of Semiconductor substrate 101, as shown in Figure 9.The ridge is located at Part on doping break-through trapping layer 107 forms semiconductor fin 108.Also, semiconductor fin 108 and Semiconductor substrate Separated by doping break-through trapping layer 107 between 101.Due on the width of ridge, the dopant that thermal annealing is pushed from Two lateral middle diffusions, therefore the break-through trapping layer 107 that adulterates has the doping content point of the width along semiconductor fin Cloth so that doping content of the doping content of 107 mid portion of doping break-through trapping layer less than two end portions.
Then, by above-mentioned known depositing operation, 109 (example of gate-dielectric is formed on the surface of semiconductor structure Such as, silicon oxide or silicon nitride).In one example, the gate-dielectric 109 is for about the thick silicon oxide layers of 0.8-1.5nm.Grid Electrolyte 109 covers the top surface of semiconductor fin 108 and side.
By above-mentioned known depositing operation, conductor layer (for example, doped polycrystalline is formed on the surface of semiconductor structure Silicon).It is possible if desired to (CMP) is chemically-mechanicapolish polished to conductor layer, to obtain even curface.
Using photoresist mask, the conductor layer is patterned as into the grid conductor 110 across semiconductor fin, and The expose portion of gate-dielectric 109 is removed further, as shown in Figure 10 a, 10b and 10c.Grid conductor 110 and grid electricity are situated between Matter 109 forms grid stacking together.In the example shown in Figure 10 a, 10b and 10c, grid conductor 110 is shaped as band, and Extend along the direction vertical with the length of semiconductor fin.
Then, by above-mentioned known depositing operation, nitride layer is formed on the surface of semiconductor structure.Show at one In example, silicon nitride layer of the nitride layer for thickness about 5-20nm.By anisotropic etch process (for example, reactive ion Etching), remove the part for extending laterally of nitride layer so that nitride layer is located at vertical on the side of grid conductor 110 Part retains, so as to form grid curb wall 111.Generally, due to form factor, the nitride layer on 108 side of semiconductor fin Thickness is less than the nitride layer thickness on the side of grid conductor 110, partly leads so as to remove completely in the etching step Nitride layer on 108 side of body fin.Otherwise, the nitride layer thickness on 108 side of semiconductor fin may interfere with greatly very much Form grid curb wall.Additional mask can be adopted further to remove the nitride layer on 108 side of semiconductor fin.
The etching exposure semiconductor fin 108 is located at the top surface of the part of 110 both sides of grid conductor and side.So Afterwards, source region and drain region can be formed in the expose portion of semiconductor fin 103 according to conventional technique.
A part of rank of the method for reference picture 12-13 description manufacture semiconductor device according to the second embodiment of the present invention The example flow of section, there is shown with the sectional view of the semiconductor structure intercepted on the width of semiconductor fin.
According to second embodiment, following steps are performed after the step shown in Fig. 5.
(gas phase drive-in) is pushed by gas phase so that dopant from the exposed side of the bottom of ridge to Diffusion inside until connection, so as to doping break-through trapping layer 107 is formed in the ridge of Semiconductor substrate 101, such as Figure 12 institutes Show.The ridge is located at the part on doping break-through trapping layer 107 and forms semiconductor fin 108.Also, semiconductor fin Separated by doping break-through trapping layer 107 between 108 and Semiconductor substrate 101.As, on the width of ridge, gas phase is pushed away The dopant for entering is spread from two lateral centres, therefore, doping break-through trapping layer 107 has the width along semiconductor fin Doping concentration distribution so that doping content of the doping content of 107 mid portion of doping break-through trapping layer less than two end portions.
In gas phase is pushed, different dopants can be adopted for different types of FinFET.Can in N-type FinFET To use P-type dopant, such as B that N type dopant, such as P, As can be used in p-type FinFET.Doping break-through trapping layer The doping type in 107 doping type and source region and drain region is conversely, such that it is able to disconnect the electric leakage stream between source region and drain region Footpath.
Then, by above-mentioned known depositing operation, 106 (example of the second insulating barrier is formed on the surface of semiconductor structure Such as, silicon oxide).Using top protection layer 102 and side wall protective layer 104 as hard mask, by selective etch process (example Such as, reactive ion etching), the second insulating barrier of etch-back 106.The etching reduces the thickness of the second insulating barrier 106.Control etching Time so that the top surface of the second insulating barrier 106 at least above adulterate break-through trapping layer 107 and Semiconductor substrate 101 it Between interface.
Then, by selective etch process (for example, reactive ion etching), relative to the second insulating barrier 106, remove Top protection layer 102 and side wall protective layer 104, as shown in figure 13.
Then, continue the step shown in Figure 10 and 11 to form grid stacking, grid curb wall, source region and drain region.
A part of rank of the method for reference picture 14-16 description manufacture semiconductor device according to the third embodiment of the invention The example flow of section, there is shown with the sectional view of the semiconductor structure intercepted on the width of semiconductor fin.
According to 3rd embodiment, following steps are performed after the step shown in Fig. 5.
Then, injected by angle-tilt ion, in ridge as hard mask using top protection layer 102 and side wall protective layer 104 Dopant layer 105 is formed in the exposed side of the bottom of shape thing, as shown in figure 14.The parameter of control ion implanting so that doping Agent does not pass through top protection layer 102 and side wall protective layer 104 and enters in the other parts of ridge.In fig. 14 ion is noted Entering to be described as in two directions (as shown by arrows) is carried out.It should be appreciated that the ion implanting can be included in the first step Ion implanting is carried out in the first direction, carries out ion implanting in the second step in a second direction.
In ion implanting, different dopants can be adopted for different types of FinFET.Can in N-type FinFET To use P-type dopant, such as B that N type dopant, such as P, As can be used in p-type FinFET.Dopant layer 105 will be used In forming doping break-through trapping layer so that the doping type in the doping type of break-through trapping layer and source region and drain region conversely, so as to The drain current path between source region and drain region can be disconnected.
Then, by above-mentioned known depositing operation, 106 (example of the second insulating barrier is formed on the surface of semiconductor structure Such as, silicon oxide).Using top protection layer 102 and side wall protective layer 104 as hard mask, by selective etch process (example Such as, reactive ion etching), the second insulating barrier of etch-back 106, as shown in figure 15.The etching reduces the thickness of the second insulating barrier 106 Degree.The time of control etching so that the top surface of the second insulating barrier 106 is at least above the bottom of side wall protective layer 104, so as to Second insulating barrier 106 at least covers dopant layer 105.
Then, by selective etch process (for example, reactive ion etching), relative to the second insulating barrier 106, remove Top protection layer 102 and side wall protective layer 104.Using thermal annealing, dopant layer 105 is located at into the part on the side of ridge It is pushed home into up to connection, so as to doping break-through trapping layer 107 is formed in the ridge of Semiconductor substrate 101, such as Figure 16 institutes Show.The ridge is located at the part on doping break-through trapping layer 107 and forms semiconductor fin 108.Also, semiconductor fin Separated by doping break-through trapping layer 107 between 108 and Semiconductor substrate 101.As, on the width of ridge, gas phase is pushed away The dopant for entering is from two lateral middle diffusions, therefore the break-through trapping layer 107 that adulterates has the width along semiconductor fin Doping concentration distribution so that doping content of the doping content of 107 mid portion of doping break-through trapping layer less than two end portions.
Then, continue the step shown in Figure 10 and 11 to form grid stacking, grid curb wall, source region and drain region.
A part of rank of the method for reference picture 17-20 description manufacture semiconductor device according to the fourth embodiment of the invention The example flow of section, there is shown with the sectional view of the semiconductor structure intercepted on the width of semiconductor fin.
As shown in figure 17, the desired depth by ion implanting in Semiconductor substrate 101 (such as Si substrates) is formed and is mixed Miscellaneous area, so as to form doping break-through trapping layer 107.Semiconductor substrate 101 is located at the part on doping break-through trapping layer 107 will Form semiconductor layer 108 '.Also, separated by doping break-through trapping layer 107 between semiconductor layer 108 ' and Semiconductor substrate 101. Doping break-through trapping layer 107 has the doping concentration distribution of the width along semiconductor fin so that doping break-through is prevented Doping content of the doping content of 107 mid portion of layer less than two end portions.
In ion implanting, different dopants can be adopted for different types of FinFET.Can in N-type FinFET To use P-type dopant, such as B that N type dopant, such as P, As can be used in p-type FinFET.Doping break-through trapping layer The doping type in 107 doping type and source region and drain region is conversely, such that it is able to disconnect the electric leakage stream between source region and drain region Footpath.
By above-mentioned known depositing operation, top protection layer 102 is formed on semiconductor layer 108 ' and (for example, is nitrogenized Silicon), as shown in figure 17.
Then, for example by being spin-coated on top protection layer 102 formation photoresist layer PR1, and by including Exposed and developed photoetching process forms photoresist layer PR1 for limiting the shape (for example, band) of semiconductor fin Pattern.
Using photoresist layer PR1 as mask, by dry etching, such as ion beam milling etching, plasma etching, reaction Ion(ic) etching, laser ablation, or by using the wet etching of etchant solutions, remove from top to bottom top protection layer 102, The expose portion of semiconductor layer 108 ', doping break-through trapping layer 107, and Semiconductor substrate 101 can be further etched to pre- Fixed depth, as shown in figure 18.By the time for controlling etching, the etch depth in Semiconductor substrate 101 can be controlled, so as to Opening is formed in Semiconductor substrate 101.Part of the semiconductor layer 108 ' between opening retains to form semiconductor fin 108.Top protection layer 102 is located on the surface of semiconductor fin 108.
Then, by dissolving in a solvent or being ashed removal photoresist layer PR1.By above-mentioned known deposition work Skill, forms the first insulating barrier 103 (for example, silicon oxide), on the surface of semiconductor structure with filling semiconductor substrate 101 Opening.In one example, made using suitable depositing operation (such as high density plasma CVD HDP-CVD) Obtain thickness of first insulating barrier 103 in the part in opening the part on top protection layer 102 is located at more than the first insulating barrier 103 Thickness.In another example, the first insulating barrier 103 is located at the thickness of the part on top protection layer 102 may be too big, can With the surface by the additional smooth semiconductor structure of chemically mechanical polishing (CMP), so as to reduce the thickness of the part, or with Top protection layer 102 removes the part completely as stop-layer.
Using top protection layer 102 as hard mask, by selective etch process (for example, reactive ion etching), The first insulating barrier of etch-back 103.The etching reduces the thickness of the first insulating barrier 103.The time of control etching so that first is exhausted The interface that the top surface of edge layer 103 at least above adulterates between break-through trapping layer 107 and Semiconductor substrate 101.
Then, by selective etch process (for example, reactive ion etching), relative to the first insulating barrier 103, remove Top protection layer 102, as shown in figure 20.
Then, continue the step shown in Figure 10 and 11 to form grid stacking, grid curb wall, source region and drain region.It should be noted that Side wall protective layer 104 and the second insulating barrier 106 need not be formed in this embodiment.
A part of rank of the method for reference picture 21-22 description manufacture semiconductor device according to the fifth embodiment of the invention The example flow of section, wherein, the interception position of the top view and sectional view of semiconductor structure is shown in Figure 21 a-22a, The sectional view of the semiconductor structure that width ascender line A-A in semiconductor fin is intercepted is shown, in figure in Figure 21 b-22b The sectional view of the semiconductor structure that A length directions ascender line B-B in semiconductor fin is intercepted is shown in 21c-22c.
According to the preferred embodiment, the step shown in Figure 21 and 22 is further performed after the step shown in Figure 11 with shape Into stress layer, and source region and drain region are formed in stress layer.
By above-mentioned known etch process (for example, reactive ion etching), optionally go relative to grid curb wall 111 Except semiconductor fin 108 is located at the part of 110 both sides of grid conductor, as shown in Figure 21 a, 21b and 21c.The etching can mixed The top surface of miscellaneous break-through trapping layer 107 stops, or further removes a part for doping break-through trapping layer 107 (such as Figure 21 c It is shown).The etching is also possible to the part for removing grid conductor 110.As the thickness of grid conductor 110 can compare semiconductor fin Piece 108 it is highly much larger, therefore, the etching only only reduces the thickness of grid conductor 110, without completely remove grid lead Body 110 (as shown in Figure 21 c).
Then, by above-mentioned known depositing operation, in 107 Epitaxial growth stress layer of doping break-through trapping layer 112, as shown in Figure 22 a, 22b and 22c.Stress layer 112 is also formed on grid conductor 110.The stress layer 112 Thickness should be sufficiently large so that top surface of the top surface of stress layer 112 greater than or equal to semiconductor fin 108, To maximize the stress applied in semiconductor fin 108.
Different stress layers 112 can be formed for different types of FinFET.By stress layer to The channel region of FinFET applies suitable stress, can improve the mobility of carrier, so as to reducing conducting resistance and improving device The switching speed of part.For this purpose, source region and drain region are formed using the semi-conducting material different from the material of semiconductor fin 108, can To produce desired stress.The content of the C e.g. formed on a si substrate for N-type FinFET, stress layer 112 is about The Si of atomic percent 0.2-2%：C layers, the longitudinal direction along channel region apply tension to channel region.For p-type The content of FinFET, the Ge that stress layer 112 is e.g. formed on a si substrate is about the SiGe of atomic percent 15-75% Layer, the longitudinal direction along channel region apply compressive stress to channel region.
With reference to a part of stage of the method for Figure 23 descriptions manufacture semiconductor device according to the sixth embodiment of the invention Example flow, wherein, the interception position of the top view and sectional view of semiconductor structure is shown in Figure 23 a, in Figure 23 b The sectional view of the semiconductor structure that width ascender line A-A in semiconductor fin is intercepted is shown, is illustrated in Figure 23 c half The sectional view of the semiconductor structure that A length directions ascender line B-B of conductor fin is intercepted.
According to the preferred embodiment, the step shown in Figure 23 is further performed after the step shown in Figure 22 to form bag Include replacement gate conductor and substitute the alternative gate stacking of gate medium.
By above-mentioned known depositing operation, 113 (for example, oxygen of the 3rd insulating barrier is formed on the surface of semiconductor structure SiClx).Semiconductor structure is chemically-mechanicapolish polished, to obtain even curface.The chemically mechanical polishing eliminates the 3rd Insulating barrier 113 is located at the part above grid conductor 110, so as to expose the stress layer 112 above grid conductor 110 With grid curb wall 111.Further, the chemically mechanical polishing can remove of stress layer 112 and grid curb wall 111 Point.
Using the 3rd insulating barrier 113 and grid curb wall 111 as hard mask, by above-mentioned known etch process (for example Reactive ion etching) remove grid conductor 110 above stress layer 112, and further remove grid conductor 110, So as to form gate openings.It is alternatively possible to further remove the part that gate-dielectric 107 is located at gate openings bottom.Press According to rear grid technique, 114 (for example, HfO of replacement gate electrolyte is formed in gate openings2) and 115 (example of replacement gate conductor Such as, TiN), as shown in Figure 23 a, 23b and 23c.Replacement gate conductor 115 and replacement gate electrolyte 114 form alternative gate together Stacking.
According to each above-mentioned embodiment, after source region and drain region is formed, can be on resulting semiconductor structure Interlayer insulating film, the through hole in interlayer insulating film, the wiring positioned at interlayer insulating film upper surface or electrode are formed, so as to complete Into the other parts of FinFET.
The ins and outs such as composition in the above description, for each layer, etching are described in detail.But It will be appreciated by those skilled in the art that layer, region of required form etc. can be formed by various technological means.In addition, being Formation same structure, those skilled in the art can be devised by and process as described above not fully identical method. Although in addition, each embodiment is respectively described more than, but it is not intended that the measure in each embodiment can not be favourable Be used in combination.
Above embodiments of the invention are described.But, the purpose that these embodiments are merely to illustrate that, and It is not intended to limit the scope of the present invention.The scope of the present invention is limited by claims and its equivalent.Without departing from this Bright scope, those skilled in the art can make various alternatives and modifications, and these alternatives and modifications should all fall the present invention's Within the scope of.

Claims (14)

1. a kind of method of manufacture FinFET, including：
Ridge is formed on a semiconductor substrate, by the situation of the part for being used to form semiconductor fin in the ridge is blocked Under, dopant is pushed by gas phase via the exposed side of the non-shield portions of ridge or angle-tilt ion injection dopant is right After carry out heat treatment with formed doping break-through trapping layer；
The part above doping break-through trapping layer is located at using ridge and forms semiconductor fin；
The grid stacking of semiconductor fin is developed across, the grid stacking includes gate-dielectric and grid conductor, and grid electricity is situated between Grid conductor and semiconductor fin are separated by matter；
Form the grid curb wall around grid conductor；And
Source region and drain region are formed in semiconductor fin is located at the part that grid stack both sides.
2. method according to claim 1, wherein the part that will be used for being formed semiconductor fin for blocking ridge includes： Block the top of ridge and the top of side wall.
3. method according to claim 2, wherein, the method for forming ridge includes：Top is formed on a semiconductor substrate Portion's protective layer, then patterned semiconductor substrate is forming ridge；
Before doping break-through trapping layer is formed, the method also includes：Wall protection in side is formed on the side on the top of ridge Layer；
After doping break-through trapping layer is formed, the method also includes：Remove top protection layer and side wall protective layer.
4. method according to claim 3, wherein including the step of doping：
Pushed by gas phase so that dopant is internally spread up to connection, so as to be formed from the exposed side of the bottom of ridge Doping break-through trapping layer.
5. method according to claim 1, wherein
The step of angle-tilt ion is injected includes：The exposed side that the non-shield portions of ridge are infused in by angle-tilt ion is formed Dopant layer, and
The step of heat treatment, includes：Dopant is pushed home into ridge from dopant layer to form doping break-through trapping layer.
6. method according to claim 3, wherein the step of ridge is formed and the step of forming side wall protective layer it Between also include：
First insulating barrier is formed by high density plasma CVD；And
The first insulating barrier of etch-back is exposing the side on the top of ridge.
7. method according to claim 6, wherein also wrapping between the step of side wall protective layer is formed and the step of doping Include：
Further the first insulating barrier of etch-back is providing the exposed side of the bottom of ridge.
8. method according to any one of claim 1 to 7, wherein the FinFET is N-type, and is hindering to break-through P-type dopant used in the step of only layer adulterates.
9. method according to any one of claim 1 to 7, wherein the FinFET is p-type, and is hindering to break-through N type dopant used in the step of only layer adulterates.
10. method according to any one of claim 1 to 7, wherein the step of forming source region and drain region includes：
Using grid curb wall and grid conductor as hard mask, by etching the expose portion for removing semiconductor fin, and enter A part for one step etching doping break-through trapping layer so that formed in grid conductor both sides and reach opening for doping break-through trapping layer Mouthful；
Stress layer is formed in opening, the stress layer is made up of the material different from semiconductor fin；And
Source region and drain region are formed in stress layer.
11. methods according to any one of claim 1 to 7, wherein also including after source region and drain region is formed：
Remove grid conductor；And
Form replacement gate conductor.
12. methods according to claim 11, wherein the step of grid conductor is removed and forming replacement gate conductor Between step, also include：
Remove gate-dielectric；And
Form replacement gate electrolyte.
13. methods according to claim 8, wherein, the P-type dopant includes B.
14. methods according to claim 9, wherein, the N type dopant includes P or As.
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