JP2007165780A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve an ability for controlling a short channel effect in a bulk-Fin FET. <P>SOLUTION: For example, a gate electrode portion 21 and source drain areas 22, 23 are formed on both sides of a fin 12 located on a surface of a bulk substrate 11 to be opposed each other. Element separating insulation films 13 are located on the lower portion of the gate electrode portion 21 respectively. The element separating insulation film 13 has a laminated-layers structure, and its lower layer side contacted with the bulk substrate 11, e.g., is formed of an SiO<SB>2</SB>film 13a of a relative permittivity of approximate 3.9, and its upper layer side contacted with the gate electrode portion 21, e.g., is formed of a high dielectric film 13b of a relative permittivity of 10 or more. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a MIS (Metal Insulator Semiconductor) type semiconductor device (FinFET: Fin Field Effect Transistor) having a Fin type structure.

  The development of semiconductor integrated circuits largely depends on the excellent characteristic of the scaling law of MOSFET (Metal Oxide Silicon FET) which is a component of the semiconductor integrated circuit. According to the scaling law, by reducing the size of the element (miniaturizing the element), more elements can be integrated within a limited chip area. However, device miniaturization by extending the conventional planar MOSFET technology is considered to reach the limit in the near future. One of the major factors is that as the miniaturization progresses, the standby power of the element increases rapidly. In principle, it is inevitable that the cutoff current increases exponentially due to a decrease in the threshold voltage. In addition, problems such as an increase in junction leak and surface leak due to an increase in impurity concentration, and deterioration of S coefficient (subthreshold swing) are involved. In fact, there is a trial calculation that the standby power exceeds the active power in the generation where the half pitch is 50 nm or less. In this case, due to the problem of heat generation, the degree of integration cannot be increased even if the elements are miniaturized.

  One of the new transistor structures replacing the planar type MOSFET is FinFET (see Non-Patent Documents 1 and 2, for example). This is a MOSFET comprising a gate electrode and source / drain regions on both sides of a convex semiconductor region (hereinafter referred to as a fin) formed on the surface of a semiconductor substrate so that the two MOSFETs face each other. Is provided. A major feature of the FinFET is that the S coefficient and the short channel effect are improved by reducing the fin width and reducing the channel impurity concentration. Therefore, it is expected that an increase in standby power accompanying miniaturization in the element can be minimized.

  FinFETs can be broadly classified into those using a bulk substrate and those using an SOI (Silicon on Insulator) substrate. A FinFET using a bulk substrate (hereinafter referred to as a bulk-FinFET) has an advantage that the manufacturing cost is lower than that using an SOI substrate, and there is no deterioration in transistor performance due to a body floating effect or a self-heating effect. On the other hand, the bulk-FinFET has a problem that the ability to control the short channel effect is lowered due to the manifestation of punch-through at a position separated from the gate electrode below the fin.

In order to avoid this problem, it has been considered indispensable to introduce a high-concentration impurity layer called a punch-through stopper as in the conventional planar MOSFET. However, the introduction of the punch-through stopper causes undesirable phenomena such as an increase in junction leakage and deterioration of the current driving force. For this reason, there is a need for the development of a new technique that can effectively control the short channel effect instead of the punch-through stopper.
H. J. et al. Cho et al. “The Vth controllability of 5 nm body-tied CMOS FinFET”, in Proc. International Symposium on VLSI Technology, pp. 116-117, 2005. T.A. S. Park et al. , "Threshold voltage behavior of body-tied finFET (OMEGA MOSFET) with respect to ion im- plementation conditions", J. et al. Appl. Phys. 1, Regul. Pap. Short Notes Rev. Pap. (Japan), vol. 43, no. 4B, pp. 2180-2184, April 2004.

  An object of the present invention is to provide a semiconductor device capable of suppressing punch-through at the time of cut-off and improving the short channel effect without causing an increase in junction leakage or deterioration of current driving force. .

  According to one aspect of the present invention, a semiconductor substrate, a semiconductor layer formed on the semiconductor substrate and having a longitudinal direction and a lateral direction, and a gate formed on at least a side surface of the semiconductor layer in the lateral direction. An electrode portion; a source / drain region formed in the semiconductor layer and adjacent to the longitudinal direction of the gate electrode portion; and a side surface of the semiconductor layer, the gate electrode portion and the semiconductor substrate, Provided is a semiconductor device characterized in that at least a portion in contact with the gate electrode portion includes an element isolation insulating film formed of a high dielectric film having a relative dielectric constant of 10 or more. Is done.

  With the above configuration, it is possible to provide a semiconductor device that can suppress punch-through at the time of cut-off and improve the short channel effect without causing an increase in junction leakage or deterioration in current driving force.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, it should be noted that the drawings are schematic and dimensional ratios and the like are different from actual ones. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

[First Embodiment]
FIG. 1 shows a basic configuration of a semiconductor device (FinFET) according to a first embodiment of the present invention. In this case, a double gate structure type bulk-FinFET using a bulk substrate is used as an example to process a part of the bulk substrate into a desired shape, thereby forming a fin (a cross section in one direction has a convex shape). A case where a rectangular semiconductor layer) is formed will be described.

  As shown in FIG. 1, fins 12 made of, for example, single crystal silicon (Si) are provided on the surface of a bulk substrate 11 that is a semiconductor substrate. That is, the fin 12 has a substantially rectangular shape, and is provided along the longitudinal direction shown in FIG. 1 at the upper center portion of the bulk substrate 11 in the substantially central portion in the short direction shown in FIG. In the case of the present embodiment, the fin 12 has a desired width (thickness) W in the short direction of the bulk substrate 11 and is formed in a convex shape, and has the same length as the longitudinal direction of the bulk substrate 11. (L) is provided. The fins 12 have a desired height (H) and are formed in the upper part of the bulk substrate 11.

  An insulating film (for example, SiN film) 14 used as a mask pattern (hard mask) is selectively provided on the upper surface of the fin 12. The insulating film 14 may be removed after being used as a mask pattern.

  Furthermore, a gate electrode portion 21 is provided via a gate insulating film 15 at least at a portion corresponding to the channel portion on each side surface of the fin 12. As the gate insulating film 15, for example, an SiO film, an HfSiO film, an HfAlO film, an HfO film, or the like is used. In the present embodiment, the gate electrode portion 21 is provided on the upper surface portion of the fin 12 via the insulating film 14 so as to cover a part of the fin 12. For example, the gate electrode portion 21 is provided in a substantially inverted U-shape so as to be orthogonal to the fins 12 at a substantially central portion in the longitudinal direction of the bulk substrate 11 shown in FIG. That is, the gate electrode portions 21 are connected to each other on the upper surface portion of the fin 12 and are integrally formed.

  A source region 22 and a drain region 23 are formed adjacent to the gate electrode portion 21 at least on the side surfaces of the fin 12 except for the channel portion.

An insulating film (element isolation insulating film) 13 for element isolation is provided on the surface of the bulk substrate 11 along each side surface of the fin 12 so as to bury the lower portion of the gate electrode portion 21. ing. This element isolation insulating film 13 has a laminated (multiple layer) structure, and the lower layer side in contact with the bulk substrate 11 is composed of, for example, an SiO ₂ film (silicon oxide film) 13a having a relative dielectric constant of about 3.9, The upper layer side in contact with the electrode portion 21 is formed by a high dielectric film 13b having a relative dielectric constant of 10 or more, for example. As the high dielectric film 13b, for example, alumina (Al ₂ O ₃ ), hafnia (HfO ₂ ) and its silicate (Hf—Si—O mixture) or aluminate (Hf—Al—O mixture), or Zirconia (ZrO ₂ ) and its silicate (Zr—Si—O mixture) or aluminate (Zr—Al—O mixture) are used.

  As described above, the bulk-FinFET of the present embodiment has the gate electrode portion 21 through the gate insulating film 15 so as to be opposed to the portions corresponding to the channel portions on both side surfaces of the fin 12 formed on the bulk substrate 11. The portion of the element isolation insulating film 13 in contact with the bulk substrate 11 is formed of a silicon oxide film 13a having a relative dielectric constant of about 3.9, and the gate electrode portion 21 of the element isolation insulating film 13 is formed. The portion in contact with is formed by a high dielectric film 13b having a relative dielectric constant of about 10. In such a structure, the short channel effect can be easily suppressed without introducing a high-concentration impurity layer called a punch-through stopper.

  2A to 2J show a manufacturing process of the bulk-FinFET having the configuration shown in FIG. Here, a double gate structure (see FIG. 1) in which the inversion layer (channel) is not formed in the fin portion corresponding to the insulating film by covering the upper surface of the fin with a thick insulating film will be described as an example. . In addition, each figure (a)-(j) is sectional drawing which follows the II-II line | wire of FIG.

First, as shown in FIG. 5A, for example, an insulating material 14a to be an insulating film 14 is deposited on the upper surface of the bulk substrate 11. Subsequently, the insulating material 14a is processed by RIE (Reactive Ion Etching) to form a hard mask 14 ', for example, as shown in FIG. Subsequently, for example, as shown in FIG. 3C, the surface portion of the bulk substrate 11 is processed by RIE using the hard mask 14 '. Subsequently, for example, as shown in FIG. 6D, the surface portion of the bulk substrate 11 is thermally oxidized to form a thermal oxide film (silicon oxide film) 13a- ₁ . Thereby, the convex-shaped fin 12 in which the width (W) with respect to the short direction of the bulk substrate 11 shown in FIG. 1 is set to a desired thickness is obtained.

Next, after the silicon oxide film 13a- ₂ is embedded in the entire surface of the bulk substrate 11, the upper surface of the silicon oxide film 13a- ₂ is flattened, for example, as shown in FIG. Subsequently, the thermal oxide film 13a- ₁ and the silicon oxide film 13a- ₂ are recessed, and, for example, as shown in FIG. It is formed to have a thickness.

Next, after filling the entire surface of the bulk substrate 11 with a material 13b- ₁ to be the high dielectric film 13b via the silicon oxide film 13a, as shown in FIG. The upper surface of 13b _-1 is flattened. Subsequently, the high dielectric film material 13b- ₁ is recessed, and the high dielectric film 13b on the upper layer side of the element isolation insulating film 13 has a predetermined thickness as shown in FIG. Form.

  Next, for example, as shown in FIG. 6I, a material 15 'to be the gate insulating film 15 is formed on the side surface of the exposed fin 12 respectively. Subsequently, for example, as shown in FIG. 6 (j), after the electrode material 21a is deposited on the entire surface of the bulk substrate 11 via the element isolation insulating film 13, the electrode material 21a is applied to the gate insulating film. The material 15 ′ and the hard mask 14 ′ are processed by RIE. In other words, the gate electrode portion 21 having a predetermined gate length (L) is formed so as to be orthogonal to the fins 12 only at a substantially central portion in the longitudinal direction of the bulk substrate 11. Finally, the source region 22 and the drain region 23 are formed on the fin 12 to complete the bulk-FinFET having the structure shown in FIG.

The bulk-FinFET having the above-described structure can be realized simply by adding the steps of depositing and recessing the high dielectric film material 13b- ₁ to the manufacturing process of a general bulk-FinFET.

  As described above, according to the structure of the present embodiment, the electric field generated by the gate electrode portion 21 acts on the lower portion of the fin 12 through the high dielectric film 13b. In other words, the sneak component of the gate electric field acts electrically directly below the gate electrode portion 21. Thereby, punch-through at the time of cut-off can be suppressed, and the short channel effect can be improved. In particular, since it is not necessary to introduce a high-concentration punch-through stopper, it is possible to suppress junction leakage and at the same time increase current driving force. Therefore, a transistor having a high on / off ratio, a fine size, and excellent standby power can be manufactured at low cost.

  Next, the results when a simulation for verifying the effects (characteristics) in the bulk-FinFET having the structure shown in FIG. 1 will be described. 3 (a) and 3 (b) show simulation results relating to current-voltage characteristics (particularly, FIG. 3 (b) shows the state of on-current when the cut-off currents are aligned). . In each figure, the horizontal axis represents the gate voltage, and the vertical axis represents the drain current. Here, the following three types of n-type bulk-FinFETs are shown in comparison. In any structure, the n-type bulk-FinFET has a gate length (L) of 70 nm and a fin width (W) of 30 nm.

  In FIGS. 4A and 4B, a broken line A indicates that an element isolation insulating film is formed only by a silicon oxide film having a relative dielectric constant of 3.9, the acceptor concentration in the substrate is constant, and a punch-through stopper is provided. The characteristics of an n-type bulk-FinFET (conventional structure 1) not introduced are shown.

  Similarly, a broken line B shows the characteristics of an n-type bulk-FinFET (conventional structure 2) in which an element isolation insulating film is formed only of a silicon oxide film having a relative dielectric constant of 3.9 and a punch-through stopper is introduced. It is.

  On the other hand, the solid line C has a structure of the present embodiment, for example, a part of the element isolation insulating film 13 having a width (height) of 230 nm, a width of 100 nm, and a relative dielectric constant. The n-type bulk-FinFET in which ten high dielectric films 13b are formed (acceptor concentration in the substrate is constant (same as in the conventional structure 1)).

  As is clear from FIGS. 4A and 4B, when the structure of this embodiment is used, an S coefficient equivalent to that of the conventional structure 2 can be obtained without using a punch-through stopper. In particular, as shown in FIG. 5B, in the case of the structure of the present embodiment, the on-current when the cut-off currents of the bulk-FinFETs are equalized becomes the largest.

  From the above, it was proved that the transistor of this embodiment can realize a transistor having a higher on / off ratio than the conventional structure.

Here, the conditions required for the high dielectric film in the structure of this embodiment will be estimated. In general, the width x _d of the drain depletion layer in the FinFET can be approximated by the following equation (1).

Where V _d is the drain bias, φ _S is the channel potential, N _a is the channel impurity concentration, ε _Si is the dielectric constant of silicon, and q is the elementary charge.

Assuming that the fin is completely depleted, the channel potential φ _S at the time of cutoff is expressed by the following equation (2).

Where ΔΦ is the Fermi level difference between the gate electrode and silicon, _Tox is the thickness of the gate insulating film (longitudinal junction depth), ε _ox is the dielectric constant of the gate insulating film, and W is the fin width.

Assuming that V _d = ΔΦ, the following formula (3) is established.

When the width _{xd of the} drain depletion layer becomes larger than half of the gate length, the source depletion layer and the drain depletion layer come into contact with each other and punch through becomes apparent. Therefore, the condition of the high dielectric film necessary for suppressing punch-through can be approximated by the following equation (4).

For example, in the previous simulation, the fin width W is 30 nm and the gate length L (L _g ) is 70 nm. It is assumed that the source / drain diffusion layer region extends to a position with a depth of 30 nm below the lower end of the gate electrode. Then, in this example, T _ox = 30 nm, and the relative dielectric constant required for the material forming the high dielectric film is calculated to be 8.7 or more (preferably about 10). This calculation result coincides with the previous simulation result.

Further, miniaturization factor, T _ox, W, if a L _g both 1 / kappa, relative dielectric constant of the high dielectric film is constant (however, kappa scaling factor). If T _ox = _{W≈L g} / 2, the relative dielectric constant of the high dielectric film only needs to be about the same as that of silicon (10 to 12) or more, and is compatible with semiconductor processes such as alumina and hafnia. Known materials can be used.

  In the first embodiment described above, for example, a structure using a punch-through stopper may be used. In this case, the peak can be set at a lower position and deeper than the conventional structure. For this reason, it is possible to minimize junction leakage and drive current degradation.

In the first embodiment described above, the case where the high dielectric film 13b has a single layer structure has been described. However, the present invention is not limited to this. For example, as shown in FIG. It is also possible to have a two-layer structure made of the materials 13b _-1 and 13b _-2 or a laminated structure having more layers. In this case, the effective dielectric constant calculated from the film thickness and the dielectric constant of each layer must satisfy the above formula (4).

  In the first embodiment described above, a thin silicon oxide film 31 may be formed between the high dielectric film 13b and the fin 12 as shown in FIG. Similarly, for example, in the structure shown in FIG. 4, it is also possible to form a thin silicon oxide film 31 between the high dielectric film 13 b and the fins 12.

  In each of the above-described structures, the double-gate structure bulk-FinFET has been described as an example. However, the present invention is not limited to this. For example, as shown in FIG. The present invention can be similarly applied to a bulk-FinFET having a triple gate structure in which the gate electrode portion 21 is formed through the insulating film 15 ′ having the same thickness as the side surface portion.

[Second Embodiment]
FIG. 7 shows a basic configuration of a semiconductor device (FinFET) according to the second embodiment of the present invention. Here, a double-gate structure bulk-FinFET using a bulk substrate will be described as an example. In addition, the same code | symbol is attached | subjected to FIG. 1 and an identical part, and detailed description is omitted.

  In the case of the present embodiment, the bulk − is formed by forming the gate electrode portion 21 through the gate insulating film 15 so as to face each other in the portions corresponding to the channel portions on both sides of the fin 12 formed on the bulk substrate 11. In the FinFET, only the upper layer portion in contact with the gate electrode portion 21 immediately below the gate electrode portion 21 of the element isolation insulating film 13 ′ is formed by the high dielectric film 13b ′ having a relative dielectric constant of about 10, and the other portions. The portion is formed of a silicon oxide film 13a ′ having a relative dielectric constant of about 3.9.

Such a structure of this embodiment is obtained by, for example, the RIE of the high dielectric film 13b using the gate electrode portion 21 as a hard mask and the silicon oxide film after the manufacturing process shown in FIGS. This can be easily realized by using a series of steps such as re-embedding and recessing the insulating material 13a _-2 to be 13a '.

  The structure of this embodiment can be expected to have substantially the same effect as the bulk-FinFET shown in the first embodiment. That is, the electric field generated by the gate electrode portion 21 acts on the lower portion of the fin 12 via the high dielectric film 13b '. Thereby, punch-through at the time of cut-off can be suppressed, and the short channel effect can be improved. Although the manufacturing process is somewhat complicated as compared with the structure shown in the first embodiment, the influence of the fringe electric field from the drain region 23 via the high dielectric film 13b ′ can be reduced. The effect of through suppression is further improved.

  8 (a) and 8 (b) show the results of a simulation regarding the current-voltage characteristics performed to verify the effect (characteristic) in the bulk-FinFET having the structure shown in FIG. FIG. 5B shows the on-current state when the cut-off currents are aligned. Various conditions for the simulation are the same as in the case of the first embodiment described above.

  As is clear from FIGS. 4A and 4B, it can be clearly seen that when the structure of this embodiment is used, a better S coefficient can be obtained than the structure of the first embodiment.

  Also in the case of the second embodiment, as described above, a structure using a punch-through stopper may be used as in the case of the first embodiment.

  In addition, the high dielectric layer 13b 'can have a stacked structure of a plurality of materials. In this case, the effective dielectric constant calculated from the film thickness and the dielectric constant of each layer must satisfy the above formula (4).

  A thin silicon oxide film (not shown) may be formed between the high dielectric film 13b 'and the fin 12.

  In any case, the present invention is not limited to the double-gate bulk-FinFET, and can be similarly applied to, for example, a triple-gate bulk-FinFET.

  Further, for example, as shown in FIGS. 9A and 9B, the element isolation insulating film 13 can be formed of a single material having a dielectric constant satisfying the above-described formula (4). 1A is a perspective view of a bulk-FinFET, and FIG. 1B is a cross-sectional view taken along line VIII-VIII in FIG. 1A. In this case, it is desirable to form the high concentration layer 41 on the boundary surface between the element isolation insulating film 13 and the bulk substrate 11.

  In any of the above-described embodiments, the gate electrode portion 21 is not limited to a single layer structure, and may be a multilayer structure of two or more layers, for example.

  Further, in any of the above-described embodiments, the fin is not limited to the case where the fin is formed by processing a part of the bulk substrate into a desired shape. For example, the fin is formed on the upper surface of the bulk substrate by an epitaxial layer or the like. The present invention can be similarly applied to a structure in which is formed.

  In addition, the present invention is not limited to the above (each) embodiment, and various modifications can be made without departing from the scope of the invention in the implementation stage. Further, the above (each) embodiment includes various stages of the invention, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if several constituent requirements are deleted from all the constituent requirements shown in the (each) embodiment, the problem (at least one) described in the column of the problem to be solved by the invention can be solved. When the effect (at least one of the effects) described in the “Effect” column is obtained, a configuration from which the constituent requirements are deleted can be extracted as an invention.

The perspective view which shows the structural example of bulk-FinFET according to the 1st Embodiment of this invention. Sectional drawing shown in order to demonstrate the manufacturing process of bulk-FinFET of FIG. The figure which shows the simulation result of bulk-FinFET in the structure of FIG. The perspective view which shows the other structural example of bulk-FinFET according to 1st Embodiment. The perspective view which shows another structural example of bulk-FinFET according to 1st Embodiment. The perspective view which shows another structural example of bulk-FinFET according to 1st Embodiment. The perspective view which shows the structural example of bulk-FinFET according to the 2nd Embodiment of this invention. The figure which shows the simulation result of bulk-FinFET in the structure of FIG. The block diagram which shows an example of bulk-FinFET which concerns on other embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 ... Bulk substrate, 12 ... Fin, 13, 13 '... Insulating film for element isolation, 13a, 13a' ... Silicon oxide film, 13b, 13b '... High dielectric film, 13b- ₁ , 13b- ₂ ... High dielectric Film material, 15... Gate insulating film, 15 ′ gate insulating film material, 21... Gate electrode portion, 31... Silicon oxide film, 41.

Claims (5)

A semiconductor substrate;
A semiconductor layer formed on the semiconductor substrate and having a longitudinal direction and a transverse direction;
A gate electrode portion formed on at least a lateral side surface of the semiconductor layer;
A source / drain region formed in the semiconductor layer and formed adjacent to the longitudinal direction of the gate electrode portion;
A side surface of the semiconductor layer, which is formed between the gate electrode portion and the semiconductor substrate, and at least a portion in contact with the gate electrode portion is formed of a high dielectric film having a relative dielectric constant of 10 or more. A semiconductor device comprising: an element isolation insulating film.   The element isolation insulating film is formed of a plurality of layers, at least a lower layer side in contact with the semiconductor substrate is formed of a silicon oxide film, and an upper layer side in contact with the gate electrode portion is formed of the high dielectric film. The semiconductor device according to claim 1.   2. The element isolation insulating film according to claim 1, wherein the gate electrode portion is formed below the high dielectric film, and the side surfaces of the source / drain regions are formed from a silicon oxide film. Semiconductor device.   4. The high dielectric film according to claim 1, wherein the high dielectric film has a single layer structure made of a single material or a laminated structure made of a plurality of materials. A semiconductor device according to claim 1. The high dielectric film is made of alumina (Al ₂ O ₃ ), hafnia (HfO ₂ ) and its silicate (Hf—Si—O mixture) or aluminate (Hf—Al—O mixture), or zirconia (ZrO). ₂ ) and a silicate thereof (Zr—Si—O mixture) or aluminate (Zr—Al—O mixture).

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