CN106952817B - Method for forming semiconductor structure - Google Patents
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- CN106952817B CN106952817B CN201610006666.7A CN201610006666A CN106952817B CN 106952817 B CN106952817 B CN 106952817B CN 201610006666 A CN201610006666 A CN 201610006666A CN 106952817 B CN106952817 B CN 106952817B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/66803—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
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- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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- Element Separation (AREA)
- Semiconductor Memories (AREA)
Abstract
A method of forming a semiconductor structure, comprising: forming a semiconductor substrate, wherein the semiconductor substrate comprises a substrate and a fin part protruding out of the substrate, and the semiconductor substrate further comprises a buffer layer positioned at the top of the fin part and a hard mask layer on the surface of the buffer layer; forming an initial isolation layer exposing the hard mask layer and the buffer layer on the substrate between the fin parts; forming a protective side wall on the side walls of the hard mask layer and the buffer layer; and removing part of the initial isolation layer to form the isolation layer. By forming the protective side wall on the side walls of the hard mask layer and the buffer layer, the buffer layer can be prevented from being exposed in an etching environment for forming the isolation layer, and the loss of the buffer layer caused by the etching process is reduced; the hard mask layer is positioned on the surface of the buffer layer and serves as a mask layer of a subsequent ion doping process, so that the hard mask layer can be prevented from collapsing due to the buffer layer, the stability and the accuracy of the ion doping process are improved, and the electrical performance of the semiconductor device is improved.
Description
Technical Field
The invention relates to the field of semiconductors, in particular to a method for forming a semiconductor structure.
Background
In semiconductor manufacturing, integrated circuit feature sizes continue to decrease with the trend toward very large scale integrated circuits. To accommodate the reduction in feature size, the channel length of MOSFET devices has also been correspondingly shortened. However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, so that the control capability of the gate to the channel is deteriorated, the difficulty of the gate voltage to pinch off the channel is increased, and the sub-threshold leakage (SCE) phenomenon, so-called short-channel effect (SCE), is easier to occur.
Therefore, in order to better accommodate the reduction of feature sizes, semiconductor processing is gradually beginning to transition from planar MOSFET transistors to three-dimensional transistors with higher power efficiency, such as fin field effect transistors (finfets). In the FinFET, the gate can control the ultrathin body (fin part) at least from two sides, the control capability of the gate on a channel is much stronger than that of a planar MOSFET device, and the short channel effect can be well inhibited; and compared with other devices, the FinFET has better compatibility of the existing integrated circuit manufacturing technology.
However, the electrical performance of the semiconductor device formed by the prior art is poor.
Disclosure of Invention
The invention provides a method for forming a semiconductor structure, which improves the electrical property of a semiconductor device.
To solve the above problems, the present invention provides a method for forming a semiconductor structure. The method comprises the following steps: forming a semiconductor substrate, wherein the semiconductor substrate comprises a substrate and a fin portion protruding out of the substrate, and the semiconductor substrate further comprises a buffer layer located on the top surface of the fin portion and a hard mask layer located on the surface of the buffer layer; forming an initial isolation layer on the substrate between the fin parts, wherein the initial isolation layer exposes the hard mask layer and the buffer layer; forming a protective side wall on the surfaces of the side walls of the hard mask layer and the buffer layer; removing part of the thickness of the initial isolation layer to form an isolation layer; carrying out an ion doping process on the fin part; and removing the protective side wall, the hard mask layer and the buffer layer.
Optionally, the step of forming the semiconductor substrate includes: providing an initial substrate; forming a buffer film on the initial substrate; forming a graphical hard mask layer on the surface of the buffer film; and etching the buffer film and the initial substrate by taking the hard mask layer as a mask to form a plurality of discrete protrusions, taking the etched initial substrate as a substrate, taking the protrusions on the surface of the substrate as fin parts, and forming a buffer layer on the top surface of the fin parts.
Optionally, the buffer layer is made of silicon oxide.
Optionally, the material of the initial isolation layer is silicon oxide.
Optionally, the top of the initial isolation layer is flush with the top of the fin portion; or the top of the initial isolation layer is lower than the top of the fin portion.
Optionally, the step of forming the initial isolation layer includes: forming an isolation film on the surface of the semiconductor substrate, wherein the isolation film covers the surface of the fin part, and the top of the isolation film is higher than that of the hard mask layer; grinding to remove the isolating film higher than the top surface of the hard mask layer; and removing part of the thickness of the isolation film by adopting a first etching process to form the initial isolation layer, wherein the hard mask layer and the buffer layer are exposed out of the initial isolation layer.
Optionally, a second etching process is used to remove a part of the thickness of the initial isolation layer.
Optionally, the first etching process is a dry etching process or a wet etching process, and the second etching process is a dry etching process or a wet etching process.
Optionally, the first etching process and the second etching process are dry etching processes, and the dry etching process is a SiCoNi etching process.
Optionally, the step of the SiCoNi etching process includes: taking nitrogen trifluoride and ammonia gas as reaction gases to generate etching gas; removing a part of the thickness of the isolation film or the initial isolation layer by etching gas to form a byproduct; carrying out an annealing process to sublimate and decompose the by-product into a gaseous product; and removing the gaseous product by air suction.
Optionally, the process parameters of the SiCoNi etching process include: the gas flow of nitrogen trifluoride is 20sccm to 200sccm, the gas flow of ammonia gas is 100sccm to 1000sccm, the chamber pressure is 1Torr to 50Torr, the process time is 10S to 500S, and the temperature of the annealing process is 100 ℃ to 200 ℃.
Optionally, the first etching process and the second etching process are wet etching processes, the solution adopted by the wet etching processes is hydrofluoric acid, the process time is 5 seconds to 500 seconds, and the volume concentration ratio of the hydrofluoric acid is 1:50 to 1: 2000.
Optionally, the thickness of the protective sidewall is
To
Optionally, the protective sidewall is made of silicon nitride, silicon oxynitride, or titanium nitride.
Optionally, the step of forming a protective sidewall on the sidewall surfaces of the hard mask layer and the buffer layer includes: forming a protective side wall film which conformally covers the surface of the initial isolation layer, the surface of the side wall of the fin part, the surface of the side wall of the buffer layer, and the side wall and the top surface of the hard mask layer; and etching and removing the protective side wall films on the surface of the initial isolation layer and the top surface of the hard mask layer by adopting a maskless etching process, and forming protective side walls on the side wall surfaces of the buffer layer and the hard mask layer.
Optionally, the process for forming the protective sidewall film is an atomic layer deposition process.
Optionally, the process parameters of the atomic layer deposition process include: the precursor introduced into the atomic layer deposition chamber is a precursor containing any of silicon, oxygen, nitrogen and titanium, the process temperature is 400-600 ℃, the pressure is 0.5-50 mTorr, the gas flow of the precursor is 500-4000 sccm, and the deposition times are 15-50 times.
Optionally, the process for removing the protective sidewall, the hard mask layer and the buffer layer is a wet etching process.
Optionally, the step of removing the protective sidewall, the hard mask layer and the buffer layer includes: the protective side wall is made of silicon nitride or silicon oxynitride, phosphoric acid is used as an etching solution, the protective side wall and the hard mask layer are removed in the same etching process, and then hydrofluoric acid is used for removing the buffer layer; or the protective side wall is made of titanium nitride, the protective side wall is removed by adopting a mixed solution of ammonia water, hydrogen peroxide and water, the hard mask layer is removed by adopting phosphoric acid, and the buffer layer is removed by adopting hydrofluoric acid.
Optionally, the step of performing an ion doping process on the fin portion includes: taking the hard mask layer as a mask, carrying out an ion doping process on the semiconductor substrate, and injecting doping ions into the isolation layer; and carrying out an annealing process on the semiconductor substrate to promote the doped ions to be diffused into the fin part in the isolation layer in the transverse direction.
Compared with the prior art, the technical scheme of the invention has the following advantages:
the buffer layer and the isolation layer are made of the same material, and protective side walls are formed on the surfaces of the side walls of the hard mask layer and the buffer layer to protect the buffer layer, so that the buffer layer can be prevented from being exposed in an etching environment for forming the isolation layer, and the loss of the buffer layer caused by the etching process is reduced; the hard mask layer is positioned on the surface of the buffer layer and serves as a mask layer of a subsequent ion doping process, so that the hard mask layer can be prevented from collapsing due to the buffer layer, the stability and the accuracy of the ion doping process can be improved, and the electrical performance of the semiconductor device can be improved.
Drawings
FIGS. 1 and 2 are schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure according to the prior art;
fig. 3 to 8 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
The electrical performance of the semiconductor device of the prior art is poor, and the reason is analyzed in combination with the forming method of the semiconductor structure of the prior art. Referring to fig. 1 and 2, schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure in the prior art are shown. The forming method of the semiconductor structure comprises the following steps:
referring to fig. 1, a semiconductor substrate is formed, and the semiconductor substrate includes a substrate 100 and a fin 110 protruding from the substrate 100. The semiconductor substrate further includes a buffer layer 200 on the top surface of the fin 110 and a hard mask layer 300 on the surface of the buffer layer 200.
The hard mask layer 300 is used as a mask layer for an etching process for forming the substrate 100 and the fin portion 110; the buffer layer 200 is used to reduce stress between the hard mask layer 300 and the fin 110.
In this embodiment, the buffer layer 200 is made of silicon oxide; the hard mask layer 300 is made of silicon nitride.
Referring to fig. 2, an isolation layer 101 is formed on the substrate 100 between the fins 110.
The isolation layer 101 is used for isolating adjacent devices. In this embodiment, the material of the isolation layer 101 may be silicon oxide.
Specifically, the step of forming the isolation layer 101 includes: forming an isolation film on the surface of the fin portion 110, wherein the isolation film also covers the surface of the hard mask layer 300, and the top of the isolation film is higher than the top of the hard mask layer 300; flattening the isolation film until the surface of the hard mask layer 300 is exposed; the isolation film is etched back to remove a portion of the thickness to form the isolation layer 101.
However, since the buffer layer 200 and the isolation film are made of the same material and are made of silicon oxide, the process of removing the isolation film with a certain thickness by etching back is prone to cause loss of the buffer layer 200, so that the contact area between the buffer layer 200 and the hard mask layer 300 is reduced, and thus the hard mask layer 300 is prone to collapse. Moreover, the hard mask layer 300 is used as a mask layer in a subsequent ion doping process, and the collapse of the hard mask layer 300 can also reduce the stability and accuracy of the ion doping process, thereby affecting the electrical performance of the semiconductor device.
In order to solve the technical problem, the invention provides a method for forming a semiconductor structure, which comprises the following steps: forming a semiconductor substrate, wherein the semiconductor substrate comprises a substrate and a fin portion protruding out of the substrate, and the semiconductor substrate further comprises a buffer layer located on the top surface of the fin portion and a hard mask layer located on the surface of the buffer layer; forming an initial isolation layer on the substrate between the fin parts, wherein the initial isolation layer exposes the hard mask layer and the buffer layer; forming a protective side wall on the surfaces of the side walls of the hard mask layer and the buffer layer; removing part of the thickness of the initial isolation layer to form an isolation layer; carrying out an ion doping process on the fin part; and removing the protective side wall, the hard mask layer and the buffer layer.
According to the invention, the buffer layer is protected by forming the protective side walls on the side wall surfaces of the hard mask layer and the buffer layer, so that the buffer layer can be prevented from being exposed in an etching environment for forming the isolation layer, and the loss of the buffer layer caused by the etching process is reduced; the hard mask layer is positioned on the surface of the buffer layer and is used as a mask layer of a subsequent ion doping process, so that the hard mask layer can be prevented from collapsing, the stability and the accuracy of the ion doping process can be improved, and the electrical performance of a semiconductor device is improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 3 to 8 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 3, a semiconductor substrate is formed, where the semiconductor substrate includes a substrate 400, a fin 410 protruding from the substrate 400, a buffer layer 500 on a top surface of the fin 410, and a hard mask layer 600 on a surface of the buffer layer 500.
The semiconductor substrate provides a process platform for subsequent device formation. In this embodiment, the semiconductor substrate is used to form an N-type device or a P-type device.
The substrate 400 is made of silicon, germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate 400 can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate; the material of the fin 410 includes silicon, germanium, silicon carbide, gallium arsenide, or indium gallium arsenide. In this embodiment, the substrate 400 is a silicon substrate, and the fin 410 is made of silicon.
Specifically, the step of forming the semiconductor substrate includes: providing an initial substrate; forming a buffer film (not shown) on the initial substrate; forming a graphical hard mask layer 600 on the surface of the buffer film, wherein the shape, the size and the position of the hard mask layer 600 are the same as those of a subsequently formed fin part; and etching the buffer film and the initial substrate by taking the hard mask layer 600 as a mask to form a plurality of discrete protrusions, taking the etched initial substrate as the substrate 400, taking the protrusions on the surface of the substrate 400 as the fin portion 410, and forming the buffer layer 500 on the top surface of the fin portion 410.
In this embodiment, the top dimension of the fin 410 is smaller than the bottom dimension. In other embodiments, the sidewalls of the fin can also be perpendicular to the substrate surface, i.e., the top dimension of the fin is equal to the bottom dimension.
In this embodiment, the hard mask layer 600 is made of silicon nitride, and when a planarization process is performed subsequently, the surface of the hard mask layer 600 can serve as a stop position of the planarization process, and can also play a role in protecting the top of the fin 410, and the hard mask layer 600 can also play a role in a mask layer in a subsequent ion doping process.
In this embodiment, the buffer layer 500 is made of silicon oxide, and is used to reduce the stress between the hard mask layer 600 and the fin 410, and avoid the problem of dislocation generated when the hard mask layer 600 is directly formed on the initial substrate.
After the formation of the fin 410, the method further includes: a linear oxide layer 401 is formed on the surface of the fin 410 to repair the fin 410.
In the process of etching the initial substrate to form the fin 410, the etching process is prone to form a convex corner on the surface of the fin 410 or to cause the surface to have defects, which is prone to affect the device performance of the finfet.
Therefore, in the present embodiment, the fin portion 410 is oxidized to form a linear oxide layer 401 on the surface of the fin portion 410. In the oxidation treatment process, because the Specific Surface (SSA) of the convex edge part of the fin 410 is larger, and is easier to be oxidized, after the linear oxide layer 401 is removed, not only the defect layer on the surface of the fin 410 is removed, but also the convex edge part is removed, so that the surface of the fin 410 is smooth, the crystal lattice quality is improved, the problem of tip discharge at the top angle of the fin 410 is avoided, and the improvement of the performance of the fin field effect transistor is facilitated.
The oxidation process also oxidizes the surface of the substrate 400, and thus, the linear oxide layer 401 is also located on the surface of the substrate 400. In this embodiment, the substrate 400 and the fin 410 are made of silicon. Correspondingly, the material of the linear oxide layer 401 is silicon oxide.
Referring to fig. 4, an initial isolation layer 402 is formed on the substrate 400 between the fins 410, the initial isolation layer 402 exposing the hard mask layer 600 and the buffer layer 500.
The initial isolation layer 402 provides a process foundation for the subsequent formation of isolation layers and provides a process platform for the subsequent formation of protective sidewalls on the sidewalls of the hard mask layer 600 and the buffer layer 500.
Specifically, the step of forming the initial isolation layer 402 includes: forming an isolation film on the surface of the semiconductor substrate, wherein the isolation film covers the surface of the fin portion 410, and the top of the isolation film is higher than the top of the hard mask layer 600; grinding to remove the isolation film higher than the top surface of the hard mask layer 600; a first etching process is used to remove a portion of the thickness of the isolation film to form the initial isolation layer 402, and the initial isolation layer 402 exposes the hard mask layer 600 and the buffer layer 500.
The material of the isolation film is different from the material of the fin 410 and the substrate 400, and the material of the isolation film is a material that is easy to remove, so that the subsequent process of removing the isolation film with a partial thickness does not damage the fin 410 and the substrate 400.
In this embodiment, the isolation film is made of silicon oxide, and the process of forming the isolation film is a chemical vapor deposition process. Accordingly, the material of the initial isolation layer 402 is silicon oxide.
It should be noted that, in order to form a protective sidewall on the sidewall surfaces of the hard mask layer 600 and the buffer layer 500 in the following step, the initial isolation layer 402 at least exposes the hard mask layer 600 and the buffer layer 500, that is, the top of the initial isolation layer 402 is flush with the top of the fin 410; alternatively, the top of the initial isolation layer 402 is lower than the top of the fin 410.
In this embodiment, the top of the initial isolation layer 402 is lower than the top of the fin 410.
In this embodiment, a chemical mechanical polishing process is used to remove the isolation film higher than the top surface of the hard mask layer 600; the first etching process is a dry etching process or a wet etching process.
Specifically, when the first etching process is a dry etching process, the dry etching process is a SiCoNi etching process. The SiCoNi etching process comprises the following steps: taking nitrogen trifluoride and ammonia gas as reaction gases to generate etching gas; removing a part of the thickness of the isolating film by etching gas to form a by-product; carrying out an annealing process to sublimate and decompose the by-product into a gaseous product; and removing the gaseous product by air suction.
In order to ensure that the initial isolation layer 402 at least exposes the hard mask layer 600 and the buffer layer 500, and to form an isolation layer meeting the thickness requirement subsequently, and to avoid excessive protective sidewalls formed subsequently due to removal of excessive isolation films, thereby avoiding unnecessary material waste, the etching process parameters need to be controlled within a reasonable range. Therefore, in this embodiment, the process parameters of the SiCoNi etching process include: the gas flow of nitrogen trifluoride is 20sccm to 200sccm, the gas flow of ammonia gas is 100sccm to 1000sccm, the chamber pressure is 1Torr to 50Torr, the process time is 10S to 500S, and the temperature of the annealing process is 100 ℃ to 200 ℃.
When the first etching process is a wet etching process, the solution adopted by the wet etching process is hydrofluoric acid. In order to ensure that the initial isolation layer 402 at least exposes the hard mask layer 600 and the buffer layer 500, and to form an isolation layer meeting the thickness requirement subsequently, and to avoid excessive protective sidewalls formed subsequently due to removal of excessive isolation films, thereby avoiding unnecessary material waste, the etching process parameters need to be controlled within a reasonable range. For this reason, in this embodiment, the process time of the wet etching process is 5 seconds to 500 seconds, and the volume concentration ratio of the hydrofluoric acid is 1:50 to 1: 2000.
It should be noted that the linear oxide layer 401 on the surface of the fin 410 exposed in the process of removing a portion of the thickness of the isolation film is also removed.
Referring to fig. 5, a protective sidewall 700 is formed on the sidewall surfaces of the hard mask layer 600 and the buffer layer 500.
The protective sidewall 700 is used to protect the buffer layer 500 and prevent the buffer layer 500 from being damaged in the subsequent etching process of the initial isolation layer 402 to form the isolation layer.
Specifically, the step of forming the protective sidewall 700 includes: forming a protective sidewall film conformally covering the surface of the initial isolation layer 402, the sidewall surface of the fin 410, the sidewall surface of the buffer layer 500, and the sidewall and top surface of the hard mask layer 600; and etching to remove the protective side wall films on the surface of the initial isolation layer 402 and the top surface of the hard mask layer 600 by using a maskless etching process, and forming a protective side wall 700 on the side wall surface of the buffer layer 500 and the side wall surface of the hard mask layer 600.
The material of the protective sidewall 700 may be silicon nitride, silicon oxynitride, or titanium nitride. In this embodiment, the material of the protection sidewall 700 is silicon nitride.
In this embodiment, the process of forming the protective sidewall film is an atomic layer deposition process.
The process parameters of the atomic layer deposition process comprise: the precursor introduced into the atomic layer deposition chamber is a precursor containing any of silicon, oxygen, nitrogen and titanium, the process temperature is 400-600 ℃, the pressure is 0.5-50 mTorr, the gas flow of the precursor is 500-4000 sccm, and the deposition times are 15-50 times.
In this embodiment, the material of the protective sidewall 700 is silicon nitride, and correspondingly, the precursor in the atomic layer deposition process is a precursor containing silicon and nitrogen.
It should be noted that the thickness of the protective sidewall 700 should not be too thick, nor too thin. Since the distance between the fins 410 is smaller, that is, the process window for forming the protective sidewall 700 is smallerSmall, in order to better form the protective sidewalls 700 between the fins 410 and to ensure that the protective sidewalls 700 do not have hole defects between the fins 410, the thickness of the protective sidewalls 700 should not be too thick; when the thickness of the protection sidewall 700 is too thin, the protection effect of the protection sidewall 700 on the buffer layer 500 is poor. For this purpose, in this embodiment, the thickness of the protection sidewall 700 is
To
Referring to fig. 6, a portion of the thickness of the initial spacer layer 402 (shown in fig. 5) is removed, forming a spacer layer 412.
The isolation layer 412 serves as an isolation structure of the semiconductor structure for isolating adjacent devices. In this embodiment, the material of the isolation layer 412 is silicon oxide.
It is to be noted that, in the present embodiment, the isolation layer 412 is a shallow trench isolation layer, but is not limited to a shallow trench isolation layer.
In this embodiment, a second etching process is used to remove a portion of the thickness of the initial isolation layer 402, where the second etching process may be a dry etching process or a wet etching process.
And when the second etching process is a dry etching process, the dry etching process is a SiCoNi etching process. The SiCoNi etching process comprises the following steps: taking nitrogen trifluoride and ammonia gas as reaction gases to generate etching gas; removing a portion of the thickness of the initial isolation layer 402 by an etching gas to form a byproduct; carrying out an annealing process to sublimate and decompose the by-product into a gaseous product; and removing the gaseous product by air suction.
Specifically, the technological parameters of the SiCoNi etching process include: the gas flow of nitrogen trifluoride is 20sccm to 200sccm, the gas flow of ammonia gas is 100sccm to 1000sccm, the chamber pressure is 1Torr to 50Torr, the process time is 10S to 500S, and the temperature of the annealing process is 100 ℃ to 200 ℃.
When the second etching process is a wet etching process, the solution adopted by the wet etching process is hydrofluoric acid, the process time is 5 seconds to 500 seconds, and the volume concentration ratio of the hydrofluoric acid is 1:50 to 1: 2000.
In this embodiment, a wet etching process is used to remove a portion of the initial isolation layer 402.
It is noted that the ratio of the thickness of the isolation layer 412 to the height of the fin 410 is greater than or equal to 1/4 and less than or equal to 1/2. In the present embodiment, the ratio of the thickness of the isolation layer 412 to the height of the fin 410 is 1/2.
Referring to fig. 7, an ion doping process is performed on the fin 410.
The ion doping process is used to form doped ions in the fin 410 located in the isolation layer 412, so as to form a punch-through prevention region, thereby preventing punch-through phenomenon from occurring between a source region and a drain region formed in the fin 410 exposed out of the isolation layer 102.
Specifically, the step of performing the ion doping process on the fin portion 410 includes: performing an ion doping process on the semiconductor substrate by using the hard mask layer 600 as a mask, and injecting doped ions into the isolation layer 412; the semiconductor substrate is subjected to an annealing process to promote lateral diffusion of the dopant ions into the fin 410 located in the isolation layer 412.
In this embodiment, the semiconductor substrate is used to form an N-type device or a P-type device. Correspondingly, the ion type doped by the ion doping process is N-type ions or P-type ions.
When the doped ions are N-type ions, the N-type ions are arsenic ions, the energy of the implanted ions is 30Kev to 120Kev, and the dose of the implanted ions is 1E12 to 1E14 atoms per square centimeter; when the doped ions are P-type ions, the P-type ions are boron ions, the energy of the implanted ions is 5Kev to 50Kev, and the dose of the implanted ions is 5E12 to 5E14 atoms per square centimeter.
Referring to fig. 8, the protective sidewall 700 (shown in fig. 7), the hard mask layer 600 (shown in fig. 7), and the buffer layer 500 (shown in fig. 7) are removed.
In this embodiment, the process of removing the protection sidewall 700, the hard mask layer 600 and the buffer layer 500 is a wet etching process.
Specifically, the step of removing the protective sidewall 700, the hard mask layer 600 and the buffer layer 500 includes: when the material of the protective sidewall 700 is silicon nitride or silicon oxynitride, phosphoric acid is used as an etching solution, the protective sidewall 700 and the hard mask layer 600 are removed in the same etching process, and then hydrofluoric acid is used to remove the buffer layer 500; or, when the material of the protective sidewall 700 is titanium nitride, the protective sidewall 700 is removed by using a mixed solution of ammonia water, hydrogen peroxide and water (SC1 solution), the hard mask layer 600 is removed by using phosphoric acid, and the buffer layer 500 is removed by using hydrofluoric acid.
According to the invention, the buffer layer is protected by forming the protective side walls on the side wall surfaces of the hard mask layer and the buffer layer, so that the buffer layer can be prevented from being exposed in an etching environment for forming the isolation layer, and the loss of the buffer layer caused by the etching process is reduced; the hard mask layer is positioned on the surface of the buffer layer and is used as a mask layer of a subsequent ion doping process, so that the hard mask layer can be prevented from collapsing, the stability and the accuracy of the ion doping process can be improved, and the electrical performance of a semiconductor device is improved.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (20)
1. A method of forming a semiconductor structure, comprising:
forming a semiconductor substrate, wherein the semiconductor substrate comprises a substrate and a fin portion protruding out of the substrate, the semiconductor substrate further comprises a buffer layer located on the top surface of the fin portion, and a hard mask layer located on the surface of the buffer layer, and the buffer layer is used for reducing stress between the hard mask layer and the fin portion;
forming an initial isolation layer on the substrate between the fin parts, wherein the top of the initial isolation layer is flush with the top of the fin part, the initial isolation layer exposes the hard mask layer and the buffer layer, and the buffer layer and the isolation layer are made of the same material;
forming a protective side wall on the hard mask layer and the surface of the side wall of the buffer layer to protect the buffer layer and avoid loss of the buffer layer caused by the follow-up etching of the initial isolation layer in the process of forming the isolation layer, and the method comprises the following steps:
forming a protective side wall film which conformally covers the surface of the initial isolation layer, the surface of the side wall of the fin part, the surface of the side wall of the buffer layer, and the side wall and the top surface of the hard mask layer;
etching and removing the protective side wall films on the surface of the initial isolation layer and the top surface of the hard mask layer by using a maskless etching process, and forming protective side walls only on the surface of the side wall of the buffer layer and the surface of the side wall of the hard mask layer;
removing part of the thickness of the initial isolation layer to form an isolation layer;
carrying out an ion doping process on the fin part;
and removing the protective side wall, the hard mask layer and the buffer layer.
2. The method of forming a semiconductor structure of claim 1, wherein the step of forming a semiconductor substrate comprises:
providing an initial substrate;
forming a buffer film on the initial substrate;
forming a graphical hard mask layer on the surface of the buffer film;
and etching the buffer film and the initial substrate by taking the hard mask layer as a mask to form a plurality of discrete protrusions, taking the etched initial substrate as a substrate, taking the protrusions on the surface of the substrate as fin parts, and forming a buffer layer on the top surface of the fin parts.
3. The method of forming a semiconductor structure of claim 1, wherein a material of the buffer layer is silicon oxide.
4. The method of forming a semiconductor structure of claim 1, wherein a material of the initial isolation layer is silicon oxide.
5. The method of forming a semiconductor structure of claim 1, wherein the step of forming the initial isolation layer comprises:
forming an isolation film on the surface of the semiconductor substrate, wherein the isolation film covers the surface of the fin part, and the top of the isolation film is higher than that of the hard mask layer;
grinding to remove the isolating film higher than the top surface of the hard mask layer;
and removing part of the thickness of the isolation film by adopting a first etching process to form the initial isolation layer, wherein the hard mask layer and the buffer layer are exposed out of the initial isolation layer.
6. The method of forming a semiconductor structure of claim 1, wherein a second etch process is used to remove a portion of the thickness of the initial isolation layer.
7. The method of forming a semiconductor structure of claim 5, wherein the first etching process is a dry etching process or a wet etching process.
8. The method of forming a semiconductor structure of claim 6, wherein the second etching process is a dry etching process or a wet etching process.
9. The method of forming a semiconductor structure of claim 7, wherein the first etching process is a dry etching process, and the dry etching process is a SiCoNi etching process.
10. The method of forming a semiconductor structure of claim 8, wherein the second etching process is a dry etching process, and the dry etching process is a SiCoNi etching process.
11. The method of forming a semiconductor structure of claim 9, wherein the step of the SiCoNi etching process comprises:
taking nitrogen trifluoride and ammonia gas as reaction gases to generate etching gas;
removing a part of the thickness of the isolation film or the initial isolation layer by etching gas to form a byproduct;
carrying out an annealing process to sublimate and decompose the by-product into a gaseous product;
and removing the gaseous product by air suction.
12. The method of forming a semiconductor structure of claim 11, wherein the process parameters of the SiCoNi etch process include: the gas flow of nitrogen trifluoride is 20sccm to 200sccm, the gas flow of ammonia gas is 100sccm to 1000sccm, the chamber pressure is 1Torr to 50Torr, the process time is 10S to 500S, and the temperature of the annealing process is 100 ℃ to 200 ℃.
13. The method for forming a semiconductor structure according to claim 7 or 8, wherein the solution used in the wet etching process is hydrofluoric acid, the process time is 5 seconds to 500 seconds, and the volume concentration ratio of the hydrofluoric acid is 1:50 to 1: 2000.
14. The method of claim 1, wherein the protective sidewall has a thickness of 20 Å to 50 Å.
15. The method of claim 1, wherein the material of the protective sidewall is silicon nitride, silicon oxynitride, or titanium nitride.
16. The method of forming a semiconductor structure of claim 1, wherein the process of forming the protective sidewall film is an atomic layer deposition process.
17. The method of forming a semiconductor structure of claim 16, wherein the process parameters of the atomic layer deposition process comprise: the precursor introduced into the atomic layer deposition chamber is a precursor containing any of silicon, oxygen, nitrogen and titanium, the process temperature is 400-600 ℃, the pressure is 0.5-50 mTorr, the gas flow of the precursor is 500-4000 sccm, and the deposition times are 15-50 times.
18. The method of claim 15, wherein the process of removing the protective sidewall, the hard mask layer, and the buffer layer is a wet etch process.
19. The method of forming a semiconductor structure of claim 18, wherein removing the protective sidewall, the hard mask layer, and the buffer layer comprises:
the protective side wall is made of silicon nitride or silicon oxynitride, phosphoric acid is used as an etching solution, the protective side wall and the hard mask layer are removed in the same etching process, and then hydrofluoric acid is used for removing the buffer layer;
or the protective side wall is made of titanium nitride, the protective side wall is removed by adopting a mixed solution of ammonia water, hydrogen peroxide and water, the hard mask layer is removed by adopting phosphoric acid, and the buffer layer is removed by adopting hydrofluoric acid.
20. The method of claim 1, wherein the step of performing an ion doping process on the fin comprises: taking the hard mask layer as a mask, carrying out an ion doping process on the semiconductor substrate, and injecting doping ions into the isolation layer;
and carrying out an annealing process on the semiconductor substrate to promote the doped ions to be diffused into the fin part in the isolation layer in the transverse direction.
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| US9142651B1 (en) * | 2014-03-26 | 2015-09-22 | Globalfoundries Inc. | Methods of forming a FinFET semiconductor device so as to reduce punch-through leakage currents and the resulting device |
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| US9142651B1 (en) * | 2014-03-26 | 2015-09-22 | Globalfoundries Inc. | Methods of forming a FinFET semiconductor device so as to reduce punch-through leakage currents and the resulting device |
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