CN106952817A - The forming method of semiconductor structure - Google Patents
The forming method of semiconductor structure Download PDFInfo
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- CN106952817A CN106952817A CN201610006666.7A CN201610006666A CN106952817A CN 106952817 A CN106952817 A CN 106952817A CN 201610006666 A CN201610006666 A CN 201610006666A CN 106952817 A CN106952817 A CN 106952817A
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- hard mask
- mask layer
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- side wall
- fin
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- 238000001039 wet etching Methods 0.000 claims description 18
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- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 12
- 229910052710 silicon Inorganic materials 0.000 claims description 12
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/66803—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Element Separation (AREA)
- Semiconductor Memories (AREA)
Abstract
A kind of forming method of semiconductor structure, including：Semiconductor base, including substrate and the fin for protruding from substrate are formed, the semiconductor base also includes the hard mask layer of the cushion at the top of fin, and buffer-layer surface；The initial seal coat for exposing the hard mask layer and the cushion is formed on substrate between fin；In hard mask layer and the side wall formation protective side wall of cushion；Part initial seal coat is removed, separation layer is formed.By the side wall formation protective side wall in hard mask layer and cushion, cushion can be avoided exposed to being formed in the etching environment of separation layer, reduce the loss that the etching technics is caused to cushion；The hard mask layer is located at the buffer-layer surface, and hard mask layer is used as the mask layer of subsequent ion doping process, so as to avoid the hard mask layer from being decayed because of the cushion, and then the stability and accuracy of ion doping technique are improved, improve the electric property of semiconductor devices.
Description
Technical field
The present invention relates to semiconductor applications, more particularly to a kind of forming method of semiconductor structure.
Background technology
In semiconductor fabrication, with the development trend of super large-scale integration, integrated circuit feature chi
Very little lasting reduction.For the reduction of meeting market's demand size, the channel length of MOSFET element also it is corresponding not
It is disconnected to shorten.However, with the shortening of device channel length, the distance between device source electrode and drain electrode is also therewith
Shorten, therefore grid is deteriorated therewith to the control ability of raceway groove, grid voltage pinch off (pinch off) raceway groove
Difficulty it is also increasing so that sub-threshold leakage (subthreshold leakage) phenomenon, i.e., it is so-called
Short-channel effect (SCE：Short-channel effects) it is easier to occur.
Therefore, for the reduction of more preferable meeting market's demand size, semiconductor technology gradually starts from plane
Mosfet transistor is to the transistor transient of the three-dimensional with more high effect, such as fin field effect
Manage (FinFET).In FinFET, grid can be at least controlled from both sides to ultra-thin body (fin),
With control ability of the grid more much better than than planar MOSFET devices to raceway groove, it can be good at suppressing short
Channelling effect；And FinFET is relative to other devices, with more preferable existing production of integrated circuits technology
Compatibility.
But, the electric property of the semiconductor devices of prior art formation is poor.
The content of the invention
The problem of present invention is solved is to provide a kind of forming method of semiconductor structure, improves semiconductor devices
Electric property.
To solve the above problems, the present invention provides a kind of forming method of semiconductor structure.Including following step
Suddenly：Semiconductor base is formed, the semiconductor base includes substrate, protrudes from the fin of the substrate,
The semiconductor base also includes the cushion positioned at the fin top surface, and positioned at the buffering
The hard mask layer of layer surface；Form initial seal coat on substrate between the fin, it is described it is initial every
Absciss layer exposes the hard mask layer and the cushion；In the hard mask layer and the side wall of the cushion
Surface forms protective side wall；The initial seal coat of segment thickness is removed, separation layer is formed；To described
Fin carries out ion doping technique；Remove the protective side wall, hard mask layer and cushion.
Optionally, the step of forming semiconductor base includes：Initial substrate is provided；In the initial substrate
Upper formation buffer film；Patterned hard mask layer is formed on the buffer film surface；With the hard mask layer
For mask, the buffer film and the initial substrate are etched, is formed after some discrete projections, etching
Initial substrate is as substrate, positioned at the raised as fin of the substrate surface, and on the top of the fin
Portion surface forms cushion.
Optionally, the material of the cushion is silica.
Optionally, the material of the initial seal coat is silica.
Optionally, the top of the initial seal coat at the top of the fin with flushing；Or, it is described first
The top of beginning separation layer is less than the top of the fin.
Optionally, the step of forming the initial seal coat includes：Formed in the semiconductor substrate surface
Barrier film, the barrier film covers the fin portion surface, and the top of the barrier film is covered firmly higher than described
The top of film layer；Grinding removes the barrier film higher than the hard mask layer top surface；Using the first etching
Technique removes the barrier film of segment thickness to form the initial seal coat, and the initial seal coat
Expose the hard mask layer and the cushion.
Optionally, the initial seal coat of segment thickness is removed using the second etching technics.
Optionally, first etching technics is dry etch process or wet-etching technology, described second
Etching technics is dry etch process or wet-etching technology.
Optionally, first etching technics and the second etching technics are dry etch process, the dry method
Etching technics is SiCoNi etching technics.
Optionally, the step of SiCoNi etching technics includes：Reaction is used as using Nitrogen trifluoride and ammonia
Gas is to generate etching gas；The barrier film of segment thickness or initial isolation are removed by etching gas
Layer, forms accessory substance；Annealing process is carried out, accessory substance distillation is decomposed into gaseous products；Pass through
Air suction mode removes the gaseous products.
Optionally, the technological parameter of the SiCoNi etching technics includes：The gas flow of Nitrogen trifluoride is
20sccm to 200sccm, the gas flow of ammonia is 100sccm to 1000sccm, and chamber pressure is 1Torr
To 50Torr, the process time is 10S to 500S, and the temperature of the annealing process is 100 DEG C to 200 DEG C.
Optionally, first etching technics and the second etching technics are wet-etching technology, the wet method
The solution that etching technics is used is hydrofluoric acid, and the process time is 5 seconds to 500 seconds, the hydrofluoric acid
Volumetric concentration ratio is 1:50 to 1:2000.
Optionally, the thickness of the protective side wall isExtremely
Optionally, the material of the protective side wall is silicon nitride, silicon oxynitride or titanium nitride.
Optionally, the step of the sidewall surfaces formation protective side wall of the hard mask layer and the cushion
Including：Form the conformal covering initial seal coat surface, the sidewall surfaces of fin, the side wall of cushion
Surface, and hard mask layer side wall and the protective side wall film of top surface；Using without mask etching technique,
Etching removes the protective side wall film of the initial seal coat surface and the hard mask layer top surface, in institute
State the sidewall surfaces of cushion and the sidewall surfaces formation protective side wall of the hard mask layer.
Optionally, the technique for forming the protective side wall film is atom layer deposition process.
Optionally, the technological parameter of the atom layer deposition process includes：It is passed through into ald room
Presoma be any a variety of presoma in siliceous, oxygen, nitrogen and titanium, technological temperature is 400 Celsius
Degree is to 600 degrees Celsius, and pressure is 0.5 millitorr to 50 millitorrs, and the gas flow of presoma is 500sccm
To 4000sccm, frequency of depositing is 15 times to 50 times.
Optionally, the technique for removing the protective side wall, hard mask layer and cushion is wet-etching technology.
Optionally, the step of removing the protective side wall, hard mask layer and cushion includes：The protection
The material of side wall is silicon nitride or silicon oxynitride, using phosphoric acid as etching solution, in same step etching technics
The middle removal protective side wall and the hard mask layer, then remove the cushion using hydrofluoric acid；Or
Person, the material of the protective side wall is titanium nitride, is first gone using the mixed solution of ammoniacal liquor, hydrogen peroxide and water
Except the protective side wall, the hard mask layer is then removed using phosphoric acid, institute is finally removed using hydrofluoric acid
State cushion.
Optionally, the step of carrying out ion doping technique to the fin includes：Using the hard mask layer as
Mask, carries out ion doping technique to the semiconductor base, Doped ions is injected into the separation layer
It is interior；Annealing process is carried out to the semiconductor base, promotes the Doped ions horizontal proliferation to enter positioned at institute
State in the fin in separation layer.
Compared with prior art, technical scheme has advantages below：
The cushion is identical with the material of the separation layer, by the hard mask layer and the buffering
The sidewall surfaces formation protective side wall of layer can avoid the cushion from being exposed to protect the cushion
In the etching environment for forming the separation layer, reduce the loss that the etching technics is caused to the cushion；
The hard mask layer is located at the buffer-layer surface, and the hard mask layer is used as subsequent ion doping process
Mask layer, so as to avoid the hard mask layer from being decayed because of the cushion, and then can be with
The stability and accuracy of ion doping technique are improved, the electric property of semiconductor devices is improved.
Brief description of the drawings
Fig. 1 be with Fig. 2 prior art semiconductor structure the embodiment of forming method one in the corresponding knot of each step
Structure schematic diagram；
Fig. 3 to Fig. 8 be semiconductor structure of the present invention the embodiment of forming method one in each step counter structure
Schematic diagram.
Embodiment
The electrical property of the semiconductor devices of prior art is poor, with reference to the formation of prior art semiconductor structure
Method analyzes its reason.With reference to Fig. 1 and Fig. 2, the forming method one of prior art semiconductor structure is shown
Each step counter structure schematic diagram in embodiment.The forming method of the semiconductor structure comprises the following steps：
With reference to Fig. 1, form semiconductor base, the semiconductor base include substrate 100, protrude from it is described
The fin 110 of substrate 100.The semiconductor base is also included positioned at the slow of the top surface of fin 110
Rush layer 200 and the hard mask layer 300 positioned at the surface of cushion 200.
The hard mask layer 300 as the etching technics for forming the substrate 100 and fin 110 mask
Layer；The cushion 200 is used to reduce the stress between the hard mask layer 300 and the fin 110.
In the present embodiment, the material of the cushion 200 is silica；The material of the hard mask layer 300
Expect for silicon nitride.
With reference to Fig. 2, separation layer 101 is formed on the substrate 100 between the fin 110.
The separation layer 101 is used for playing buffer action between adjacent devices.It is described in the present embodiment
The material of separation layer 101 can be silica.
Specifically, the step of forming separation layer 101 includes：The surface of fin 110 formed every
From film, the barrier film also covers the surface of hard mask layer 300, and the top of the barrier film is higher than institute
State the top of hard mask layer 300；The barrier film is planarized until exposing the surface of hard mask layer 300；
It is etched back to remove the barrier film of segment thickness to form the separation layer 101.
But because the cushion 200 is identical with the material of the barrier film, silica material is, is returned
The technique that etching removes the barrier film of segment thickness easily causes loss to the cushion 200, makes
The contact area of the cushion 200 and the hard mask layer 300 diminishes, so as to be easily caused described hard
Mask layer 300 collapses.Moreover, the covering as subsequent ion doping process of hard mask layer 300
Film layer, collapsing for the hard mask layer 300 can also reduce the stability and accuracy of ion doping technique,
And then influence the electric property of semiconductor devices.
In order to solve the technical problem, the present invention provides a kind of forming method of semiconductor structure, including：
Semiconductor base is formed, the semiconductor base includes substrate, protrudes from the fin of the substrate, described
Semiconductor base also includes the cushion positioned at the fin top surface, and positioned at the cushion table
The hard mask layer in face；Initial seal coat, the initial seal coat are formed on substrate between the fin
Expose the hard mask layer and the cushion；In the sidewall surfaces of the hard mask layer and the cushion
Form protective side wall；The initial seal coat of segment thickness is removed, separation layer is formed；To the fin
Carry out ion doping technique；Remove the protective side wall, hard mask layer and cushion.
The present invention is by the sidewall surfaces formation protective side wall in the hard mask layer and the cushion to protect
The cushion is protected, the cushion can be avoided to be exposed to and formed in the etching environment of the separation layer,
Reduce the loss that the etching technics is caused to the cushion；The hard mask layer is located at the cushion
Surface, and the hard mask layer is as the mask layer of subsequent ion doping process, it is described so as to avoid
Hard mask layer decays, and then can improve the stability and accuracy of ion doping technique, improves half
The electric property of conductor device.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings
The specific embodiment of the present invention is described in detail.
Fig. 3 to Fig. 8 be semiconductor structure of the present invention the embodiment of forming method one in each step counter structure
Schematic diagram.
With reference to Fig. 3, form semiconductor base, the semiconductor base include substrate 400, protrude from it is described
The fin 410 of substrate 400, the semiconductor base is also included positioned at the slow of the top surface of fin 410
Rush layer 500, and the hard mask layer 600 positioned at the surface of cushion 500.
The semiconductor base provides technique platform to be subsequently formed device.It is described partly to lead in the present embodiment
Body substrate is used to form N-type device or P-type device.
The material of the substrate 400 is silicon, germanium, SiGe, carborundum, GaAs or gallium indium, institute
It can also be the silicon substrate on insulator or the germanium substrate on insulator to state substrate 400；The fin 410
Material include silicon, germanium, SiGe, carborundum, GaAs or gallium indium.It is described in the present embodiment
Substrate 400 is silicon substrate, and the material of the fin 410 is silicon.
Specifically, the step of forming the semiconductor base includes：Initial substrate is provided；Described initial
Buffer film (not shown) is formed in substrate；Patterned hard mask layer 600 is formed on the buffer film surface,
Pattern, size and the position of the hard mask layer 600 and pattern, size and the position of the fin being subsequently formed
Put identical；It is mask with the hard mask layer 600, etches the buffer film and the initial substrate, shape
Into some discrete projections, the initial substrate after etching is as substrate 400, positioned at the surface of substrate 400
Projection as fin 410, and the fin 410 top surface formation cushion 500.
In the present embodiment, the top dimension of the fin 410 is less than bottom size.In other embodiments,
The side wall of the fin can also be perpendicular with substrate surface, i.e., the top dimension of described fin is equal to bottom
Size.
In the present embodiment, the material of the hard mask layer 600 is silicon nitride, is subsequently carrying out flat chemical industry
During skill, the surface of hard mask layer 600 can as flatening process stop position, additionally it is possible to play
The effect at the top of fin 410 is protected, and the hard mask layer 600 can also adulterate in subsequent ion
Play a part of mask layer in technique.
In the present embodiment, the material of the cushion 500 is silica, for reducing the hard mask layer
Stress between 600 and the fin 410, it is to avoid the hard mask is directly formed on the initial substrate
The problem of dislocation being produced during layer 600.
It should be noted that after the fin 410 is formed, also including：In the table of fin 410
Face forms liner oxidation layer 401, for repairing the fin 410.
During the etching initial substrate forms the fin 410, etching technics is easily described
The surface of fin 410 forms the corner angle of protrusion or surface is had defect, and this easily influences fin field effect pipe
Device performance.
Therefore, the present embodiment carries out oxidation processes to the fin 410 with the surface shape of fin 410
Linear oxide layer 401.In oxidation processes, the faceted portions protruded due to the fin 410
It is bigger than surface (SSA, specific surface area), it is easier to be oxidized, subsequently remove the line
Property oxide layer 401 after, not only the defect layer on the surface of fin 410 is removed, and protrusion corners
Point also it is removed, makes that the surface of the fin 410 is smooth, lattice quality is improved, it is to avoid the fin
The drift angle point discharge problem of portion 410, is conducive to improving the performance of fin field effect pipe.
The oxidation processes can also be aoxidized to the surface of substrate 400, therefore, the liner oxidation
Layer 401 is also located at the surface of substrate 400.In the present embodiment, the substrate 400 and the fin 410
Material be silicon.Accordingly, the material of the liner oxidation layer 401 is silica.
With reference to Fig. 4, initial seal coat 402 is formed on the substrate 400 between the fin 410, it is described
Initial seal coat 402 exposes the hard mask layer 600 and the cushion 500.
The initial seal coat 402 provides Process ba- sis to be subsequently formed separation layer, and to be follow-up described
The sidewall surfaces formation protective side wall of hard mask layer 600 and the cushion 500 provides technique platform.
Specifically, the step of forming initial seal coat 402 includes：In the semiconductor substrate surface
Barrier film is formed, the barrier film covers the surface of fin 410, and the top of the barrier film is higher than
The top of the hard mask layer 600；Grinding removes the isolation higher than the top surface of hard mask layer 600
Film；The first etching technics is used to remove the barrier film of segment thickness to form the initial seal coat
402, and the initial seal coat 402 exposes the hard mask layer 600 and the cushion 500.
The material of the barrier film is different from the material of the fin 410 and the substrate 400, and institute
State the material of barrier film to be easy to removed material so that the follow-up barrier film for removing segment thickness
Technique the fin 410 and the substrate 400 will not be caused damage.
In the present embodiment, the material of the barrier film is silica, forms the technique of the barrier film to change
Learn gas-phase deposition.Accordingly, the material of the initial seal coat 402 is silica.
It should be noted that in order to subsequently in the hard mask layer 600 and the side wall of the cushion 500
Surface forms protective side wall, and the initial seal coat 402 at least exposes the hard mask layer 600 and institute
State cushion 500, that is to say, that the top of the initial seal coat 402 and the top of the fin 410
Flush；Or, the top of the initial seal coat 402 is less than the top of the fin 410.
In the present embodiment, the top of the initial seal coat 402 is less than the top of the fin 410.
In the present embodiment, removed and pushed up higher than the hard mask layer 600 using chemical mechanical milling tech grinding
The barrier film on portion surface；First etching technics is dry etch process or wet-etching technology.
Specifically, when first etching technics is dry etch process, the dry etch process is
SiCoNi etching technics.The step of SiCoNi etching technics, includes：Using Nitrogen trifluoride and ammonia as
Reacting gas is to generate etching gas；The barrier film of segment thickness is removed by etching gas, is formed
Accessory substance；Annealing process is carried out, accessory substance distillation is decomposed into gaseous products；Pass through air suction mode
Remove the gaseous products.
In order to ensure that the initial seal coat 402 at least exposes the hard mask layer 600 and the buffering
Layer 500, while meeting the separation layer of thickness requirement to be subsequently formed, and avoids removing excessive isolation
Film and cause to be subsequently formed excessive protective side wall, in order to avoid cause unnecessary waste of material, the etching
Technological parameter need to be controlled in the reasonable scope.Therefore, in the present embodiment, the SiCoNi etching technics
Technological parameter includes：The gas flow of Nitrogen trifluoride is 20sccm to 200sccm, the gas flow of ammonia
For 100sccm to 1000sccm, chamber pressure is 1Torr to 50Torr, the process time be 10S to 500S,
The temperature of the annealing process is 100 DEG C to 200 DEG C.
When first etching technics is wet-etching technology, the solution that the wet-etching technology is used
For hydrofluoric acid.In order to ensure that the initial seal coat 402 at least exposes the hard mask layer 600 and institute
Cushion 500 is stated, while meet the separation layer of thickness requirement to be subsequently formed, and avoids removing excessive
Barrier film and cause to be subsequently formed excessive protective side wall, in order to avoid cause unnecessary waste of material, institute
Stating etch process parameters need to control in the reasonable scope.Therefore, in the present embodiment, the wet etching work
The process time of skill is 5 seconds to 500 seconds, and the volumetric concentration ratio of the hydrofluoric acid is 1:50 to 1:2000.
It should be noted that also removing what is exposed during the barrier film of segment thickness is removed
The liner oxidation layer 401 on the surface of fin 410.
With reference to Fig. 5, in the sidewall surfaces formation protection side of the hard mask layer 600 and the cushion 500
Wall 700.
The protective side wall 700 is used to protect the cushion 500, it is to avoid initially isolate described in subsequent etching
During layer 402 is to form separation layer, loss is caused to the cushion 500.
Specifically, the step of forming protective side wall 700 includes：Formed conformal covering it is described it is initial every
The surface of absciss layer 402, the sidewall surfaces of fin 410, the sidewall surfaces of cushion 500, and hard mask
The side wall and the protective side wall film of top surface of layer 600；Using without mask etching technique, etching removes institute
The protective side wall film of the surface of initial seal coat 402 and the top surface of the hard mask layer 600 is stated, described
The sidewall surfaces of cushion 500 and the sidewall surfaces of the hard mask layer 600 formation protective side wall 700.
The material of the protective side wall 700 can be silicon nitride, silicon oxynitride or titanium nitride.The present embodiment
In, the material of the protective side wall 700 is silicon nitride.
In the present embodiment, the technique for forming the protective side wall film is atom layer deposition process.
The technological parameter of the atom layer deposition process includes：The presoma being passed through into ald room
For any a variety of presoma in siliceous, oxygen, nitrogen and titanium, technological temperature is 400 degrees Celsius to 600
Degree Celsius, pressure is 0.5 millitorr to 50 millitorrs, and the gas flow of presoma is 500sccm to 4000sccm,
Frequency of depositing is 15 times to 50 times.
In the present embodiment, the material of the protective side wall 700 is silicon nitride, accordingly, the atomic layer
Presoma in depositing operation is the siliceous presoma with nitrogen.
It should be noted that the thickness of the protective side wall 700 is unsuitable blocked up, it is also unsuitable excessively thin.Due to
The distance between the fin 410 is smaller, that is to say, that form the process window of the protective side wall 700
Mouth is smaller, in order that the protective side wall 700 is formed preferably between the fin 410, and it is described
Protective side wall 700 is without hole defect between the fin 410, and the thickness of the protective side wall 700 is not
It is preferably blocked up；When the thickness of the protective side wall 700 is excessively thin, 700 pairs of the protective side wall buffering
The protecting effect of layer 500 is poor.Therefore, in the present embodiment, the thickness of the protective side wall 700 is
Extremely
With reference to Fig. 6, remove the initial seal coat 402 (as shown in Figure 5) of segment thickness, formation every
Absciss layer 412.
The separation layer 412 as semiconductor structure isolation structure, for being played between adjacent devices
Buffer action.In the present embodiment, the material of the separation layer 412 is silica.
It should be noted that in the present embodiment, the separation layer 412 is shallow groove isolation layer, but is not limited
In shallow groove isolation layer.
In the present embodiment, the initial seal coat 402 of segment thickness, institute are removed using the second etching technics
It can be dry etch process or wet-etching technology to state the second etching technics.
When second etching technics is dry etch process, the dry etch process is carved for SiCoNi
Etching technique.The step of SiCoNi etching technics, includes：Reacting gas is used as using Nitrogen trifluoride and ammonia
To generate etching gas；The initial seal coat 402 of segment thickness is removed by etching gas, forms secondary
Product；Annealing process is carried out, accessory substance distillation is decomposed into gaseous products；Gone by air suction mode
Except the gaseous products.
Specifically, the technological parameter of the SiCoNi etching technics includes：The gas flow of Nitrogen trifluoride is
20sccm to 200sccm, the gas flow of ammonia is 100sccm to 1000sccm, and chamber pressure is 1Torr
To 50Torr, the process time is 10S to 500S, and the temperature of the annealing process is 100 DEG C to 200 DEG C.
When second etching technics is wet-etching technology, it is molten that the wet-etching technology is used
Liquid is hydrofluoric acid, and the process time is 5 seconds to 500 seconds, and the volumetric concentration ratio of the hydrofluoric acid is 1:50 to
1:2000。
In the present embodiment, the part initial seal coat 402 is removed using wet-etching technology.
It should be noted that the ratio between the thickness of the separation layer 412 and height of the fin 410 are more than
Equal to 1/4 and less than or equal to 1/2.In the present embodiment, the thickness of the separation layer 412 and the fin 410
The ratio between height be 1/2.
With reference to Fig. 7, ion doping technique is carried out to the fin 410.
The ion doping technique is used in the fin 410 in the separation layer 412 form doping
Ion, so as to form anti-reach through region, it is to avoid be subsequently exposed in the fin 410 of the separation layer 102
Occurs punch through between the source region of formation and drain region.
Specifically, the step of carrying out ion doping technique to the fin 410 includes：With the hard mask
Layer 600 is mask, carries out ion doping technique to the semiconductor base, Doped ions are injected into institute
State in separation layer 412；Annealing process is carried out to the semiconductor base, promotes the Doped ions horizontal
Diffuse into the fin 410 in the separation layer 412.
In the present embodiment, the semiconductor base is used to form N-type device or P-type device.Accordingly,
The ionic type that the ion doping technique is adulterated is N-type ion or p-type ion.
When the Doped ions are N-type ion, the N-type ion is arsenic ion, the ion energy of injection
Measure as 30Kev to 120Kev, the ion dose of injection is 1E12 to 1E14 atom per square centimeters；When
When the Doped ions are p-type ion, the p-type ion is boron ion, and the ion energy of injection is 5Kev
To 50Kev, the ion dose of injection is 5E12 to 5E14 atom per square centimeters.
With reference to Fig. 8, the protective side wall 700 (as shown in Figure 7), (such as Fig. 7 of hard mask layer 600 are removed
It is shown) and cushion 500 (as shown in Figure 7).
In the present embodiment, the technique for removing the protective side wall 700, hard mask layer 600 and cushion 500
For wet-etching technology.
Specifically, the step of removing the protective side wall 700, hard mask layer 600 and cushion 500 includes：
When the material of the protective side wall 700 is silicon nitride or silicon oxynitride, using phosphoric acid as etching solution,
The protective side wall 700 and the hard mask layer 600 are removed in same step etching technics, then using hydrogen fluorine
Acid removes the cushion 500；Or, when the material of the protective side wall 700 is titanium nitride, first use
The mixed solution (SC1 solution) of ammoniacal liquor, hydrogen peroxide and water removes the protective side wall 700, then uses
Phosphoric acid removes the hard mask layer 600, finally removes the cushion 500 using hydrofluoric acid.
The present invention is by the sidewall surfaces formation protective side wall in the hard mask layer and the cushion to protect
The cushion is protected, the cushion can be avoided to be exposed to and formed in the etching environment of the separation layer,
Reduce the loss that the etching technics is caused to the cushion；The hard mask layer is located at the cushion
Surface, and the hard mask layer is as the mask layer of subsequent ion doping process, it is described so as to avoid
Hard mask layer decays, and then can improve the stability and accuracy of ion doping technique, improves half
The electric property of conductor device.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art,
Without departing from the spirit and scope of the present invention, it can make various changes or modifications, therefore the guarantor of the present invention
Shield scope should be defined by claim limited range.
Claims (20)
1. a kind of forming method of semiconductor structure, it is characterised in that including：
Semiconductor base is formed, the semiconductor base includes substrate, protrudes from the fin of the substrate,
The semiconductor base also includes the cushion positioned at the fin top surface, and positioned at the buffering
The hard mask layer of layer surface；
Initial seal coat is formed on substrate between the fin, the initial seal coat exposes described hard
Mask layer and the cushion；
In the sidewall surfaces formation protective side wall of the hard mask layer and the cushion；
The initial seal coat of segment thickness is removed, separation layer is formed；
Ion doping technique is carried out to the fin；
Remove the protective side wall, hard mask layer and cushion.
2. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that formed semiconductor-based
The step of bottom, includes：
Initial substrate is provided；
Buffer film is formed on the initial substrate；
Patterned hard mask layer is formed on the buffer film surface；
Using the hard mask layer as mask, the buffer film and the initial substrate are etched, some points are formed
Initial substrate after vertical projection, etching is as substrate, positioned at the raised as fin of the substrate surface,
And in the top surface formation cushion of the fin.
3. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that the cushion
Material is silica.
4. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that the initial isolation
The material of layer is silica.
5. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that the initial isolation
The top of layer at the top of the fin with flushing；
Or, the top of the initial seal coat is less than the top of the fin.
6. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that form described initial
The step of separation layer, includes：
In semiconductor substrate surface formation barrier film, the barrier film covers the fin portion surface, and
The top of the barrier film is higher than the top of the hard mask layer；
Grinding removes the barrier film higher than the hard mask layer top surface；
The barrier film of the first etching technics removal segment thickness is used to form the initial seal coat,
And the initial seal coat exposes the hard mask layer and the cushion.
7. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that etched using second
Technique removes the initial seal coat of segment thickness.
8. the forming method of semiconductor structure as claimed in claims 6 or 7, it is characterised in that described first
Etching technics is dry etch process or wet-etching technology, and second etching technics is dry etching
Technique or wet-etching technology.
9. the forming method of semiconductor structure as claimed in claim 8, it is characterised in that first etching
Technique and the second etching technics are dry etch process, and the dry etch process is that SiCoNi etches work
Skill.
10. the forming method of semiconductor structure as claimed in claim 9, it is characterised in that the SiCoNi
The step of etching technics, includes：
Using Nitrogen trifluoride and ammonia as reacting gas to generate etching gas；
The barrier film or initial seal coat of segment thickness are removed by etching gas, accessory substance is formed；
Annealing process is carried out, accessory substance distillation is decomposed into gaseous products；
The gaseous products are removed by air suction mode.
11. the forming method of semiconductor structure as claimed in claim 10, it is characterised in that the SiCoNi
The technological parameter of etching technics includes：The gas flow of Nitrogen trifluoride is 20sccm to 200sccm, ammonia
The gas flow of gas is 100sccm to 1000sccm, and chamber pressure is 1Torr to 50Torr, technique
Time is 10S to 500S, and the temperature of the annealing process is 100 DEG C to 200 DEG C.
12. the forming method of semiconductor structure as claimed in claim 8, it is characterised in that first etching
Technique and the second etching technics are wet-etching technology, the solution that the wet-etching technology is used for
Hydrofluoric acid, the process time is 5 seconds to 500 seconds, and the volumetric concentration ratio of the hydrofluoric acid is 1:50 to
1:2000。
13. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that the protective side wall
Thickness beExtremely
14. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that the protective side wall
Material be silicon nitride, silicon oxynitride or titanium nitride.
15. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that in the hard mask
The step of sidewall surfaces formation protective side wall of layer and the cushion, includes：
Form the conformal covering initial seal coat surface, the sidewall surfaces of fin, the side wall table of cushion
Face, and hard mask layer side wall and the protective side wall film of top surface；
Using without mask etching technique, etching removes the initial seal coat surface and the hard mask layer top
The protective side wall film on portion surface, in the sidewall surfaces and the sidewall surfaces of the hard mask layer of the cushion
Form protective side wall.
16. the forming method of the semiconductor structure as described in claims 14 or 15, it is characterised in that form institute
The technique for stating protective side wall film is atom layer deposition process.
17. the forming method of semiconductor structure as claimed in claim 16, it is characterised in that the atomic layer deposition
The technological parameter of product technique includes：The presoma being passed through into ald room is siliceous, oxygen, nitrogen
With any a variety of presoma in titanium, technological temperature is 400 degrees Celsius to 600 degrees Celsius, pressure
For 0.5 millitorr to 50 millitorrs, the gas flow of presoma is 500sccm to 4000sccm, deposition time
Number is 15 times to 50 times.
18. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that remove the protection
The technique of side wall, hard mask layer and cushion is wet-etching technology.
19. the forming method of the semiconductor structure as described in claim 14 or 18, it is characterised in that remove institute
The step of stating protective side wall, hard mask layer and cushion includes：
The material of the protective side wall is silicon nitride or silicon oxynitride, using phosphoric acid as etching solution, same
The protective side wall and the hard mask layer are removed in one step etching technics, institute is then removed using hydrofluoric acid
State cushion；
Or, the material of the protective side wall is titanium nitride, first using the mixing of ammoniacal liquor, hydrogen peroxide and water
Solution removes the protective side wall, then the hard mask layer is removed using phosphoric acid, finally using hydrofluoric acid
Remove the cushion.
20. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that enter to the fin
The step of row ion doping technique, includes：Using the hard mask layer as mask, to the semiconductor base
Ion doping technique is carried out, Doped ions are injected into the separation layer；
Annealing process is carried out to the semiconductor base, promotes the Doped ions horizontal proliferation to enter positioned at institute
State in the fin in separation layer.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101577278A (en) * | 2008-05-06 | 2009-11-11 | 台湾积体电路制造股份有限公司 | Semiconductor structure and forming method thereof |
| CN103855015A (en) * | 2012-11-30 | 2014-06-11 | 中国科学院微电子研究所 | FinFET and manufacturing method |
| US9142651B1 (en) * | 2014-03-26 | 2015-09-22 | Globalfoundries Inc. | Methods of forming a FinFET semiconductor device so as to reduce punch-through leakage currents and the resulting device |
| US9184293B2 (en) * | 2013-08-09 | 2015-11-10 | Samsung Electronics Co., Ltd. | Methods of fabricating semiconductor devices having punch-through stopping regions |
| CN106601688A (en) * | 2015-10-16 | 2017-04-26 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and manufacturing method thereof, and electronic device |
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2016
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101577278A (en) * | 2008-05-06 | 2009-11-11 | 台湾积体电路制造股份有限公司 | Semiconductor structure and forming method thereof |
| CN103855015A (en) * | 2012-11-30 | 2014-06-11 | 中国科学院微电子研究所 | FinFET and manufacturing method |
| US9184293B2 (en) * | 2013-08-09 | 2015-11-10 | Samsung Electronics Co., Ltd. | Methods of fabricating semiconductor devices having punch-through stopping regions |
| US9142651B1 (en) * | 2014-03-26 | 2015-09-22 | Globalfoundries Inc. | Methods of forming a FinFET semiconductor device so as to reduce punch-through leakage currents and the resulting device |
| CN106601688A (en) * | 2015-10-16 | 2017-04-26 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and manufacturing method thereof, and electronic device |
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