CN107342227B - Method for forming fin field effect transistor grid structure - Google Patents
Method for forming fin field effect transistor grid structure Download PDFInfo
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- CN107342227B CN107342227B CN201710731200.8A CN201710731200A CN107342227B CN 107342227 B CN107342227 B CN 107342227B CN 201710731200 A CN201710731200 A CN 201710731200A CN 107342227 B CN107342227 B CN 107342227B
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- 238000000034 method Methods 0.000 title claims abstract description 27
- 230000005669 field effect Effects 0.000 title claims abstract description 11
- 238000005468 ion implantation Methods 0.000 claims abstract description 13
- 239000000463 material Substances 0.000 claims abstract description 13
- 239000000126 substance Substances 0.000 claims abstract description 10
- 238000005498 polishing Methods 0.000 claims abstract description 9
- 238000000151 deposition Methods 0.000 claims abstract description 8
- 238000000059 patterning Methods 0.000 claims abstract description 7
- 238000005530 etching Methods 0.000 claims abstract description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 6
- 229920005591 polysilicon Polymers 0.000 claims abstract description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- 229910003481 amorphous carbon Inorganic materials 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 229910052582 BN Inorganic materials 0.000 claims description 3
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910000449 hafnium oxide Inorganic materials 0.000 claims description 3
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 238000003384 imaging method Methods 0.000 claims 1
- 230000000717 retained effect Effects 0.000 claims 1
- 238000002347 injection Methods 0.000 abstract 1
- 239000007924 injection Substances 0.000 abstract 1
- 239000004065 semiconductor Substances 0.000 description 4
- 239000003989 dielectric material Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 230000005764 inhibitory process Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
Abstract
The invention provides a method for forming a fin field effect transistor grid structure, which comprises the following steps: performing trap ion implantation after the STI structure is formed; depositing a dielectric layer material on the structure; carrying out chemical mechanical polishing treatment on the dielectric layer material, and then carrying out back etching to form a sub-dielectric layer; depositing a gate dielectric layer and a polysilicon layer on the structure; carrying out chemical mechanical polishing treatment on the structure, and then carrying out gate patterning to expose the fin structure and the sub-dielectric layer in the source drain region; removing the sub-dielectric layer exposed in the source drain region; and carrying out subsequent process treatment on the gate structure. According to the forming method of the fin field effect transistor grid structure, the sub-dielectric layer is formed below the grid, the position of an effective channel is improved, the trap ion injection interface is avoided, and the performance of a FinFET device is improved.
Description
Technical Field
The present invention relates to the field of semiconductor integrated circuit fabrication, and more particularly, to a method for forming a fin field effect transistor gate structure.
Background
With the increase of the integration level of a miniaturized system, the size of a Metal Oxide Semiconductor (MOS) device is sharply reduced, the high integration level of the device and the ultra-thin gate oxide layer enable the device to provide better performance, but the manufactured MOS device will bring a series of reliability problems due to the shortening of the channel of the device and the thinning of the gate oxide layer. Conventional devices below 20 nm have failed to meet moore's law, and FinFET devices typically include a semiconductor fin (fin) having a high aspect ratio, typically comprising a single crystal semiconductor material that is substantially rectangular in cross-section, with the height of the fin typically being greater than the width of the fin to achieve a higher on-current per unit area while forming the channel and source/drain regions of the transistor in the fin. Compared with the conventional transistor, the FinFET has higher gate width-length ratio, increases the control of the gate to the channel, can inhibit the short-channel effect and increase the driving current, has the advantages of higher switching speed, higher current density, better inhibition of the short-channel effect and the like, and is applied more and more.
The FinFET is a three-dimensional structure, and the ion implantation of the trap needs to be performed in an inclined mode, so that an ion implantation interface exists at the junction of the fin structure and the STI, and weak points are brought to the device. The existing structure can not avoid the interface of ion implantation no matter the polysilicon grid or the metal grid.
Disclosure of Invention
The invention provides a method for forming a fin field effect transistor grid structure.
In order to achieve the above object, the present invention provides a method for forming a gate structure of a fin field effect transistor, comprising the steps of:
performing trap ion implantation after the STI structure is formed;
depositing a dielectric layer material on the structure;
carrying out chemical mechanical polishing treatment on the dielectric layer material, and then carrying out back etching to form a sub-dielectric layer;
depositing a gate dielectric layer and a polysilicon layer on the structure;
carrying out chemical mechanical polishing treatment on the structure, and then carrying out gate patterning to expose the fin structure and the sub-dielectric layer in the source drain region;
removing the sub-dielectric layer exposed in the source drain region;
and carrying out subsequent process treatment on the gate structure.
Furthermore, the dielectric layer material is an oxide layer, silicon nitride, amorphous carbon, boron nitride, silicon oxynitride or hafnium oxide.
Further, the height of the sub-dielectric layer accounts for less than 20% of the height of the fin structure.
Further, the height of the sub-dielectric layer accounts for less than 10% of the height of the fin structure.
Further, the sub-dielectric layer is a stress layer.
Further, the sub-dielectric layers have a stress of >500MPa or < -500 MPa.
Furthermore, the sub-dielectric layer exposed from the source drain region is reserved after the gate patterning treatment.
According to the forming method of the fin field effect transistor grid structure, trap ion implantation is conducted on the STI structure, then the dielectric layer material is deposited, etching back is conducted after CMP processing to obtain the sub-dielectric layer, the sub-dielectric layer is formed below the grid, the position of an effective channel is improved, the trap ion implantation interface is avoided, and the performance of a FinFET device is improved.
Drawings
Fig. 1 is a flow chart illustrating a method of forming a finfet gate structure according to a preferred embodiment of the invention.
Fig. 2 to 6 are schematic structural views illustrating a method for forming a finfet gate structure according to a preferred embodiment of the invention.
Detailed Description
The following description will be given with reference to the accompanying drawings, but the present invention is not limited to the following embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is noted that the drawings are in greatly simplified form and that non-precision ratios are used for convenience and clarity only to aid in the description of the embodiments of the invention.
Referring to fig. 1, fig. 1 is a flow chart illustrating a method for forming a gate structure of a finfet device according to a preferred embodiment of the invention.
The invention provides a method for forming a fin field effect transistor grid structure, which comprises the following steps:
step S100: performing trap ion implantation after the STI structure is formed;
step S200: depositing a dielectric layer material on the structure;
step S300: carrying out chemical mechanical polishing treatment on the dielectric layer material, and then carrying out back etching to form a sub-dielectric layer;
step S400: depositing a gate dielectric layer and a polysilicon layer on the structure;
step S500: carrying out chemical mechanical polishing treatment on the structure, and then carrying out gate patterning to expose the fin structure and the sub-dielectric layer in the source drain region;
step S600: removing the sub-dielectric layer exposed in the source drain region;
step S700: and carrying out subsequent process treatment on the gate structure.
Fig. 2 to 6 are schematic structural views illustrating a method for forming a finfet gate structure according to a preferred embodiment of the invention. In fig. 2, a well ion implantation (well implant) process is performed after the STI structure is formed, wherein a fin structure 200 and an STI oxide layer 300 are disposed on the STI structure 100, and fig. 3 shows a dielectric material 400 deposited on the STI structure, wherein the dielectric material 400 is Oxide (OX), silicon nitride (SiN), amorphous carbon (amorphous carbon), boron nitride, silicon oxynitride, or HK (e.g., hafnium oxide), but is not limited thereto.
Fig. 4 shows that the dielectric layer material 400 is etched back after being subjected to the chemical mechanical polishing process to form the sub-dielectric layer 500, the height of the sub-dielectric layer 500 accounts for less than 20%, preferably less than 10%, of the height of the fin structure 200, the sub-dielectric layer 500 is preferably a stress layer, different stresses can be selected according to NMOS/PMOS requirements, and the stress of the sub-dielectric layer 500 can also be the same stress, and is preferably greater than 500MPa (high tensile stress) or < -500MPa (high compressive stress). The high stress of the sub-dielectric layer 500 may be rls by ion implantation, but is not limited to NMOS/PMOS.
Fig. 5 shows a gate dielectric layer and a polysilicon layer 600 deposited on the structure, fig. 6 shows a gate patterning performed after the structure is subjected to chemical mechanical polishing, the fin structure 200 and the sub-dielectric layer 500 in the source/drain region are exposed, and the sub-dielectric layer 500 exposed in the source/drain region is removed. According to another preferred embodiment of the present invention, after the gate patterning, the sub-dielectric layer 500 in the source/drain (S/D) region can be selectively remained, and for the gate-last process, after the dummy gate is removed, the sub-dielectric layer 500 in the channel region is remained.
In summary, the method for forming the gate structure of the fin field effect transistor provided by the invention performs well ion implantation on the STI structure, then deposits the dielectric layer material, performs etching back after CMP processing to obtain the sub-dielectric layer, and forms the sub-dielectric layer under the gate, thereby improving the position of the effective channel, avoiding the interface of the well ion implantation, and improving the performance of the FinFET device.
Although the present invention has been described with reference to the preferred embodiments, it is not intended to be limited thereto. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the protection scope of the present invention should be determined by the appended claims.
Claims (7)
1. A method for forming a gate structure of a fin field effect transistor (FinFET) comprises the following steps:
performing trap ion implantation after the STI structure is formed; wherein the STI structure is provided with a fin structure and an STI oxide layer;
depositing a dielectric layer material on the STI structure;
carrying out chemical mechanical polishing treatment on the dielectric layer material, and then carrying out back etching to form a sub-dielectric layer;
depositing a gate dielectric layer and a polysilicon layer on the sub-dielectric layer and the fin structure of the STI structure;
performing chemical mechanical polishing treatment on the STI structure, and then performing gate imaging to expose the fin structure and the sub-dielectric layer in the source drain region;
removing the sub-dielectric layer exposed in the source drain region;
and carrying out subsequent process treatment on the gate structure.
2. The method of claim 1, wherein the dielectric layer is formed of an oxide layer, silicon nitride, amorphous carbon, boron nitride, silicon oxynitride, or hafnium oxide.
3. The method of claim 1, wherein the sub-dielectric layer has a height that is less than 20% of a height of the fin structure.
4. The method of claim 1, wherein the sub-dielectric layer has a height that is less than 10% of a height of the fin structure.
5. The method of claim 1, wherein the sub-dielectric layer is a stress layer.
6. The method of claim 1, wherein the sub-dielectric layer has a stress of >500MPa or < -500 MPa.
7. The method of claim 1, wherein the exposed sub-dielectric layer of the source and drain regions is retained after the gate patterning.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710731200.8A CN107342227B (en) | 2017-08-23 | 2017-08-23 | Method for forming fin field effect transistor grid structure |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710731200.8A CN107342227B (en) | 2017-08-23 | 2017-08-23 | Method for forming fin field effect transistor grid structure |
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| Publication Number | Publication Date |
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| CN107342227A CN107342227A (en) | 2017-11-10 |
| CN107342227B true CN107342227B (en) | 2020-07-17 |
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Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007165780A (en) * | 2005-12-16 | 2007-06-28 | Toshiba Corp | Semiconductor device |
| CN103855015B (en) * | 2012-11-30 | 2020-03-06 | 中国科学院微电子研究所 | FinFET and manufacturing method thereof |
| CN105826194A (en) * | 2015-01-07 | 2016-08-03 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and formation method thereof |
| US9824943B2 (en) * | 2015-10-20 | 2017-11-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor structure and method for forming the same |
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