CN110071175A - FinFET and its manufacturing method - Google Patents

FinFET and its manufacturing method Download PDF

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Publication number
CN110071175A
CN110071175A CN201910373585.4A CN201910373585A CN110071175A CN 110071175 A CN110071175 A CN 110071175A CN 201910373585 A CN201910373585 A CN 201910373585A CN 110071175 A CN110071175 A CN 110071175A
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layer
semiconductor
fin structure
semiconductor devices
dopant
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朱慧珑
许淼
梁擎擎
尹海洲
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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Priority to CN201910373585.4A priority Critical patent/CN110071175A/en
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    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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    • H01L29/107—Substrate region of field-effect devices
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    • H01L29/7856—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with an non-uniform gate, e.g. varying doping structure, shape or composition on different sides of the fin, or different gate insulator thickness or composition on opposing fin sides

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Abstract

Disclose a kind of semiconductor devices.The semiconductor devices includes: semiconductor substrate；The semiconductor fin structure formed on a semiconductor substrate；And the dopant layer formed on fin structure side wall, wherein the top surface of dopant layer is lower than the top surface of semiconductor fin structure；And formation and position break-through trapping layer corresponding with dopant layer in fin structure.

Description

FinFET and its manufacturing method
The application is the hair of entitled " FinFET and its manufacturing method " submitted to Patent Office of the People's Republic of China on November 30th, 2012 The divisional application of bright patent application No.201210507134.3.
Technical field
The present invention relates to semiconductor technologies, more particularly, to FinFET and preparation method thereof.
Background technique
As the size of semiconductor devices is smaller and smaller, short-channel effect is further obvious.In order to inhibit short-channel effect, mention The FinFET formed in SOI wafer or bulk semiconductor substrate is gone out.FinFET includes the fin (fin) in semiconductor material The intermediate channel region formed, and the source/drain region formed at fin both ends.Gate electrode surrounds ditch in two sides of channel region Road area (i.e. double-gate structure), to form inversion layer on each side of channel.Due to entire channel region can by the control of grid, Therefore can play the role of inhibiting short-channel effect.
In batch production, compared with using SOI wafer, using semiconductor substrate manufacture FinFET cost efficiency more Height, to be widely used.However, the height of semiconductor fin is difficult to control in the FinFET using semiconductor substrate, and The conductive path via semiconductor substrate is likely to form between source region and drain region, to lead to the problem of leakage current.
Doping break-through trapping layer (punch-through-stopper layer) is formed below semiconductor fin, it can be with Reduce the leakage current between source region and drain region.However, the ion implanting executed to form break-through trapping layer may partly led Undesirable dopant is introduced in the channel region of body fin.This it is additional doping so that in the channel region of FinFET there is with The fluctuation of machine doping concentration.
Due to the height change and random doping fluctuation of concentration of semiconductor fin, the threshold voltage of FinFET is undesirably sent out Raw random variation.
Summary of the invention
The purpose of the present invention is reducing the leakage current between source region and drain region in the FinFET based on semiconductor substrate, and And reduce the random variation of threshold voltage.
According to an aspect of the present invention, a kind of manufacturing semiconductor devices are provided, comprising: semiconductor substrate；It is served as a contrast in semiconductor The semiconductor fin structure formed on bottom；And the dopant layer formed on fin structure side wall, wherein the top of dopant layer Face is lower than the top surface of semiconductor fin structure；And formation and position break-through resistance corresponding with dopant layer in fin structure Only layer.
In FinFET of the invention, semiconductor fin and semiconductor substrate are separated using doping break-through trapping layer, from And the drain current path between source region and drain region via semiconductor substrate can be disconnected.It, can during forming the FinFET To avoid the undesirable doping to semiconductor fin using top protection layer and/or side wall protective layer, so as to reduce threshold The random variation of threshold voltage.In a preferred embodiment, the source region formed in stress layer and drain region can be to half Channel region in conductor fin applies suitable stress to provide the mobility of carrier.In another or further preferred reality Apply in example, using rear grid technique formed grid stack, thus obtain high quality gate-dielectric and desired work function.
Detailed description of the invention
By referring to the drawings to the description of the embodiment of the present invention, above-mentioned and other purposes of the invention, feature and Advantage will be apparent from, in the accompanying drawings:
Fig. 1-11 is each stage of the method for the manufacturing semiconductor devices for showing first embodiment according to the present invention Semiconductor structure schematic diagram.
Figure 12-13 shows a part of stage of the method for the manufacturing semiconductor devices of second embodiment according to the present invention Semiconductor structure schematic diagram.
Figure 14-16 shows a part of stage of the method for the manufacturing semiconductor devices of third embodiment according to the present invention Semiconductor structure schematic diagram.
Figure 17-20 shows a part of stage of the method for the manufacturing semiconductor devices of fourth embodiment according to the present invention Semiconductor structure schematic diagram.
Figure 21-22 shows a part of stage of the method for the manufacturing semiconductor devices of fifth embodiment according to the present invention Semiconductor structure schematic diagram.
Figure 23 shows a part of stage of the method for the manufacturing semiconductor devices of sixth embodiment according to the present invention The schematic diagram of semiconductor structure.
Specific embodiment
Hereinafter reference will be made to the drawings, and the present invention will be described in more detail.In various figures, identical element is using similar attached Icon is remembered to indicate.For the sake of clarity, the various pieces in attached drawing are not necessarily to scale.
For brevity, the semiconductor structure obtained after several steps can be described in a width figure.
It should be appreciated that being known as being located at another floor, another area when by a floor, a region in the structure of outlines device When domain " above " or " top ", can refer to above another layer, another region, or its with another layer, it is another Also comprising other layers or region between a region.Also, if device overturn, this layer, a region will be located at it is another Layer, another region " following " or " lower section ".
If will use " directly exist ... herein to describe located immediately at another layer, another region above scenario Above " or " ... abut above and therewith " form of presentation.
In this application, term " semiconductor structure " refers to entire half formed in each step of manufacturing semiconductor devices The general designation of conductor structure, including all layers formed or region.It is described hereinafter of the invention many specific thin Section, such as structure, material, size, treatment process and the technology of device, to be more clearly understood that the present invention.But as ability The technical staff in domain it will be appreciated that as, can not realize the present invention according to these specific details.
Unless hereinafter particularly pointing out, the various pieces of FinFET can be by material well known to those skilled in the art It constitutes.Semiconductor material is for example including Group III-V semiconductor, such as GaAs, InP, GaN, SiC and IV race semiconductor, as Si, Ge.Grid conductor can be formed by capableing of conductive a variety of materials, such as metal layer, doped polysilicon layer or including metal layer With the stacked gate conductor of doped polysilicon layer either other conductive materials, for example, TaC, TiN, TaTbN, TaErN, TaYbN, TaSiN, HfSiN, MoSiN, RuTax, NiTax, MoNx, TiSiN, TiCN, TaAlC, TiAlN, TaN, PtSix, Ni3The combination of Si, Pt, Ru, Ir, Mo, HfRu, RuOx and the various conductive materials.Gate-dielectric can be by SiO2Or dielectric Constant is greater than SiO2Material constitute, for example including oxide, nitride, oxynitride, silicate, aluminate, titanate, In, oxide is for example including SiO2、HfO2、ZrO2、Al2O3、TiO2、La2O3, nitride is for example including Si3N4, silicate is for example Including HfSiOx, aluminate is for example including LaAlO3, titanate is for example including SrTiO3, oxynitride is for example including SiON.And And gate-dielectric can not only be formed by material well known to those skilled in the art, it can also be using the use of exploitation in the future In the material of gate-dielectric.
The present invention can be presented in a variety of manners, some of them example explained below.
Referring to Fig.1-11 describe first embodiment according to the present invention manufacturing semiconductor devices method example flow, Wherein, the top view of semiconductor structure and the interception position of sectional view are shown in Figure 10 a-11a, in Fig. 1-9,10b-11b In show semiconductor fin width direction ascender line A-A interception semiconductor structure sectional view, show in Figure 10 c-11c Out in the sectional view of the A length direction ascender line B-B of the semiconductor fin semiconductor structure intercepted.
As shown in Figure 1, by known depositing operation, such as electron beam evaporation (EBM), chemical vapor deposition (CVD), atom Layer deposition (ALD), sputtering etc. form top protection layer 102 (for example, nitridation on semiconductor substrate 101 (such as Si substrate) Silicon).In one example, top protection layer 102 is, for example, the silicon nitride layer that thickness is about 50-100nm.As will hereafter retouch It states, semiconductor fin will be formed in semiconductor substrate 101.
Then, for example, by be spin-coated on top protection layer 102 formed photoresist layer PR1, and by including Photoresist layer PR1 is formed the shape (for example, band) for being used to limit semiconductor fin by the photoetching process of exposure and imaging Pattern.
Using photoresist layer PR1 as mask, by dry etching, such as ion beam milling etching, plasma etching, reaction Ion(ic) etching, laser ablation, or by using the wet etching of etchant solutions, remove the exposed portion of top protection layer 102 Point, and further etching semiconductor substrate 101 is to scheduled depth, as shown in Figure 2.It, can be with by the time of control etching The etch depth in semiconductor substrate 101 is controlled, to form opening in semiconductor substrate 101, and is limited between opening Determine ridge.Top protection layer 102 is located on the top surface of ridge.
Then, by dissolving or being ashed removal photoresist layer PR1 in a solvent.Pass through above-mentioned known deposition work Skill forms the first insulating layer 103 (for example, silica), in filling semiconductor substrate 101 on the surface of semiconductor structure Opening.In one example, made using suitable depositing operation (such as high density plasma CVD HDP-CVD) The thickness for obtaining part of first insulating layer 103 in opening is greater than the first insulating layer 103 and is located at the part on top protection layer 102 Thickness.In another example, the thickness that the first insulating layer 103 is located at the part on top protection layer 102 may be too big, can To pass through the surface of additional chemically mechanical polishing (CMP) smooth semiconductor structure, thus reduce the thickness of the part, or with Top protection layer 102 completely removes the part as stop-layer.
Using top protection layer 102 be used as hard mask, by selectivity etch process (for example, reactive ion etching), The first insulating layer of etch-back 103, as shown in Figure 3.The etching not only removes the first insulating layer 103 and is located on top protection layer 102 Part, and reduce the first insulating layer 103 be located at opening in part thickness.The time of etching is controlled, so that first is exhausted Edge layer 103 is located at the part in opening and is used as separation layer, and limits the depth of opening.The top of opening exposure ridge Side, and the depth being open should be substantially equal to the height of semiconductor fin to be formed.
Then, by above-mentioned known depositing operation, conformal nitride layer (example is formed on the surface of semiconductor structure Such as, silicon nitride).In one example, the thickness of the nitride layer is about 10-20nm.
By anisotropic etch process (for example, reactive ion etching), nitride layer is removed in the first insulating layer 103 Exposed surface on the part that is laterally extended so that nitride layer is located at the reservation of the vertical component on the side of ridge, thus Side wall protective layer 104 is formed, as shown in Figure 4.As a result, top protection layer 102 is covered at the top of ridge, the top of ridge Side be covered with side wall protective layer 104, the side of the lower part of ridge and the first insulating layer 103 are adjacent.
Then, hard mask is used as using top protection layer 102 and side wall protective layer 104, passes through the etch process of selectivity (for example, reactive ion etching), the first insulating layer of etch-back 103, as shown in Figure 5.The etching reduces the first insulating layer 103 Thickness, and a part of the side of the lower part of exposure ridge.The time for controlling etching, so that the exposure of the lower part of ridge The height h (i.e. the reduction amount of the thickness of the first insulating layer 103) of side is scheduled value.
Then, conformal doping is formed using conformal doping (conformal doping) on the surface of a semiconductor substrate Oxidant layer 105, as shown in Figure 6.Dopant layer 105 includes top protection layer 102, side wall protective layer 104, the first insulating layer 103 The superficial layer comprising dopant in the exposed side of surface and the lower part of ridge.
Different dopants can be used for different types of FinFET.P-type doping can be used in N-type FinFET N type dopant, such as P, As can be used in agent, such as B in p-type FinFET.Dopant layer 105 will be used to form doping and wear Logical trapping layer, so that the doping type in the doping type of break-through trapping layer and source region and drain region is on the contrary, so as to disconnect source region Drain current path between drain region.
Then, by above-mentioned known depositing operation, 106 (example of second insulating layer is formed on the surface of semiconductor structure Such as, silica).Hard mask is used as using top protection layer 102 and side wall protective layer 104, passes through the etch process (example of selectivity Such as, reactive ion etching), etch-back second insulating layer 106, as shown in Figure 7.The etching reduces the thickness of second insulating layer 106 Degree.The time of etching is controlled, so that the top surface of second insulating layer 106 is at least above the bottom of side wall protective layer 104, thus Second insulating layer 106 at least covers the part that dopant layer 105 is located on the side of ridge.
Then, by the etch process (for example, reactive ion etching) of selectivity, relative to second insulating layer 106, removal Top protection layer 102 and side wall protective layer 104, as shown in Figure 8.The etching also removes dopant layer 105 and is located at top protection Part on the surface of layer 102 and side wall protective layer 104.
Then, using thermal annealing, dopant layer 105 is located to the part on the side of ridge and is pushed home into until even It is logical, to form doping break-through trapping layer 107 in the ridge of semiconductor substrate 101, as shown in Figure 9.The ridge is located at It adulterates the part on break-through trapping layer 107 and forms semiconductor fin 108.Also, semiconductor fin 108 and semiconductor substrate It is separated between 101 by doping break-through trapping layer 107.Due in the width direction of ridge, the dopant of thermal annealing push-in from Two sides are spread to centre, therefore there is the doping concentrations of the width direction along semiconductor fin point for doping break-through trapping layer 107 Cloth, so that the doping concentration of doping 107 middle section of break-through trapping layer is less than the doping concentration of both ends part.
Then, by above-mentioned known depositing operation, 109 (example of gate-dielectric is formed on the surface of semiconductor structure Such as, silicon oxide or silicon nitride).In one example, which is the silicon oxide layer of about 0.8-1.5nm thickness.Grid Dielectric 109 covers top surface and the side of semiconductor fin 108.
By above-mentioned known depositing operation, conductor layer is formed on the surface of semiconductor structure (for example, doped polycrystalline Silicon).If desired, can be chemically-mechanicapolish polished to conductor layer (CMP), to obtain even curface.
Using photoresist mask, by the patterned grid conductor 110 across semiconductor fin of the conductor layer, and The expose portion for further removing gate-dielectric 109, as shown in Figure 10 a, 10b and 10c.Grid conductor 110 and grid electricity are situated between Matter 109 is formed together grid stacking.In the example shown in Figure 10 a, 10b and 10c, the shape of grid conductor 110 is band, and Extend along the direction vertical with the length of semiconductor fin.
Then, by above-mentioned known depositing operation, nitride layer is formed on the surface of semiconductor structure.Show at one In example, which is the silicon nitride layer of thickness about 5-20nm.By anisotropic etch process (for example, reactive ion Etching), remove the part of nitride layer being laterally extended so that nitride layer be located at it is vertical on the side of grid conductor 110 Part retains, to form grid curb wall 111.Nitride layer generally, due to form factor, on 108 side of semiconductor fin Thickness is smaller than the nitride layer thickness on the side of grid conductor 110, partly leads to can completely remove in the etching step Nitride layer on 108 side of body fin.Otherwise, the nitride layer thickness on 108 side of semiconductor fin may interfere with greatly very much Form grid curb wall.Nitride layer on 108 side of semiconductor fin can further be removed using additional mask.
Etching exposure semiconductor fin 108 is located at top surface and the side of the part of 110 two sides of grid conductor.So Afterwards, source region and drain region can be formed in the expose portion of semiconductor fin 103 according to conventional technique.
2-13 describes a part of rank of the method for the manufacturing semiconductor devices of second embodiment according to the present invention referring to Fig.1 The example flow of section, there is shown with the sectional views of the semiconductor structure intercepted in the width direction of semiconductor fin.
According to second embodiment, following steps are executed after step shown in Fig. 5.
Be pushed into (gas phase drive-in) by gas phase so that dopant from the exposed side of the lower part of ridge to Inside diffusion is until be connected to, so that doping break-through trapping layer 107 is formed in the ridge of semiconductor substrate 101, such as Figure 12 institute Show.The part that the ridge is located on doping break-through trapping layer 107 forms semiconductor fin 108.Also, semiconductor fin It is separated between 108 and semiconductor substrate 101 by doping break-through trapping layer 107.Since in the width direction of ridge, gas phase is pushed away The dopant entered is spread from two sides to centre, and therefore, there is the width directions along semiconductor fin for doping break-through trapping layer 107 Doping concentration distribution so that doping 107 middle section of break-through trapping layer doping concentration be less than both ends part doping concentration.
In gas phase push-in, different dopants can be used for different types of FinFET.It can in N-type FinFET To use P-type dopant, such as B, N type dopant, such as P, As can be used in p-type FinFET.Adulterate break-through trapping layer 107 doping type and source region and the doping type in drain region are on the contrary, so as to disconnect the electric leakage flow path between source region and drain region Diameter.
Then, by above-mentioned known depositing operation, 106 (example of second insulating layer is formed on the surface of semiconductor structure Such as, silica).Hard mask is used as using top protection layer 102 and side wall protective layer 104, passes through the etch process (example of selectivity Such as, reactive ion etching), etch-back second insulating layer 106.The etching reduces the thickness of second insulating layer 106.Control etching Time so that the top surface of second insulating layer 106 at least above adulterate break-through trapping layer 107 and semiconductor substrate 101 it Between interface.
Then, by the etch process (for example, reactive ion etching) of selectivity, relative to second insulating layer 106, removal Top protection layer 102 and side wall protective layer 104, as shown in figure 13.
Then, continue step shown in Figure 10 and 11 to form grid stacking, grid curb wall, source region and drain region.
4-16 describes a part of rank of the method for the manufacturing semiconductor devices of third embodiment according to the present invention referring to Fig.1 The example flow of section, there is shown with the sectional views of the semiconductor structure intercepted in the width direction of semiconductor fin.
According to third embodiment, following steps are executed after step shown in Fig. 5.
Then, hard mask is used as using top protection layer 102 and side wall protective layer 104, is injected by angle-tilt ion, in ridge Dopant layer 105 is formed in the exposed side of the lower part of shape object, as shown in figure 14.The parameter of ion implanting is controlled, so that doping Agent does not pass through top protection layer 102 and side wall protective layer 104 and enters in the other parts of ridge.Ion is infused in Figure 14 Enter to be described as in two directions progress (as shown by arrows).It should be appreciated that the ion implanting may include in the first step Ion implanting is carried out along first direction, carries out ion implanting in a second direction in the second step.
In ion implanting, different dopants can be used for different types of FinFET.It can in N-type FinFET To use P-type dopant, such as B, N type dopant, such as P, As can be used in p-type FinFET.Dopant layer 105 will be used Adulterate break-through trapping layer in being formed so that the doping type in the doping type of break-through trapping layer and source region and drain region on the contrary, to The drain current path between source region and drain region can be disconnected.
Then, by above-mentioned known depositing operation, 106 (example of second insulating layer is formed on the surface of semiconductor structure Such as, silica).Hard mask is used as using top protection layer 102 and side wall protective layer 104, passes through the etch process (example of selectivity Such as, reactive ion etching), etch-back second insulating layer 106, as shown in figure 15.The etching reduces the thickness of second insulating layer 106 Degree.The time of etching is controlled, so that the top surface of second insulating layer 106 is at least above the bottom of side wall protective layer 104, thus Second insulating layer 106 at least covers dopant layer 105.
Then, by the etch process (for example, reactive ion etching) of selectivity, relative to second insulating layer 106, removal Top protection layer 102 and side wall protective layer 104.Using thermal annealing, dopant layer 105 is located to the part on the side of ridge It is pushed home into until connection, adulterates break-through trapping layer 107 to be formed in the ridge of semiconductor substrate 101, such as Figure 16 institute Show.The part that the ridge is located on doping break-through trapping layer 107 forms semiconductor fin 108.Also, semiconductor fin It is separated between 108 and semiconductor substrate 101 by doping break-through trapping layer 107.Since in the width direction of ridge, gas phase is pushed away The dopant entered is spread from two sides to centre, therefore there is the width directions along semiconductor fin for doping break-through trapping layer 107 Doping concentration distribution so that doping 107 middle section of break-through trapping layer doping concentration be less than both ends part doping concentration.
Then, continue step shown in Figure 10 and 11 to form grid stacking, grid curb wall, source region and drain region.
7-20 describes a part of rank of the method for the manufacturing semiconductor devices of fourth embodiment according to the present invention referring to Fig.1 The example flow of section, there is shown with the sectional views of the semiconductor structure intercepted in the width direction of semiconductor fin.
As shown in figure 17, the predetermined depth formation by ion implanting in semiconductor substrate 101 (such as Si substrate) is mixed Miscellaneous area, to form doping break-through trapping layer 107.Semiconductor substrate 101 is located at the part on doping break-through trapping layer 107 will Form semiconductor layer 108 '.Also, it is separated between semiconductor layer 108 ' and semiconductor substrate 101 by doping break-through trapping layer 107. Adulterating break-through trapping layer 107, there is the doping concentration distributions of the width direction along semiconductor fin, so that doping break-through prevents The doping concentration of 107 middle section of layer is less than the doping concentration of both ends part.
In ion implanting, different dopants can be used for different types of FinFET.It can in N-type FinFET To use P-type dopant, such as B, N type dopant, such as P, As can be used in p-type FinFET.Adulterate break-through trapping layer 107 doping type and source region and the doping type in drain region are on the contrary, so as to disconnect the electric leakage flow path between source region and drain region Diameter.
By above-mentioned known depositing operation, top protection layer 102 is formed on semiconductor layer 108 ' (for example, nitridation Silicon), as shown in figure 17.
Then, for example, by be spin-coated on top protection layer 102 formed photoresist layer PR1, and by including Photoresist layer PR1 is formed the shape (for example, band) for being used to limit semiconductor fin by the photoetching process of exposure and imaging Pattern.
Using photoresist layer PR1 as mask, by dry etching, such as ion beam milling etching, plasma etching, reaction Ion(ic) etching, laser ablation, or by using the wet etching of etchant solutions, remove from top to bottom top protection layer 102, Semiconductor layer 108 ', the expose portion for adulterating break-through trapping layer 107, and semiconductor substrate 101 can be further etched to pre- Fixed depth, as shown in figure 18.By the time of control etching, the etch depth in semiconductor substrate 101 can control, thus Opening is formed in semiconductor substrate 101.Semiconductor layer 108 ' is located at the part between opening and retains to form semiconductor fin 108.Top protection layer 102 is located on the surface of semiconductor fin 108.
Then, by dissolving or being ashed removal photoresist layer PR1 in a solvent.Pass through above-mentioned known deposition work Skill forms the first insulating layer 103 (for example, silica), in filling semiconductor substrate 101 on the surface of semiconductor structure Opening.In one example, made using suitable depositing operation (such as high density plasma CVD HDP-CVD) The thickness for obtaining part of first insulating layer 103 in opening is greater than the first insulating layer 103 and is located at the part on top protection layer 102 Thickness.In another example, the thickness that the first insulating layer 103 is located at the part on top protection layer 102 may be too big, can To pass through the surface of additional chemically mechanical polishing (CMP) smooth semiconductor structure, thus reduce the thickness of the part, or with Top protection layer 102 completely removes the part as stop-layer.
Using top protection layer 102 be used as hard mask, by selectivity etch process (for example, reactive ion etching), The first insulating layer of etch-back 103.The etching reduces the thickness of the first insulating layer 103.The time of etching is controlled, so that first is exhausted The top surface of edge layer 103 is at least above the interface adulterated between break-through trapping layer 107 and semiconductor substrate 101.
Then, by the etch process (for example, reactive ion etching) of selectivity, relative to the first insulating layer 103, removal Top protection layer 102, as shown in figure 20.
Then, continue step shown in Figure 10 and 11 to form grid stacking, grid curb wall, source region and drain region.It should be noted that It does not need to form side wall protective layer 104 and second insulating layer 106 in this embodiment.
A part of rank of the method for the manufacturing semiconductor devices of fifth embodiment according to the present invention is described referring to Figure 21-22 The example flow of section, wherein the top view of semiconductor structure and the interception position of sectional view are shown in Figure 21 a-22a, Sectional view in the semiconductor structure of the width direction ascender line A-A interception of semiconductor fin is shown in Figure 21 b-22b, is being schemed Sectional view in the semiconductor structure of the A length direction ascender line B-B interception of semiconductor fin is shown in 21c-22c.
Execute step shown in Figure 21 and 22 further according to the preferred embodiment, after the step shown in Figure 11 with shape At stress layer, and source region and drain region are formed in stress layer.
By above-mentioned known etch process (for example, reactive ion etching), selectively gone relative to grid curb wall 111 Except semiconductor fin 108 is located at the part of 110 two sides of grid conductor, as shown in Figure 21 a, 21b and 21c.The etching can mix The top surface of miscellaneous break-through trapping layer 107 stops, or further a part (such as Figure 21 c of removal doping break-through trapping layer 107 It is shown).The etching is also possible to a part of removal grid conductor 110.Since the thickness of grid conductor 110 can compare semiconductor fin The height of piece 108 is much larger, and therefore, which only only reduces the thickness of grid conductor 110, leads without completely removing grid Body 110 (as shown in Figure 21 c).
Then, by above-mentioned known depositing operation, the epitaxial growth stress layer on doping break-through trapping layer 107 112, as shown in Figure 22 a, 22b and 22c.Stress layer 112 is also formed on grid conductor 110.The stress layer 112 Thickness should be sufficiently large, so that the top surface of stress layer 112 is greater than or equal to the top surface of semiconductor fin 108, To maximize the stress applied in semiconductor fin 108.
Different stress layers 112 can be formed for different types of FinFET.By stress layer to The channel region of FinFET applies suitable stress, the mobility of carrier can be improved, to reduce conducting resistance and improve device The switching speed of part.For this purpose, source region and drain region are formed using the semiconductor material different from the material of semiconductor fin 108, it can To generate desired stress.For N-type FinFET, the content for the C that stress layer 112 is e.g. formed on a si substrate is about The Si:C layer of atomic percent 0.2-2% applies tensile stress to channel region along the longitudinal direction of channel region.For p-type FinFET, the content for the Ge that stress layer 112 is e.g. formed on a si substrate are about the SiGe of atomic percent 15-75% Layer applies compression to channel region along the longitudinal direction of channel region.
A part of stage of the method for the manufacturing semiconductor devices of sixth embodiment according to the present invention is described referring to Figure 23 Example flow, wherein the top view of semiconductor structure and the interception position of sectional view are shown in Figure 23 a, in Figure 23 b Sectional view in the semiconductor structure of the width direction ascender line A-A interception of semiconductor fin is shown, is shown in Figure 23 c half The sectional view of the semiconductor structure of the A length direction ascender line B-B interception of conductor fin.
Execute step shown in Figure 23 further according to the preferred embodiment, after the step shown in Figure 22 to form packet It includes replacement gate conductor and substitutes the alternative gate stacking of gate medium.
By above-mentioned known depositing operation, third insulating layer 113 is formed on the surface of semiconductor structure (for example, oxygen SiClx).Semiconductor structure is chemically-mechanicapolish polished, to obtain even curface.The chemically mechanical polishing eliminates third Insulating layer 113 is located at a part of 110 top of grid conductor, to expose the stress layer 112 of 110 top of grid conductor With grid curb wall 111.Further, which can remove one of stress layer 112 and grid curb wall 111 Point.
Hard mask is used as using third insulating layer 113 and grid curb wall 111, by above-mentioned known etch process (such as Reactive ion etching) the stress layer 112 of 110 top of grid conductor is removed, and grid conductor 110 is further removed, To form gate openings.It is alternatively possible to which further removal gate-dielectric 107 is located at the part of gate openings bottom.It presses According to rear grid technique, replacement gate dielectric 114 is formed in gate openings (for example, HfO2) and 115 (example of replacement gate conductor Such as, TiN), as shown in Figure 23 a, 23b and 23c.Replacement gate conductor 115 and replacement gate dielectric 114 are formed together alternative gate It stacks.
It can be on obtained semiconductor structure after forming source region and drain region according to above-mentioned each embodiment Interlayer insulating film, the through-hole in interlayer insulating film, the wiring positioned at interlayer insulating film upper surface or electrode are formed, thus complete At the other parts of FinFET.
In the above description, the technical details such as composition, the etching of each layer are not described in detail.But It will be appreciated by those skilled in the art that can be by various technological means, come layer, the region etc. for forming required shape.In addition, being Formation same structure, those skilled in the art can be devised by and process as described above not fully identical method. In addition, although respectively describing each embodiment above, but it is not intended that the measure in each embodiment cannot be advantageous Ground is used in combination.
The embodiment of the present invention is described above.But the purpose that these embodiments are merely to illustrate that, and It is not intended to limit the scope of the invention.The scope of the present invention is limited by appended claims and its equivalent.This hair is not departed from Bright range, those skilled in the art can make a variety of alternatives and modifications, these alternatives and modifications should all fall in of the invention Within the scope of.

Claims (13)

1. a kind of semiconductor devices, comprising:
Semiconductor substrate；
The semiconductor fin structure formed on a semiconductor substrate；And
The dopant layer formed on fin structure side wall, wherein the top surface of dopant layer is lower than the top of semiconductor fin structure Face；And
Formation and position break-through trapping layer corresponding with dopant layer in fin structure.
2. semiconductor devices according to claim 1, wherein break-through trapping layer and fin structure be located at break-through trapping layer it On part between have doping concentration transition zone, thickness and fin of the doping concentration transition zone in fin structure short transverse The half of the width of shape structure has same order.
3. semiconductor devices according to claim 2, wherein the thickness of doping concentration transition zone and the width of fin structure Half it is suitable.
4. semiconductor devices according to claim 1, wherein break-through trapping layer and fin structure be located at break-through trapping layer it On part between have doping concentration interface.
5. semiconductor devices described in any one of -4 according to claim 1, wherein width of the break-through trapping layer along fin structure Direction has doping concentration distribution, so that the doping concentration of break-through trapping layer middle section is lower than the doping concentration of both ends part.
6. semiconductor devices according to claim 1, wherein fin structure and semiconductor substrate one.
7. semiconductor devices according to claim 1, further includes:
Formation and top surface are lower than the separation layer of the top surface of semiconductor fin structure on a semiconductor substrate, wherein dopant layer exists On separation layer.
8. semiconductor devices according to claim 1, wherein dopant layer includes extending on the side of fin structure Part and the part extended in the lateral surfaces of semiconductor substrate.
9. semiconductor devices according to claim 8, further includes: the separation layer in the dopant layer.
10. the semiconductor devices according to claim 7 or 9, further includes:
The grid across fin structure formed on separation layer stack, and it includes gate dielectric layer and grid conductor layer which, which stacks,；
The source-drain area formed in the semiconductor fin structure for being located at grid stacking two sides.
11. semiconductor devices according to claim 1, wherein
The semiconductor devices is N-type device, includes P-type dopant in the dopant layer；Or
The semiconductor devices is P-type device, includes N type dopant in the dopant layer.
12. semiconductor devices according to claim 11, wherein the P-type dopant includes B, the N type dopant packet Include P or As.
13. semiconductor devices according to claim 1, wherein the side wall of dopant layer and fin structure is substantially conformal.
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CN105304715B (en) 2016-08-17
CN103855015B (en) 2020-03-06
CN107863299B (en) 2021-06-15
CN105097555A (en) 2015-11-25
CN105118863A (en) 2015-12-02
CN103855015A (en) 2014-06-11
CN105304715A (en) 2016-02-03
CN105304716A (en) 2016-02-03
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CN105261651B (en) 2018-11-27
CN105097555B (en) 2017-03-29

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