CN103985712B - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
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- CN103985712B CN103985712B CN201310050125.0A CN201310050125A CN103985712B CN 103985712 B CN103985712 B CN 103985712B CN 201310050125 A CN201310050125 A CN 201310050125A CN 103985712 B CN103985712 B CN 103985712B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 205
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 238000000034 method Methods 0.000 title claims description 39
- 239000004020 conductor Substances 0.000 claims abstract description 103
- 238000002955 isolation Methods 0.000 claims abstract description 43
- 239000000758 substrate Substances 0.000 claims abstract description 39
- 230000005669 field effect Effects 0.000 claims abstract description 35
- VMXJCRHCUWKQCB-UHFFFAOYSA-N NPNP Chemical compound NPNP VMXJCRHCUWKQCB-UHFFFAOYSA-N 0.000 claims abstract description 10
- 230000004888 barrier function Effects 0.000 claims description 29
- 239000003792 electrolyte Substances 0.000 claims description 17
- 230000015572 biosynthetic process Effects 0.000 claims description 14
- 239000002019 doping agent Substances 0.000 claims description 12
- 238000002347 injection Methods 0.000 claims description 3
- 239000007924 injection Substances 0.000 claims description 3
- 239000003989 dielectric material Substances 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 158
- 238000005530 etching Methods 0.000 description 24
- 238000000151 deposition Methods 0.000 description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 12
- 150000002500 ions Chemical class 0.000 description 11
- 239000000463 material Substances 0.000 description 11
- 150000004767 nitrides Chemical class 0.000 description 11
- 230000008569 process Effects 0.000 description 11
- 239000000203 mixture Substances 0.000 description 9
- 238000001020 plasma etching Methods 0.000 description 9
- 229910052814 silicon oxide Inorganic materials 0.000 description 9
- 230000000694 effects Effects 0.000 description 8
- 229910052581 Si3N4 Inorganic materials 0.000 description 7
- 238000011065 in-situ storage Methods 0.000 description 6
- 239000011229 interlayer Substances 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
- 238000004544 sputter deposition Methods 0.000 description 6
- 229910021419 crystalline silicon Inorganic materials 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 230000008901 benefit Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000005457 optimization Methods 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 4
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 3
- 229910052681 coesite Inorganic materials 0.000 description 3
- 230000001276 controlling effect Effects 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 3
- 229910052906 cristobalite Inorganic materials 0.000 description 3
- 230000005611 electricity Effects 0.000 description 3
- 229910052732 germanium Inorganic materials 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 229910052682 stishovite Inorganic materials 0.000 description 3
- 229910052905 tridymite Inorganic materials 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 229910005542 GaSb Inorganic materials 0.000 description 2
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 2
- 229910000673 Indium arsenide Inorganic materials 0.000 description 2
- 229910015617 MoNx Inorganic materials 0.000 description 2
- 229910003217 Ni3Si Inorganic materials 0.000 description 2
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 2
- 229910019897 RuOx Inorganic materials 0.000 description 2
- 229910004200 TaSiN Inorganic materials 0.000 description 2
- 229910010037 TiAlN Inorganic materials 0.000 description 2
- 229910008482 TiSiN Inorganic materials 0.000 description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 2
- YQNQNVDNTFHQSW-UHFFFAOYSA-N acetic acid [2-[[(5-nitro-2-thiazolyl)amino]-oxomethyl]phenyl] ester Chemical compound CC(=O)OC1=CC=CC=C1C(=O)NC1=NC=C([N+]([O-])=O)S1 YQNQNVDNTFHQSW-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 238000005566 electron beam evaporation Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 2
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 2
- 229910052741 iridium Inorganic materials 0.000 description 2
- QRXWMOHMRWLFEY-UHFFFAOYSA-N isoniazide Chemical compound NNC(=O)C1=CC=NC=C1 QRXWMOHMRWLFEY-UHFFFAOYSA-N 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 229910052707 ruthenium Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000002904 solvent Substances 0.000 description 2
- 230000001629 suppression Effects 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 229910002244 LaAlO3 Inorganic materials 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 229910002370 SrTiO3 Inorganic materials 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 150000004645 aluminates Chemical class 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 238000000354 decomposition reaction Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000002305 electric material Substances 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000004969 ion scattering spectroscopy Methods 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum oxide Inorganic materials [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 1
- 238000000608 laser ablation Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000003801 milling Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000007800 oxidant agent Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- KTUFCUMIWABKDW-UHFFFAOYSA-N oxo(oxolanthaniooxy)lanthanum Chemical compound O=[La]O[La]=O KTUFCUMIWABKDW-UHFFFAOYSA-N 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 238000005549 size reduction Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
- 238000003079 width control Methods 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Disclosed are a semiconductor device and a method of manufacturing the same, the semiconductor device including: a semiconductor substrate; a back gate isolation structure in the semiconductor substrate; and adjacent field effect transistors on a back gate isolation structure, wherein each of the adjacent field effect transistors comprises a sandwich structure on the back gate isolation structure, the sandwich structure comprising a back gate conductor, semiconductor fins on both sides of the back gate conductor, and respective back gate dielectrics respectively separating the back gate conductor from the semiconductor fins, wherein the back gate isolation structure is used as a part of a conductive path of the back gate conductor of the adjacent field effect transistors, and a PNPN junction or a NPNP junction is formed between the back gate conductors of the adjacent field effect transistors. The semiconductor device adopts a back gate isolation structure, and different voltages are respectively applied to the back gates of one or more field effect transistors, so that the threshold voltage of each field effect transistor is correspondingly adjusted.
Description
Technical field
The present invention relates to semiconductor technology, more particularly, to the quasiconductor comprising fin (Fin)
Device and its manufacture method.
Background technology
With semiconductor technology development it is desirable to reduce semiconductor device size integrated to improve
Reduce power consumption while spending.In order to suppress the short-channel effect leading to due to size reduction, propose
The FinFET being formed in the SOI wafer or bulk semiconductor substrate.FinFET includes partly leading
The channel region of the intermediate formation of the fin of body material, and the source/drain region being formed at fin two ends.Grid
Electrode at least surrounds channel region (i.e. double-gate structure) in two sides of channel region, thus each in raceway groove
Inversion layer is formed on side.Because whole channel region can be controlled by grid, therefore, it is possible to play
The effect of suppression short-channel effect.In order to reduce because the power consumption leading to of leaking electricity is it is proposed that partly leading
UTBB (ultra-thin buried oxide body) type FET being formed in body substrate.UTBB type
FET includes ultrathin buried oxide skin(coating) in Semiconductor substrate, is located at ultrathin oxide buried regions
The front gate of top and source/drain region and the backgate below ultrathin buried oxide skin(coating).In work
In, by applying bias voltage to backgate, can be substantially reduced in the case of maintaining speed constant
Power consumption.
Despite the presence of respective advantage, but without proposition is a kind of, two kinds of advantage is combined one
The semiconductor device rising, this is because form backgate to there are many difficulties in FinFET.?
Based in the FinFET of bulk semiconductor substrate, due to connecing of semiconductor fin and Semiconductor substrate
Contacting surface amasss very little, and the backgate being formed will lead to serious self-heating effect.Based on SOI wafer
In FinFET, problem that high cost is led to due to the expensive of SOI wafer.And,
SOI wafer formation backgate needs the ion implanting using precise control, exists through top semiconductor layer
The buried insulator layer injection region for backgate formed below, thus lead to technologic difficulty so that becoming
Product rate is low, and leads to device performance to fluctuate due to the unintentionally doping to channel region.
Content of the invention
It is an object of the invention to provide a kind of semiconductor device including backgate isolation structure, to improve
The regulating power of threshold voltage.
According to an aspect of the present invention, there is provided a kind of semiconductor device, including：Semiconductor substrate；
Backgate isolation structure in Semiconductor substrate；And the adjacent field effect on backgate isolation structure is brilliant
Body pipe, wherein, each of described adjacent field-effect transistor is included positioned at backgate isolation junction
Sandwich on structure, this sandwich includes backgate conductor, is located at partly leading of backgate conductor both sides
Body fin and the respective backgate electrolyte that backgate conductor and semiconductor fin are spaced one from,
Wherein, the conductive path of the backgate conductor as described adjacent field-effect transistor for the backgate isolation structure
The part in footpath, and, formed between the backgate conductor of described adjacent field-effect transistor
PNPN knot or NPNP knot.
According to a further aspect in the invention, there is provided a kind of manufacture semiconductor device method, including：
Form backgate isolation structure in the semiconductor substrate so that Semiconductor substrate is located at backgate isolation structure
The part of top forms semiconductor layer；And
Adjacent field-effect transistor is formed on backgate isolation structure, including：On the semiconductor layer
Form multiple mask layers；Form opening in of the top in the plurality of mask layer；?
Opening inwall forms another mask layer of side wall form；Using another mask layer described as hard
Mask, opening is passed through the plurality of mask layer and described semiconductor layer to extend to backgate isolation structure；
Form backgate electrolyte in opening inwall；Form backgate conductor in the opening；Form bag in the opening
Include the insulating cap of another mask layer described, this insulating cap covers backgate electrolyte and backgate is led
Body；Using insulating cap as hard mask, semiconductor layer pattern is turned to semiconductor fin；Wherein,
Backgate conductor, the semiconductor fin being formed by semiconductor layer being located at backgate conductor both sides and general
The respective backgate dielectric formation sandwich that backgate conductor and semiconductor fin are spaced one from, its
Backgate conductor is separated by middle insulating cap with front gate conductor, and wherein, backgate isolation structure is as described
A part for the conductive path of backgate conductor of adjacent field-effect transistor, and, in described phase
Form PNPN knot or NPNP knot between the adjacent backgate conductor of field-effect transistor.
The semiconductor device of the present invention includes adjacent with a respective side of two semiconductor fin
Backgate conductor.Because backgate conductor is not formed at below semiconductor fin, therefore can be as needed
Independently determine this backgate conductor and as the contact surface between the well region of a part for conductive path
Long-pending, with the self-heating effect avoiding backgate conductor to produce.And, due to formed backgate conductor when not
Need execution through the ion implanting of semiconductor fin, therefore can avoid to channel region unintentionally
Adulterate and lead to device performance to fluctuate.
This semiconductor device has combined the advantage of FinFET and UTBB type FET, on the one hand permissible
Controlled using backgate conductor or the dynamic threshold voltage adjusting semiconductor device, maintaining, speed is constant
In the case of be substantially reduced power consumption, on the other hand can using Fin suppress short-channel effect, contracting
The performance of semiconductor device is maintained during little semiconductor device.Therefore, this semiconductor device can subtract
The size of little semiconductor device is to improve reduction power consumption while integrated level.And, and this partly leads
The manufacture method of body device is compatible with existing semiconductor technology, thus low cost of manufacture.Adjacent
Form PNPN knot or NPNP knot between the backgate of field-effect transistor, so that adjacent field effect
The backgate of transistor separates, and can adjust the threshold voltage of field-effect transistor independently of each other.
Brief description
By the description to the embodiment of the present invention referring to the drawings, the present invention above-mentioned and other
Objects, features and advantages will be apparent from, in the accompanying drawings：
Fig. 1-13 shows the side manufacturing semiconductor device according to an embodiment of the invention
The schematic diagram of the semiconductor structure in each stage of method.
Figure 14-15 shows the manufacture semiconductor device according to present invention further optimization embodiment
The semiconductor structure in a part of stage of method schematic diagram.
Figure 16-18 shows the manufacture semiconductor device according to present invention further optimization embodiment
The semiconductor structure in a part of stage of method schematic diagram.
Figure 19 shows the decomposition diagram of semiconductor device according to a preferred embodiment of the invention.
Specific embodiment
It is more fully described the present invention hereinafter with reference to accompanying drawing.In various figures, identical element
To be represented using similar reference.For the sake of clarity, the various pieces in accompanying drawing are not pressed
Ratio is drawn.
For brevity, the quasiconductor that can obtain after several steps in a width in figure description
Structure.
It should be appreciated that in the structure of outlines device, when by one layer, region be referred to as located at another
One layer, another region " above " or when " top ", can refer to be located immediately at another layer, another
Above region, or also comprise other layers or region and another layer, another region between at it.
And, if device is overturn, this layer, region will positioned at another layer, another region " under
Face " or " lower section ".
If being located immediately at another layer, another region above scenario to describe, will adopt herein
With " directly existing ... above " or " ... adjoin above and therewith " form of presentation.
In this application, term " semiconductor structure " refers in each step manufacturing semiconductor device
The general designation of the whole semiconductor structure being formed, including all layers having been formed or region.Below
In describe many specific details of the present invention, the structure of such as device, material, size, place
Science and engineering skill and technology, to be more clearly understood that the present invention.But as those skilled in the art's energy
As enough understanding, the present invention can not be realized according to these specific details.
Unless hereinafter particularly pointed out, the various pieces of semiconductor device can be by the skill of this area
Material known to art personnel is constituted.Semi-conducting material for example includes Group III-V semiconductor, such as GaAs,
InP, GaN, SiC, and IV race quasiconductor, such as Si, Ge.Grid conductor can be by can lead
The various materials of electricity are formed, such as metal level, doped polysilicon layer or include metal level and doping
The stack gate conductor of polysilicon layer or other conductive materials, for example, TaC, TiN, TaTbN,
TaErN, TaYbN, TaSiN, HfSiN, MoSiN, RuTax, NiTax, MoNx, TiSiN,
TiCN、TaAlC、TiAlN、TaN、PtSix、Ni3Si、Pt、Ru、Ir、Mo、W、HfRu、
RuOx and the combination of described various conductive material.Gate dielectric can be by SiO2Or dielectric constant is big
In SiO2Material constitute, for example include oxide, nitride, oxynitride, silicate, aluminum
Hydrochlorate, titanate, wherein, oxide for example includes SiO2、HfO2、ZrO2、Al2O3、TiO2、
La2O3, nitride for example includes Si3N4, silicate for example includes HfSiOx, and aluminate for example wraps
Include LaAlO3, titanate for example includes SrTiO3, oxynitride for example includes SiON.And,
Gate dielectric not only can be formed by material well known to those skilled in the art, it would however also be possible to employ will
To develop the material for gate dielectric.
The present invention can present in a variety of manners, some of them example explained below.
Reference picture 1-13 describes the side manufacturing semiconductor device according to an embodiment of the invention
The example flow of method, wherein, shows top view and the sectional view of semiconductor structure in Figure 13 a
Interception position, in the width ascender line of semiconductor fin shown in Fig. 1-12 and 13b
The sectional view of the semiconductor structure that A-A intercepts, in the width of semiconductor fin shown in Figure 13 c
The sectional view of the semiconductor structure that direction ascender line B-B intercepts, in quasiconductor shown in Figure 13 d
The sectional view of the semiconductor structure that length direction ascender line C-C of fin intercepts.
The method starts from the Semiconductor substrate 101 of bulk.In block Semiconductor substrate 101
Form four well regions 102a, 102b, 103a and 103b.Well region 102a and 102b is laterally
Adjacent, well region 103a and 103b is laterally adjacent, and well region 103a and 103b is located at trap respectively
The top of area 102a and 102b.Semiconductor substrate 101 is located above well region 103a and 103b
Part forms semiconductor layer 104, and well region 102a, 102b, 103a and 103b are by quasiconductor
Layer 104 and Semiconductor substrate 101 separate.In Semiconductor substrate 101 formed well region 102a, 102b,
The technique of 103a and 103b is known, for example with ion implanting thus shape in the semiconductor layer
Become doped region and then annealed to activate the dopant in doped region.In one example, half
Form well region 102a, 102b, 103a and 103b in conductor substrate 101 to include in Semiconductor substrate
Form well region 102a in 101 part, be located above well region 102a in Semiconductor substrate 101
Partly middle formation well region 103a, the partly middle shape adjoining with well region 102a in Semiconductor substrate 101
Become well region 102b, be located at the partly middle formation well region above well region 102b in Semiconductor substrate 101
103b.In one example, the concentration of dopant atoms of well region 102a, 102b, 103a and 103b
It is respectively about 1016cm-3To 1019cm-3.Just as will be described, in well region 103a and 103b
The FET of opposite types will be formed in the semiconductor layer 104 of top.Then, according to conventional technique
Form shallow trench isolation (STI) 105, to limit the active area of FET and to separate adjacent FET.
Shallow trench isolation 105 extends through semiconductor layer 104, well region 103a and 103b, and reaches trap
Desired depth in area 102a and 102b.Trench isolations 105 not only separate the half of adjacent FET
Conductor layer 104, and separate well region 103a and 103b so that adjacent FET separates, only
Only exist adjacent well region 102a and 102b.
For p-type FET, can be formed N-type well region 103a, 103b and P type trap zone 102a,
102b, for N-type FET, can be formed P type trap zone 103a, 103b and N-type well region 102a,
102b.Form the FET of opposite types respectively in the semiconductor layer on well region 103a, 103b.Trap
The doping type of area 102a, 102b, 103a and 103b is related to the conduction type of FET, is formed
The conductive path of backgate, and with shallow trench isolation together with formed for by a FET with adjacent
The backgate isolation structure that FET and Semiconductor substrate 101 separate.This backgate isolation structure makes trap
The path that area 103a-102a-102b-103b is formed constitutes PNPN knot or NPNP knot all the time.
Further, by known depositing operation, such as electron beam evaporation (EBM), chemical gas
Mutually deposition (CVD), ald (ALD), sputtering etc., on semiconductor layer 104 successively
Form the first mask layer 106, the second mask layer 107 and the 3rd mask layer 108.Then, for example logical
Cross and be spin-coated on formation photoresist layer PR on the 3rd mask layer 108, and by including exposure
With the photoetching process of development, (for example, photoresist layer PR is formed the pattern being used for limiting backgate
Width is about the opening of 15nm-100nm), as shown in Figure 1.
Semiconductor substrate 101 by selected from Si, Ge, SiGe, GaAs, GaSb, AlAs, InAs,
One of group that InP, GaN, SiC, InGaAs, InSb and InGaSb are constituted composition.?
In one example, Semiconductor substrate 101 is, for example, monocrystalline substrate.It is just as will be described,
Semiconductor layer 104 will form semiconductor fin, and determine the general height of semiconductor fin.
Can control as needed ion implanting and annealing technological parameter, with control well region 102a,
The depth of 102b, 103a and 103b and expanded range.As a result, it is possible to obtain the half of desired thickness
Conductor layer 104.
First mask layer 106, the second mask layer 107 and the 3rd mask layer 108 can be by requiredization
Learn and the material of physical property forms, thus obtaining required etching selectivity in an etching step,
And/or as stop-layer in chemically mechanical polishing (CMP), and/or in final semiconductor device
It is further used as insulating barrier in part.And, according to the material using, the first mask layer 106, the
Two mask layers 107 and the 3rd mask layer 108 can be using identical or different above-mentioned depositing operation shapes
Become.In one example, the first mask layer 106 is to be about 5-15nm by the thickness that thermal oxide is formed
Silicon oxide layer, the second mask layer 107 is to be about 50nm-200nm by sputtering the thickness that formed
Amorphous silicon layer, the 3rd mask layer 108 is the nitrogen being about 5-15nm by sputtering the thickness that formed
SiClx layer.
Then, using photoresist layer PR as mask, by dry etching, such as ion beam milling
Etching, plasma etching, reactive ion etching, laser ablation, or molten by using etchant
The wet etching of liquid, removes the exposure of the 3rd mask layer 108 and the second mask layer 107 from top to bottom
Partly form opening, as shown in Figure 2.Due to the selectivity of etching, or etched by control
Time is so that this etching step stops at the top of the first mask layer.Can be with the etching of multiple steps
Etch different layers respectively.In one example, the first step etching includes adopting reactive ion etching,
Using a kind of suitable etchant, with respect to for example being gone by the second mask layer 107 that non-crystalline silicon forms
Except the expose portion of the 3rd mask layer 108 being for example made up of silicon nitride above, the second step etching
Including adopting reactive ion etching, using another kind of suitable etchant, with respect to for example by aoxidizing
First mask layer 106 of silicon composition removes the second mask layer being for example made up of above non-crystalline silicon
107 expose portion.
Then, by dissolving in a solvent or being ashed removal photoresist layer PR.By above-mentioned
The depositing operation known, forms the 4th conformal mask layer 109 on the surface of semiconductor structure.Logical
Cross anisotropic etch process (for example, reactive ion etching), remove the 4th mask layer 109
Above the 3rd mask layer 108 part of horizontal expansion and be located at opening bottom (first cover
In mold layer 106) part so that the part that the 4th mask layer 109 is located on opening inwall retains
And form side wall, as shown in Figure 3.Just as will be described, the 4th mask layer 109 will be used
In the width limiting semiconductor fin.Can be according to the width control system the 4th of required semiconductor fin
The thickness of mask layer 109.In one example, the 4th mask layer 109 is by ald
The thickness being formed is about the silicon nitride layer of 3nm-28nm.
Then, using the 3rd mask layer 108 and the 4th mask layer 109 as hard mask, by upper
State the expose portion that known etch process removes the first mask layer 106 via opening.And enter one
Step etching semiconductor layer 104 and the expose portion of well region 103a, 103b, up through semiconductor layer
104 and reach predetermined depth in well region 103a, 103b, as shown in Figure 4.Can basis
Design is it needs to be determined that the depth of part in well region 103a, 103b for the opening, and is lost by control
Time at quarter controls the depth of this part.In one example, the depth of this part is e.g. about
10nm-30nm, such that it is able to sufficiently large to stop the dopant in well region 103a, 103b subsequent
Step in be diffused in semiconductor fin.
Then, by above-mentioned known depositing operation, the surface of semiconductor structure is formed conformal
Dielectric layer.By anisotropic etch process (for example, reactive ion etching), removing should
The dielectric layer part of horizontal expansion and the bottom being located at opening above the 3rd mask layer 108
The part of (i.e. well region 103a, 103b is on the exposed surface in opening) is so that this dielectric layer
Part on opening inwall retains and forms the backgate electrolyte 110 of side wall form.Replace it
The technique of middle deposit dielectrics layer, can be by thermal oxide directly in semiconductor layer 104 and well region
103a, 103b are located at the backgate electrolyte 110 forming oxide side wall form on the side wall in opening,
From without subsequent anisotropic etching, this can Simplified flowsheet further.In an example
In, backgate electrolyte 110 is the silicon oxide layer that thickness is about 10nm-30nm.
Then, by above-mentioned known depositing operation, conductor is formed on the surface of semiconductor structure
Layer.This conductor layer at least fills up opening.This conductor layer is carried out with etch-back, removes and be located at outside opening
The part in portion, and remove the part that this conductor layer is located in opening further, thus in opening
Interior formation backgate conductor 111, as shown in Figure 5.Between backgate conductor 111 and semiconductor layer 104
Separated by backgate electrolyte 110.Backgate conductor 111 by selected from TaC, TiN, TaTbN, TaErN,
TaYbN, TaSiN, HfSiN, MoSiN, RuTax, NiTax, MoNx, TiSiN, TiCN,
TaAlC、TiAlN、TaN、PtSix、Ni3Si、Pt、Ru、Ir、Mo、W、HfRu、RuOx、
At least one composition in the polysilicon of doping.In one example, backgate conductor 111 is by adulterating
For the polysilicon composition of N-type or p-type, doping content for example, 1 × 1018cm-3-1×1021cm-3.
Etch-back for forming backgate conductor 111 makes the top of backgate conductor 111 be located at backgate
The lower section of electrolyte 110.It is alternatively possible to further with respect to backgate conductor 111 optionally
Etch-back backgate electrolyte 110 is so that the top of backgate electrolyte 110 and backgate conductor 111 is neat
Flat.
Then, in the case of not using mask, by above-mentioned known etch process, with respect to
Second mask layer 107, optionally removes completely and covers positioned at the 3rd of the second mask layer 107 top
Mold layer 108, thus expose the surface of the second mask layer 107.In one example, cover second
In the case of mold layer 107 is made up of non-crystalline silicon and the 3rd mask layer 108 is made up of silicon oxide, can
To be used Fluohydric acid. optionally to remove silicon as etchant.By above-mentioned known deposition work
Skill, forms insulating barrier on the surface of semiconductor structure.This insulating barrier at least fills up opening, thus
Cover the top surface of backgate conductor 111.This insulating barrier is carried out with etch-back, removes and be located at opening
Outside part.In one example, this insulating barrier is by sputtering the silicon nitride layer being formed.Should
Insulating barrier forms insulating cap 109 ' together with the 4th mask layer 109, as shown in Figure 6.This etching
The part that this insulating barrier is located in opening may be removed further.By controlling the time of etch-back,
Make the part that this insulating barrier is located in opening cover the top of backgate conductor 111, and institute is provided
The electrical insulation characteristics needing.
Then, in the case of not using mask, by above-mentioned known etch process, with respect to
Insulating cap 109 ' and the first mask layer 106, optionally remove the second mask layer 107 completely,
Thus exposing the surface of the first mask layer 106, as shown in Figure 7.In one example, first
Mask layer 106 is made up of silicon oxide, the second mask layer 107 is made up of non-crystalline silicon and insulating cap
109 ' in the case of be made up of silicon nitride, it is possible to use Tetramethylammonium hydroxide (TMAH) conduct
Etchant optionally removes non-crystalline silicon.
Then, using insulating cap 109 ' as hard mask, by above-mentioned known etch process
Remove the expose portion of the first mask layer 106 and semiconductor layer 104.And etch well region further
The expose portion of 103a, 103b is until reach predetermined depth, as shown in Figure 8.Removing first
During mask layer 106, shallow trench isolation 105 is likely to be etched, but the selectivity due to etching
And by controlling etching period, the top of shallow trench isolation 105 is located at well region 103a, 103b
Over top, thus well region 103a, 103b still can be separated.It is just as will be described below,
Well region 103a, 103b are using a part for the conductive path as backgate.Can be by during control etching
Between controlling the depth of etching so that well region 103a, 103b maintain certain thickness to reduce correlation
Dead resistance.
Semiconductor layer 104 is patterned to and leads positioned at the two and half of backgate conductor 111 both sides by this etching
Body fin 104 ', by respective backgate between backgate conductor 111 and two semiconductor fin 104 '
Electrolyte 110 separates, thus forming the interlayer of fin-backgate-fin (Fin-Back Gate-Fin)
Structure.Semiconductor fin 104 ' is a part for initial Semiconductor substrate 101, therefore equally
By selected from Si, Ge, SiGe, GaAs, GaSb, AlAs, InAs, InP, GaN, SiC, InGaAs,
One of group that InSb and InGaSb is constituted composition.In the example depicted in fig. 8, quasiconductor
Fin 104 ' be shaped as band, its length along the direction perpendicular to paper, its width along
Horizontal direction in paper, it is highly along the vertical direction in paper.Semiconductor fin 104 '
Height substantially by initial semiconductor layer 104 thickness determine, the width of semiconductor fin 104 '
Degree is substantially determined by the thickness of the 4th initial mask layer 109, the length of semiconductor fin 104 '
Then can need to limit by additional etching step according to design.In this etching step and subsequently
Processing step in, the backgate conductor 111 being previously formed provides machine for semiconductor fin 104 '
Tool supports and protects, it is hereby achieved that high finished product rate.
Then, by above-mentioned known depositing operation, the surface of semiconductor structure forms first
Insulating barrier 112, as shown in Figure 9.In one example, the first insulating barrier 112 for example by
The silicon oxide composition that sputtering is formed.The thickness of the first insulating barrier 112 be enough to be filled in formation quasiconductor
The opening positioned at semiconductor fin 104 ' side being formed in the etching step of fin 104 ', and
Also cover insulating cap 109 '.It is possible if desired to pass through in-situ sputtering or additional further
Chemically-mechanicapolish polish the surface of smooth first insulating barrier 112.
Then, by selective etch process (for example, reactive ion etching), etch-back first
Insulating barrier 112 and shallow trench isolation 105.This etching not only removes the first insulating barrier 112 and is located at absolutely
Part on the top of edge cap 109 ', and reduce the first insulating barrier 112 and be located at semiconductor fin
The thickness of the part in the opening of piece 104 ' both sides, as shown in Figure 10.Control the time of etching,
Make the first insulating barrier 112 surface be higher than well region 103a, 103b top, and expose and be located at
The side of the semiconductor fin 104 ' above well region.When removing the first insulating barrier 112, shallow ridges
Groove isolation 105 is likely to be etched.
As optional step, dopant is injected in the first insulating barrier 112 using ion implanting,
As shown in figure 11.Due to the ion scattering on surface, dopant can be easily from the first insulating barrier
The bottom that 112 near surface enters semiconductor fin 104 ' makes under semiconductor fin 104 '
Portion forms break-through trapping layer 113.Alternatively, can using additional thermal annealing by dopant from the
One insulating barrier 112 pushes in (drive-in) semiconductor fin 104 ' and forms break-through trapping layer 113.
Break-through trapping layer 113 is also possible that well region 103a, 103b are located at the surface of the first insulating barrier 112
A neighbouring part.For the FET of the opposite types being formed in same Semiconductor substrate, can
First to block the active area of the FET of the second conduction type using mask, for the first conduction type
FET carries out above-mentioned ion implanting to form the break-through trapping layer 113 of the second conduction type.Then
Block the active area of the FET of the first conduction type using mask, for the FET of the second conduction type
Carry out above-mentioned ion implanting to form the break-through trapping layer 113 of the first conduction type.
Can be using different dopants for different types of FET.Permissible in N-type FET
Using P-type dopant, such as B, p-type FET can use N type dopant, such as P,
As.As a result, break-through trapping layer 113 is by semiconductor fin 104 ' and Semiconductor substrate 101
Well region 103a, 103b separate.And, the doping type of break-through trapping layer 113 and source region and drain region
Doping type contrary, and the doping higher than well region 103a, 103b in Semiconductor substrate 101
Concentration.Although well region 103a, 103b can disconnect the drain current path between source region and drain region,
Play the effect of break-through trapping layer to a certain extent, but be located at additional below semiconductor fin 104 '
Highly doped break-through trapping layer 113 can improve further suppression source region and drain region between electric leakage
The effect of stream.
Then, by above-mentioned known depositing operation, front gate is formed on the surface of semiconductor structure
Electrolyte 114 (silicon oxide or silicon nitride).In one example, this front gate dielectric 114 is about
The thick silicon oxide layer of 0.8-1.5nm.Front gate dielectric 114 covers two semiconductor fin 104 '
A respective side.Then, by above-mentioned known depositing operation, in the table of semiconductor structure
Front gate conductor 115 (for example, DOPOS doped polycrystalline silicon) is formed on face, as shown in figure 12.If necessary,
(CMP) can be chemically-mechanicapolish polished to front gate conductor 115, to obtain even curface.
Then, using photoresist mask, this conductor layer is patterned as and semiconductor fin
104 ' intersecting front gate conductors 115.Then, by dissolving in a solvent or to be ashed removal photic anti-
Erosion oxidant layer.By above-mentioned known depositing operation, nitride is formed on the surface of semiconductor structure
Layer.In one example, this nitride layer is the silicon nitride layer of thickness about 5-20nm.By each
Heterotropic etch process (for example, reactive ion etching), removes the horizontal expansion of nitride layer
Partly so that the vertical component that nitride layer is located on the side of front gate conductor 115 retains, thus
Form grid curb wall 116, as shown in Figure 13 a, 13b, 13c and 13d.
Generally, due to the form factor (thickness of such as grid conductor layer (for example, DOPOS doped polycrystalline silicon)
More than the height of the fin of twice, or using up big and down small fin shapes), semiconductor fin 104 '
Nitride layer thickness on side is less than the nitride layer thickness on the side of front gate conductor 115, from
And the nitride layer on semiconductor fin 104 ' side can be removed in this etching step completely.
Otherwise, the nitride layer on semiconductor fin 104 ' side can affect the formation of follow-up source/drain region.
Nitride layer on semiconductor fin 104 ' side can be removed further using additional mask.
Front gate conductor 115 forms grid stacking together with front gate dielectric 114.Figure 13 a, 13b,
In example shown in 13c and 13d, front gate conductor 115 be shaped as band, and along with half
The direction that the length of conductor fin is vertical extends.
In a subsequent step, can be according to conventional technique, with front gate conductor 115 and gate electrode side
Wall 116, as hard mask, forms the source region that the channel region being provided with semiconductor fin 104 ' is connected
And drain region.In one example, source region and drain region can be the logical of semiconductor fin 104 ' two ends
Cross ion implanting or the doped region of doping formation in situ.In another example, source region and drain region can
Be two ends with semiconductor fin 104 ' or contacts side surfaces additional semiconductor layer in by from
Son injection or the doped region that doping is formed in situ.
Reference picture 14-15 describes the manufacture semiconductor device according to present invention further optimization embodiment
The example flow in a part of stage of the method for part, wherein, shows half in Figure 14 a and 15a
The top view of conductor structure and the interception position of sectional view, are partly leading shown in Figure 14 b and 15b
The sectional view of the semiconductor structure that width ascender line A-A of body fin intercepts, in Figure 14 c and
Shown in 15c semiconductor fin width ascender line B-B intercept semiconductor structure cut
Face figure, shown in Figure 14 d and 15d, length direction ascender line C-C in semiconductor fin intercepts
Semiconductor structure sectional view.
According to the preferred embodiment, after the step shown in Figure 13, execute Figure 14 and 15 further
Shown step is to form stress layer.
Then, by above-mentioned known depositing operation, in the exposed side of semiconductor fin 104 '
Epitaxial growth stress layer 117, as shown in Figure 14 a, 14b, 14c and 14d.Answer masterpiece
It is also formed on front gate conductor 115 with layer 117.The thickness of this stress layer 117 should be enough to
In semiconductor fin 104 ' the desired stress of upper applying.
Different stress layers 117 can be formed for different types of FinFET.By stress
Active layer 117 applies suitable stress to the channel region of FinFET, can improve moving of carrier
Shifting rate, thus reducing conducting resistance and improving the switching speed of device.For this reason, adopting and quasiconductor
The semi-conducting material that the material of fin 104 ' is different forms stress layer 117, can produce expectation
Stress.For N-type FinFET, stress layer 117 is e.g. formed on a si substrate
The content of C is about the Si of atomic percent 0.2-2%：C layer, along the longitudinal direction pair of channel region
Channel region applies tension.For p-type FinFET, stress layer 117 is e.g. in Si lining
The content of the Ge being formed on bottom is about the SiGe layer of atomic percent 15-75%, along channel region
Longitudinal direction to channel region apply compressive stress.
Then, by above-mentioned known depositing operation, the surface of semiconductor structure forms second
Insulating barrier 118.In one example, the second insulating barrier 118 e.g. silicon oxide layer, and thick
Degree enough to be filled in formed semiconductor fin 104 ' etching step in formed positioned at semiconductor fin
The opening of piece 104 ' side, and also cover the top surface of front gate conductor 115.With gate electrode side
Wall 116, as stop-layer, chemically-mechanicapolish polishes to the second insulating barrier 118, smooth to obtain
Surface, as shown in Figure 15 a, 15b, 15c and 15d.This chemically mechanical polishing goes de-stress to make
With the part positioned at front gate conductor 115 top for the layer 117, and expose the top of front gate conductor 115
Portion surface.
Further, as it was previously stated, in a subsequent step, can according to conventional technique, with
Front gate conductor 115 and grid curb wall 116, as hard mask, are formed and are carried with semiconductor fin 104 '
For channel region be connected source region and drain region.In one example, source region and drain region can partly be led
The doped region by ion implanting or doping formation in situ at body fin 104 ' two ends.At another
In example, source region and drain region can be the attached of two ends with semiconductor fin 104 ' or contacts side surfaces
Plus semiconductor layer in by ion implanting or doped region that in situ doping is formed.
Reference picture 16-18 describes the manufacture semiconductor device according to present invention further optimization embodiment
The example flow in a part of stage of the method for part, wherein, shows in Figure 16 a, 17a and 18a
The top view of semiconductor structure and the interception position of sectional view are gone out, in Figure 16 b, 17b and 18b
Shown in semiconductor fin width ascender line A-A intercept semiconductor structure section
Figure, in width ascender line B-B of semiconductor fin shown in Figure 16 c, 17c and 18c
The sectional view of the semiconductor structure intercepting, in semiconductor fin shown in Figure 16 d, 17d and 18d
Length direction ascender line C-C intercept semiconductor structure sectional view.
According to the preferred embodiment, the step of Figure 12 forms sacrificial gate conductor 114 ' and sacrifices
Form stress layer 117 after gate dielectric 113 ', and the step shown in Figure 17, and
Source region and drain region are formed, then the step shown in execution Figure 18 and 19 adopts inclusion further
Alternative gate conductor and substitute gate medium alternative gate stacking replace including sacrificial gate conductor 114 ' with sacrificial
The sacrificial gate stacking of domestic animal gate dielectric 113 '.
Using the second insulating barrier 118 and grid curb wall 116 as hard mask, by above-mentioned known
Etch process (such as reactive ion etching) removes sacrificial gate conductor 114 ', thus form grid opening
Mouthful, as shown in Figure 16 a, 16b, 16c and 16d.It is alternatively possible to remove sacrificial gate further
Electrolyte 113 ' is located at the part of gate openings bottom.According to rear grid technique, in gate openings
Formed and substitute gate dielectric 119, as shown in Figure 17 a, 17b, 17c and 17d, and using leading
Electric material fills gate openings to form alternative gate conductor 120, such as Figure 18 a, 18b, 18c and 18d
Shown.Alternative gate conductor 120 forms alternative gate stacking together with substituting gate dielectric 119.One
In individual example, substitute gate dielectric 119 to be situated between is the HfO that thickness is about 0.3nm-1.2nm2Layer, replaces
It is, for example, TiN layer for grid conductor 120.
According to each above-mentioned embodiment, after forming source region and drain region, can be obtained
On semiconductor structure formed interlayer insulating film, be located at interlayer insulating film in plunger, be located at interlayer exhausted
The wiring of edge layer upper surface or electrode, thus complete the other parts of semiconductor device.
Figure 19 shows the exploded perspective of semiconductor device 100 according to a preferred embodiment of the invention
Figure, is wherein not shown for clarity the second insulating barrier 118.This semiconductor device 100 is to adopt
Step shown in Fig. 1-18 is formed, thus including multiple preferred aspects of the present invention, but should not manage
Solve the combination for limiting the invention to this multiple preferred aspect.Additionally, for brevity no longer
Repeat material hereinbefore already mentioned above.
Semiconductor device 100 includes Semiconductor substrate 101, the well region in Semiconductor substrate 101
102a, 102b, 103a, 103b and the backgate isolation structure of shallow trench isolation 105 composition.Partly lead
Body device 100 includes the opposite types being formed respectively in the semiconductor layer on well region 103a, 103b
FET100a, 100b.The doping type of well region 102a, 102b, 103a and 103b and FET
Conduction type related, and formed backgate conductive path and by a FET with adjacent
The backgate isolation structure that FET and Semiconductor substrate 101 separate.This backgate isolation structure makes trap
The path that area 103a-102a-102b-103b is formed constitutes PNPN knot or NPNP knot all the time.Well region
103a, 103b part also as the conductive path of backgate conductor 111.FET 100a、100b
Include the sandwich on well region 103a, 103b respectively.This sandwich includes backgate conductor
111st, it is located at two semiconductor fin 104 ' of backgate conductor 111 both sides and by backgate conductor
111 and the respective backgate electrolyte 110 that is spaced one from of two semiconductor fin 104 '.Break-through hinders
Only layer 113 is located at semiconductor fin 104 ' bottom.Front gate stacking is intersected with semiconductor fin 104 ',
This front gate stacking include before gate dielectric and front gate conductor, and front gate dielectric by front gate conductor and
Semiconductor fin 104 ' separates.
In example shown in Figure 19, front gate dielectric is the alternative gate electricity being formed according to rear grid technique
Medium 119, front gate conductor is the alternative gate conductor 120 being formed according to rear grid technique.Grid curb wall
On 116 sides being located at alternative gate conductor 120.Although eliminating sacrifice during rear grid technique
The part that gate dielectric 113 ' is located in gate openings, but remain under grid curb wall 116
The part of side.
Additionally, insulating cap 109 ' is located above backgate conductor 111, and by backgate conductor 111
Separate with alternative gate conductor 120.First insulating barrier 112 is located at and substitutes gate dielectric 119 and well region
Between 103a, 103b, and replacement gate dielectric 119 and well region 103a, 103b are separated.
The source that the channel region that semiconductor device 100 also includes providing with semiconductor fin 104 ' is connected
Area and drain region.In example shown in Figure 19, source region and drain region can be semiconductor fin 104 '
The doped region by ion implanting or doping formation in situ at two ends.Additional stress layer 117
Contacts side surfaces with semiconductor fin 104 '.FET 100a, 100b of two opposite types are each
Including two semiconductor fin 104 '.Plunger 121 is connected respectively to each through interlayer insulating film
The source region of respective semiconductor fin 104 ' of FET and drain region.Additional plunger 121 connects respectively
It is connected to the alternative gate conductor 120 of each FET, other additional plungers 121 pass through interlayer exhausted
Edge layer and the first insulating barrier 112 are connected respectively to well region 102a, 102b, 103a, 103b, thus
Can be with applied voltage.Well region 102a, 102b, 103a, 103b and the shallow trench isolation 105 composition back of the body
Grid isolation structure is so that can be via well region 103a, 103b respectively to two opposite types
The backgate 111 of FET applies different voltages, thus correspondingly adjusting the threshold voltage of each FET.
In the above description, the ins and outs such as the composition of each layer, etching are not made in detail
Thin explanation.It should be appreciated to those skilled in the art that can be come by various technological means
Form layer, region of required form etc..In addition, in order to form same structure, people in the art
Member can be devised by the not identical method with process as described above.Although in addition,
More than respectively describe each embodiment, but it is not intended that the measure in each embodiment can not
It is advantageously combined use.
Above embodiments of the invention are described.But, these embodiments are used for the purpose of
Descriptive purpose, and be not intended to limit the scope of the present invention.The scope of the present invention is by appended right
Require and its equivalent limits.Without departing from the scope of the present invention, those skilled in the art can make
Multiple replacements and modification, these substitute and modification all should fall within the scope of the present invention.
Claims (15)
1. a kind of semiconductor device, including：
Semiconductor substrate；
Backgate isolation structure in Semiconductor substrate；And
Adjacent field-effect transistor on backgate isolation structure,
Wherein, each of described adjacent field-effect transistor is included positioned at backgate isolation structure
On sandwich, this sandwich include backgate conductor, be located at backgate conductor both sides quasiconductor
Fin and the respective backgate electrolyte that backgate conductor and semiconductor fin are spaced one from,
Wherein, backgate isolation structure leading as the backgate conductor of described adjacent field-effect transistor
A part for power path, and, shape between the backgate conductor of described adjacent field-effect transistor
Become PNPN knot or NPNP knot,
Wherein, backgate isolation structure includes：
The first well region being laterally abutted and the second well region；
Be located at respectively above the first well region and the second well region and respectively with the first well region and the second well region
The 3rd adjacent well region and the 4th well region；And
The shallow trench that 3rd well region and the 4th well region are separated is isolated,
Wherein, the backgate conductor of the first field-effect transistor in described adjacent field-effect transistor
Contact with the 3rd well region, the backgate conductor of the second field-effect transistor is contacted with the 4th well region.
2. semiconductor device according to claim 1, is also included positioned at semiconductor fin bottom
Break-through trapping layer.
3. semiconductor device according to claim 2, the wherein doping type of break-through trapping layer
Contrary with the conduction type of field-effect transistor.
4. semiconductor device according to claim 1, also includes the side with semiconductor fin
The additional stress layer of contact.
5. semiconductor device according to claim 1, the wherein conduction type of the first transistor
Contrary with the conduction type of transistor seconds, and the doping type of the first well region and the first field effect
The conduction type of transistor is identical, the 3rd doping type of well region and leading of the first field-effect transistor
Electric type is contrary, and the doping type of the second well region is identical with the conduction type of the second field-effect transistor,
The doping type of the 4th well region is contrary with the conduction type of the second field-effect transistor.
6. semiconductor device according to claim 5, wherein the 3rd well region the-the first well region-
PNPN knot or NPNP knot are formed on the second well region, the path of the 4th well region.
7. a kind of method manufacturing semiconductor device, including：
Form backgate isolation structure in the semiconductor substrate so that Semiconductor substrate is located at backgate isolation
The part of superstructure forms semiconductor layer；And
Adjacent field-effect transistor is formed on backgate isolation structure, including：
Form multiple mask layers on the semiconductor layer；
Form opening in of the top in the plurality of mask layer；
Form another mask layer of side wall form in opening inwall；
Using another mask layer described as hard mask, opening is passed through the plurality of mask
Layer and described semiconductor layer extend to backgate isolation structure；
Form backgate electrolyte in opening inwall；
Form backgate conductor in the opening；
Form the insulating cap including another mask layer described, this insulating cap in the opening
Cover backgate electrolyte and backgate conductor；
Using insulating cap as hard mask, semiconductor layer pattern is turned to semiconductor fin；
Wherein, backgate conductor, the semiconductor fin being formed by semiconductor layer positioned at backgate conductor both sides
Piece and the respective backgate dielectric formation folder that backgate conductor and semiconductor fin are spaced one from
Backgate conductor is separated by Rotating fields, wherein insulating cap with front gate conductor,
Wherein, backgate isolation structure leading as the backgate conductor of described adjacent field-effect transistor
A part for power path, and, shape between the backgate conductor of described adjacent field-effect transistor
Become PNPN knot or NPNP knot.
8. method according to claim 7, before the step of patterned semiconductor layer and formation
Between the step of grid stacking, it is additionally included in semiconductor fin bottom and forms break-through trapping layer.
9. method according to claim 8, wherein forms break-through trapping layer and includes carrying out ion
Injection and in the semiconductor fin partly middle introducing dopant adjacent with well region.
10. method according to claim 9, wherein forms break-through trapping layer and includes carrying out
Before ion implanting, form the position that insulating barrier limits break-through trapping layer.
11. methods according to claim 9, wherein in the step forming break-through trapping layer
The dopant type using is contrary with the conduction type of field-effect transistor.
12. methods according to claim 7, also include forming the side with semiconductor fin
Epitaxial growth stress layer.
13. methods according to claim 7, wherein form backgate isolation structure and include：
Form the first well region in the semiconductor substrate；
3rd well region is formed on the first well region；
Form the second well region in the semiconductor substrate, the second well region is laterally abutted with the first well region；
4th well region is formed on the second well region；
Form shallow trench isolation to separate the 3rd well region and the 4th well region,
Wherein, the backgate conductor of the first field-effect transistor in described adjacent field-effect transistor
Contact with the 3rd well region, the backgate conductor of the second field-effect transistor is contacted with the 4th well region.
14. methods according to claim 13, wherein in the 3rd well region the-the first well region-the second
PNPN knot or NPNP knot are formed on well region, the path of the 4th well region.
15. methods according to claim 13, the wherein first well region, the second well region,
The concentration of dopant atoms of three well regions and the 4th well region is 1016cm-3To 1019cm-3.
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|---|---|---|---|---|
| US7767546B1 (en) * | 2009-01-12 | 2010-08-03 | International Business Machines Corporation | Low cost fabrication of double box back gate silicon-on-insulator wafers with built-in shallow trench isolation in back gate layer |
| CN102088027A (en) * | 2009-12-08 | 2011-06-08 | S.O.I.Tec绝缘体上硅技术公司 | Circuit of uniform transistors on SeOI with buried back control gate beneath the insulating film |
| US8021943B2 (en) * | 2009-11-25 | 2011-09-20 | International Business Machines Corporation | Simultaneously formed isolation trench and through-box contact for silicon-on-insulator technology |
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| US7084461B2 (en) * | 2004-06-11 | 2006-08-01 | International Business Machines Corporation | Back gate FinFET SRAM |
| US7259420B2 (en) * | 2004-07-28 | 2007-08-21 | International Business Machines Corporation | Multiple-gate device with floating back gate |
| US7087966B1 (en) * | 2005-05-18 | 2006-08-08 | International Business Machines Corporation | Double-Gate FETs (field effect transistors) |
| JP2007242950A (en) * | 2006-03-09 | 2007-09-20 | Toshiba Corp | Semiconductor memory |
| US20090206405A1 (en) * | 2008-02-15 | 2009-08-20 | Doyle Brian S | Fin field effect transistor structures having two dielectric thicknesses |
| CN102479821B (en) * | 2010-11-30 | 2014-07-16 | 中国科学院微电子研究所 | Semiconductor device and method of forming the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7767546B1 (en) * | 2009-01-12 | 2010-08-03 | International Business Machines Corporation | Low cost fabrication of double box back gate silicon-on-insulator wafers with built-in shallow trench isolation in back gate layer |
| US8021943B2 (en) * | 2009-11-25 | 2011-09-20 | International Business Machines Corporation | Simultaneously formed isolation trench and through-box contact for silicon-on-insulator technology |
| CN102088027A (en) * | 2009-12-08 | 2011-06-08 | S.O.I.Tec绝缘体上硅技术公司 | Circuit of uniform transistors on SeOI with buried back control gate beneath the insulating film |
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| CN103985712A (en) | 2014-08-13 |
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