WO2014121539A1

WO2014121539A1 - Semiconductor device and manufacturing method thereof

Info

Publication number: WO2014121539A1
Application number: PCT/CN2013/072525
Authority: WO
Inventors: 朱慧珑
Original assignee: 中国科学院微电子研究所
Priority date: 2013-02-08
Filing date: 2013-03-13
Publication date: 2014-08-14
Also published as: CN103985712B; CN103985712A

Abstract

Disclosed are a semiconductor device and manufacturing method thereof, the semiconductor device comprising: a semiconductor substrate, a back-gate isolation structure in the semiconductor substrate, and neighboring field effect transistors on the back-gate isolation structure; each of the neighboring field effect transistors comprises a sandwich structure on the back-gate isolation structure, the sandwich structure comprising a back-gate conductor, a semiconductor fin on the two sides of the back-gate conductor, and respective back-gate dielectrics respectively isolating the back-gate conductor from the semiconductor fin; the back-gate isolation structure is part of the conductive paths of the back-gate conductors of the neighboring field effect transistors, and forms a PNPN junction or an NPNP junction between the back-gate conductors of the neighboring field effect transistors. The semiconductor device employs a back-gate isolation structure to apply different voltages to the back gate of one or more field effect transistors respectively, thus regulating the threshold voltage of each field effect transistor accordingly.

Description

Semiconductor device and method of manufacturing the same

The present invention relates to semiconductor technology and, more particularly, to a semiconductor device including a fin (Fin) and a method of fabricating the same. Background technique

With the development of semiconductor technology, it is desirable to reduce the power consumption while reducing the size of a semiconductor device to improve integration. In order to suppress the short channel effect due to size reduction, a FinFET formed on an SOI wafer or a bulk semiconductor substrate is proposed. The FinFET includes a channel region formed in the middle of the fins of the semiconductor material, and source/drain regions formed at both ends of the fin. The gate electrode surrounds the channel region (i.e., the double gate structure) at least on both sides of the channel region, thereby forming an inversion layer on each side of the channel. Since the entire channel region can be controlled by the gate, it is possible to suppress the short channel effect. In order to reduce power consumption due to leakage, a UTBB (ultra-thin buried oxide body) type FET formed in a semiconductor substrate has been proposed. The UTBB type FET includes an ultra-thin buried oxide layer in a semiconductor substrate, a front gate and source/drain regions over the ultra-thin oxide buried layer, and a back gate under the ultra-thin buried oxide layer. In operation, by applying a bias voltage to the back gate, power consumption can be significantly reduced while maintaining the same speed.

Despite their respective advantages, a semiconductor device that combines the advantages of both has not been proposed because of the many difficulties in forming a back gate in a FinFET. In a FinFET based on a bulk semiconductor substrate, since the contact area of the semiconductor fin with the semiconductor substrate is small, the formed back gate will cause a severe self-heating effect. In FinFETs based on SOI wafers, high cost problems are caused by the high price of SOI wafers. Moreover, the formation of the back gate on the SOI wafer requires precise controlled ion implantation through the top semiconductor layer to form an implant region for the back gate under the buried insulating layer, resulting in process difficulties resulting in low yield, and due to the trench Unintentional doping of the track region causes device performance to fluctuate. Summary of the invention

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device including a back gate isolation structure to improve the adjustment capability of a threshold voltage.

According to an aspect of the present invention, a semiconductor device is provided, comprising: a semiconductor substrate; a back gate isolation structure in the semiconductor substrate; and an adjacent field effect transistor on the back gate isolation structure, wherein the phase Each of the adjacent field effect transistors includes a sandwich structure on the back gate isolation structure, the sandwich structure including a back gate conductor, semiconductor fins on both sides of the back gate conductor, and a back gate conductor and the semiconductor fin Opening respective back gate dielectrics, wherein the back gate isolation structure is part of a conductive path of the back gate conductor of the adjacent field effect transistor and between the back gate conductors of the adjacent field effect transistors A P PN junction or a PNP junction is formed.

According to another aspect of the present invention, a method of fabricating a semiconductor device is provided, comprising: forming a back gate isolation structure in a semiconductor substrate such that a portion of the semiconductor substrate over the back gate isolation structure forms a semiconductor layer;

Forming adjacent field effect transistors on the back gate isolation structure, comprising: forming a plurality of mask layers on the semiconductor layer; forming an opening in one of the topmost ones of the plurality of mask layers; forming an inner wall of the opening Another mask layer in the form of a wall; using the other mask layer as a hard mask, extending an opening through the plurality of mask layers and the semiconductor layer to the back gate isolation structure; forming a back on the inner wall of the opening a gate dielectric; forming a back gate conductor in the opening; forming an insulating cap including the another mask layer in the opening, the insulating cap covering the back gate dielectric and the back gate conductor; using an insulating cap as a hard mask, Patterning the semiconductor layer into a semiconductor fin; wherein, the back gate conductor, the semiconductor fin formed by the semiconductor layer on both sides of the back gate conductor, and the respective back gate dielectric separating the back gate conductor from the semiconductor fin Forming a sandwich structure, wherein the insulating cap separates the back gate conductor from the front gate conductor, wherein the back gate isolation structure serves as a back gate conductor of the adjacent field effect transistor A portion of the conductive path, and the P PN junction is formed or P P junction between the back gate conductor adjacent to the field effect transistor.

The semiconductor device of the present invention includes a back gate conductor adjacent to a respective one side of the two semiconductor fins. Since the back gate conductor is not formed under the semiconductor fins, the contact area between the back gate conductor and the well region as a part of the conductive path can be independently determined as needed to avoid the self-heating effect generated by the back gate conductor. Also, since it is not necessary to perform ion implantation through the semiconductor fins when forming the back gate conductor, unintentional doping of the channel region can be avoided to cause fluctuation in device performance.

The semiconductor device combines the advantages of FinFET and UTBB type FETs. On the one hand, the back gate conductor can be used to control or dynamically adjust the threshold voltage of the semiconductor device, and the power consumption can be significantly reduced while maintaining the speed. On the other hand, Fin can be utilized. The short channel effect is suppressed, and the performance of the semiconductor device is maintained when the semiconductor device is shrunk. Therefore, the semiconductor device can reduce power consumption while reducing the size of the semiconductor device to improve integration. Moreover, and the manufacturing method of the semiconductor device is compatible with the existing semiconductor process, the manufacturing cost is low. A PNPN junction or an NPNP junction is formed between the back gates of adjacent field effect transistors, thereby causing adjacent field effects The back gates of the transistors are spaced apart and the threshold voltage of the field effect transistors can be adjusted independently of each other. DRAWINGS

The above and other objects, features and advantages of the present invention will become more apparent from

1-13 are schematic views showing semiconductor structures at various stages of a method of fabricating a semiconductor device in accordance with an embodiment of the present invention.

14-15 are schematic diagrams showing a portion of a semiconductor structure of a method of fabricating a semiconductor device in accordance with a further preferred embodiment of the present invention.

16-18 are schematic diagrams showing a portion of a semiconductor structure of a method of fabricating a semiconductor device in accordance with a further preferred embodiment of the present invention.

Figure 19 shows an exploded perspective view of a semiconductor device in accordance with a preferred embodiment of the present invention. detailed description

The invention will be described in more detail below with reference to the accompanying drawings. In the various figures, the same elements are denoted by like reference numerals. For the sake of clarity, the various parts in the figures are not drawn to scale.

For the sake of brevity, the semiconductor structure obtained after several steps can be described in one figure.

It should be understood that when describing a structure of a device, when a layer or a region is referred to as being "above" or "above" another layer, another region may be directly above another layer or another region, or Other layers or regions are also included between it and another layer. Also, if the device is flipped, the layer, one area will be located on the other layer, and the other area "below" or "below".

In the case of describing a situation directly above another layer or another area, this article will adopt the expression "directly above" or "above and adjacent to".

In the present application, the term "semiconductor structure" refers to a general term for the entire semiconductor structure formed in the various steps of fabricating a semiconductor device, including all layers or regions that have been formed. Many specific details of the invention are described below, such as the structure, materials, dimensions, processing, and techniques of the invention, in order to provide a clear understanding of the invention. However, the invention may be practiced without these specific details, as will be understood by those skilled in the art.

Unless otherwise indicated below, various portions of the semiconductor device can be constructed from materials well known to those skilled in the art. The semiconductor material includes, for example, a III-V semiconductor such as GaAs, InP, GaN, SiC, And Group IV semiconductors, such as Si, Ge. The gate conductor may be formed of various materials capable of conducting electricity, such as a metal layer, a doped polysilicon layer, or a stacked gate conductor including a metal layer and a doped polysilicon layer, or other conductive materials such as TaC, TiN TaTbN, TaErN, TaYbN TaSiN HfSiN MoSiN RuTax, NiTax, MoNx TiSiN, TiCN, TaAlC, TiAlN TaN, PtSix, Ni ₃ Si, Pt, Ru, Ir, Mo, W, HfR _U , RuOx, and combinations of the various conductive materials. The gate dielectric may be composed of SiO ₂ or a material having a dielectric constant greater than SiO ₂ , and includes, for example, an oxide, a nitride, an oxynitride, a silicate, an aluminate, a titanate, wherein the oxide includes, for example, SiO ₂ , _{_{_{Hro 2 Zr0 2, A1 2 0}}} 3, Ti0 2, La 2 0 3, for example, comprises nitride Si ₃ N _4, including silicates such as HfSiOx, e.g. aluminates including LaA10 _3, titanates include, for example SrTi0 _3, The oxynitride includes, for example, SiON. Also, the gate dielectric may be formed not only by materials well known to those skilled in the art, but also materials developed for the gate dielectric in the future.

The present invention can be embodied in various forms, some of which are described below.

An exemplary flow of a method of fabricating a semiconductor device in accordance with one embodiment of the present invention is described with reference to Figures 1-13, wherein a top view and a cross-sectional view of the cross-sectional view of the semiconductor structure are shown in Figure 13a, in Figures 1-12 and 13b A cross-sectional view of the semiconductor structure taken along line AA in the width direction of the semiconductor fin is shown, and a cross-sectional view of the semiconductor structure taken along line BB in the width direction of the semiconductor fin is shown in FIG. 13c, which is shown in FIG. 13d. A cross-sectional view of the semiconductor structure taken along line CC in the length direction of the semiconductor fin.

The method begins with a bulk semiconductor substrate 101. Four well regions 102a, 102b, 103a, and 103b are formed in the bulk semiconductor substrate 101. The well regions 102a and 102b are laterally adjacent to each other, the well regions 103a and 103b are laterally adjacent, and the well regions 103a and 103b are located above the well regions 102a and 102b, respectively. The portion of the semiconductor substrate 101 above the well regions 103a and 103b forms the semiconductor layer 104, and the well regions 102a, 102b, 103a, and 103b separate the semiconductor layer 104 from the semiconductor substrate 101. A process of forming well regions 102a, 102b, 103a, and 103b in a semiconductor substrate 101 is known, for example, by ion implantation to form a doped region in a semiconductor layer and then annealed to activate a dopant in the doped region. In one example, . Forming the well regions 102a, 102b, 103a, and 103b in the semiconductor substrate 101 includes forming a well region 102a in a portion of the semiconductor substrate 101, and forming a well region 103a in a portion of the semiconductor substrate 101 above the well region 102a, in the semiconductor A well region 102b is formed in a portion of the substrate 101 adjacent to the well region 102a, and a well region 103b is formed in a portion of the semiconductor substrate 101 above the well region 102b. In one example, the well region 102a, 102b, 103a and 103b, respectively, the concentration of dopant atoms is from about ^10,160 to ^ ³ 10 ¹⁹ cm_ ^3. As will be described below, opposite types of FETs will be formed in the semiconductor layer 104 over the well regions 103a and 103b. Shallow trench isolation (STI) 105 is then formed in accordance with conventional processes to define the active regions of the FETs and to separate adjacent FETs. Shallow trench isolation 105 extends through The semiconductor layer 104, the well regions 103a and 103b, and reach a predetermined depth in the well regions 102a and 102b. The trench isolation 105 not only separates the semiconductor layers 104 of adjacent FETs, but also separates the well regions 103a and 103b such that adjacent FETs are separated, with only adjacent well regions 102a and 102b being present.

For the P-type FET, N-type well regions 103a, 103b and P-type well regions 102a, 102b can be formed, and for the N-type FET, P-type well regions 103a, 103b and N-type well regions 102a, 102b can be formed. Opposite types of FETs are formed in the semiconductor layers on the well regions 103a, 103b, respectively. The doping type of the well regions 102a, 102b, 103a, and 103b is related to the conductivity type of the FET, forming a conductive path of the back gate, and is formed together with the shallow trench isolation for forming one FET and the adjacent FET and the semiconductor substrate 101. Separated back gate isolation structures. The back gate isolation structure allows the paths formed by the well regions 103a-102a-102b-103b to always constitute a P PN junction or a P P junction.

Further, the first mask layer 106 is sequentially formed on the semiconductor layer 104 by a known deposition process such as electron beam evaporation (EBM), chemical vapor deposition (CVD), atomic layer deposition (ALD), sputtering, or the like. The second mask layer 107 and the third mask layer 108. Then, a photoresist layer PR is formed on the third mask layer 108, for example, by spin coating, and the photoresist layer PR is formed to define a pattern of the back gate by a photolithography process including exposure and development therein. (For example, an opening having a width of about 15 nm to 100 nm), as shown in FIG.

The semiconductor substrate 101 is composed of one selected from the group consisting of Si, Ge, SiGe, GaAs, GaSb, AlAs, InAs, InP, GaN, SiC, InGaAs, InSb, and InGaSb. In one example, the semiconductor substrate 101 is, for example, a single crystal silicon substrate. As will be described below, the semiconductor layer 104 will form semiconductor fins and determine the approximate height of the semiconductor fins. Process parameters that control ion implantation and annealing can be controlled as needed to control the depth and extent of well regions 102a, 102b, 103a, and 103b. As a result, the semiconductor layer 104 of a desired thickness can be obtained.

The first mask layer 106, the second mask layer 107, and the third mask layer 108 may be composed of materials of desired chemical and physical properties to achieve desired etch selectivity in the etching step, and/or in chemistry It is used as a stop layer in mechanical polishing (CMP), and/or as an insulating layer in the final semiconductor device. Also, the first mask layer 106, the second mask layer 107, and the third mask layer 108 may be formed using the same or different deposition processes described above, depending on the materials used. In one example, the first mask layer 106 is a silicon oxide layer having a thickness of about 5-15 nm formed by thermal oxidation, and the second mask layer 107 is amorphous silicon having a thickness of about 50 nm to 200 nm formed by sputtering. The third mask layer 108 is a silicon nitride layer having a thickness of about 5-15 Å formed by sputtering.

Then, using the photoresist layer PR as a mask, by dry etching, such as ion milling etching, plasma etching, reactive ion etching, laser ablation, or by wet etching using an etchant solution, from top to bottom The exposed portions of the third mask layer 108 and the second mask layer 107 are removed to form openings, as shown in FIG. The etching step is stopped at the top of the first mask layer due to the selectivity of the etching, or by controlling the etching time. Different layers can be etched separately by etching in multiple steps. In one example, the first step of etching includes using a reactive ion etch to remove a third, for example, silicon nitride, from a second mask layer 107, such as comprised of amorphous silicon, using a suitable etchant. The exposed portion of the mask layer 108, the second step of etching includes the use of reactive ion etching, using another suitable etchant, to remove the upper, for example, amorphous silicon, relative to, for example, the first mask layer 106 comprised of silicon oxide. The exposed portion of the second mask layer 107.

Then, the photoresist layer PR is removed by dissolving or ashing in a solvent. A conformal fourth mask layer 109 is formed on the surface of the semiconductor structure by the above-described known deposition process. The portion of the fourth mask layer 109 that extends laterally over the third mask layer 108 and the bottom portion of the opening (ie, the first mask layer 106) are removed by an anisotropic etching process (eg, reactive ion etching). In part, the portion of the fourth mask layer 109 on the inner wall of the opening is left to form a side wall, as shown in FIG. As will be described below, the fourth mask layer 109 will be used to define the width of the semiconductor fins. The thickness of the fourth mask layer 109 can be controlled according to the width of the desired semiconductor fin. In one example, the fourth mask layer 109 is a silicon nitride layer having a thickness of about 3 nm to 28 nm formed by atomic layer deposition.

Then, using the third mask layer 108 and the fourth mask layer 109 as a hard mask, the exposed portion of the first mask layer 106 is removed through the opening by the above-described known etching process. And the semiconductor layer 104 and the exposed portions of the well regions 103a, 103b are further etched until passing through the semiconductor layer 104 and reaching a predetermined depth in the well regions 103a, 103b, as shown in FIG. The depth of the portion of the opening in the well regions 103a, 103b can be determined according to design needs, and the depth of the portion can be controlled by controlling the etching time. In one example, the depth of the portion is, for example, about 10 nm to 30 nm, and thus may be large enough to prevent dopants in the well regions 103a, 103b from diffusing into the semiconductor fins in subsequent steps.

A conformal dielectric layer is then formed over the surface of the semiconductor structure by the known deposition process described above. The portion of the dielectric layer that extends laterally over the third mask layer 108 and the bottom portion of the opening (ie, the exposed regions of the well regions 103a, 103b within the opening) are removed by an anisotropic etch process (eg, reactive ion etching). The portion of the dielectric layer on the inner wall of the opening remains to form the back gate dielectric 110 in the form of a sidewall. Instead of the process in which the dielectric layer is deposited, the back gate dielectric 110 in the form of an oxide spacer can be formed directly on the sidewalls of the semiconductor layer 104 and the well regions 103a, 103b located in the opening by thermal oxidation, thereby eliminating the need for subsequent anisotropy. Etching, this can further simplify the process. In one example, back gate dielectric 110 is a silicon oxide layer having a thickness of between about 10 nm and 30 nm. Then, a conductor layer is formed on the surface of the semiconductor structure by the above-described known deposition process. The conductor layer fills at least the opening. The conductor layer is etched back to remove a portion located outside the opening, and a portion of the conductor layer located inside the opening is further removed, thereby forming a back gate conductor 111 in the opening, as shown in FIG. The back gate conductor 111 and the semiconductor layer 104 are separated by a back gate dielectric 110. The back gate conductor 111 is selected from the group consisting of TaC, window, TaTbN, TaErN TaYbN TaSiN, HfSiN MoSiN RuTax, NiTax, MoNx TiSiN, TiCN, TaAlC, TiAlN TaN, PtSix, Ni ₃ Si, Pt, Ru, Ir, Mo, W, HfRu At least one of RuOx, doped polysilicon. In one example, the back gate conductor 111 is doped with N-type or P-type polysilicon, the doping concentration of for example ^{^{1 X 10 18 cm_ 3 -l X}} 10 21 cm_ 3.

The etch back used to form the back gate conductor 111 is such that the top of the back gate conductor 111 is below the back gate dielectric 110. Alternatively, the back gate dielectric 110 can be selectively etched back relative to the back gate conductor 111 such that the tops of the back gate dielectric 110 and the back gate conductor 111 are flush.

Then, in the case where the mask is not used, the third mask layer 108 located above the second mask layer 107 is selectively completely removed with respect to the second mask layer 107 by the above-described known etching process, thereby The surface of the second mask layer 107 is exposed. In one example, in the case where the second mask layer 107 is composed of amorphous silicon and the third mask layer 108 is composed of silicon oxide, silicon oxide can be selectively removed using hydrofluoric acid as an etchant. An insulating layer is formed on the surface of the semiconductor structure by the above-described known deposition process. The insulating layer fills at least the opening to cover the top surface of the back gate conductor 111. The insulating layer is etched back to remove a portion located outside the opening. In one example, the insulating layer is a silicon nitride layer formed by sputtering. The insulating layer forms an insulating cap 109' with the fourth mask layer 109, as shown in FIG. The etching may further remove a portion of the insulating layer that is located within the opening. By controlling the time of the etch back, the portion of the insulating layer located within the opening covers the top of the back gate conductor 111 and provides the desired electrical insulating properties.

Then, in the case where the mask is not used, the second mask layer 107 is selectively completely removed with respect to the insulating cap 109' and the first mask layer 106 by the above-described known etching process, thereby exposing the first The surface of the mask layer 106 is as shown in FIG. In one example, in the case where the first mask layer 106 is composed of silicon oxide, the second mask layer 107 is composed of amorphous silicon, and the insulating cap 109' is composed of silicon nitride, tetramethyl hydroxide can be used. Ammonium (TMAH) selectively removes amorphous silicon as an etchant.

Then, using the insulating cap 109' as a hard mask, the exposed portions of the first mask layer 106 and the semiconductor layer 104 are removed by the above-described known etching process. And the exposed portions of the well regions 103a, 103b are further etched until a predetermined depth is reached, as shown in FIG. The shallow trench isolation 105 may also be etched when the first mask layer 106 is removed, but due to the selectivity of the etch and by controlling the etch time, the top of the shallow trench isolation 105 The portions are located above the top of the well regions 103a, 103b so that the well regions 103a, 103b can still be separated. As will be described below, well regions 103a, 103b will be part of the conductive path of the back gate. The depth of the etch can be controlled by controlling the etch time such that the well regions 103a, 103b maintain a certain thickness to reduce the associated parasitic resistance.

The etch engraves the semiconductor layer 104 into two semiconductor fins 104' on either side of the back gate conductor 111, and the back gate conductor 111 and the two semiconductor fins 104' are separated by respective back gate dielectrics 110 to form Fin-back Gate-Fin sandwich structure. The semiconductor fin 104' is part of the initial semiconductor substrate 101 and is therefore also comprised of a group selected from the group consisting of Si, Ge, SiGe, GaAs, GaSb, AlAs, InAs, InP, GaN, SiC, InGaAs, InSb, and InGaSb. A composition. In the example shown in FIG. 8, the semiconductor fin 104' is in the form of a strip having a length along a direction perpendicular to the plane of the paper, a width along a lateral direction in the plane of the paper, and a height along the plane of the paper. Vertical direction. The height of the semiconductor fin 104' is substantially determined by the thickness of the initial semiconductor layer 104, the width of the semiconductor fin 104' is substantially determined by the thickness of the initial fourth mask layer 109, and the length of the semiconductor fin 104' can be designed according to the design. Need to be defined by an additional etching step. In this etching step and subsequent process steps, the previously formed back gate conductor 111 provides mechanical support and protection for the semiconductor fins 104', thereby achieving high yield.

Then, a first insulating layer 112 is formed on the surface of the semiconductor structure by the above-described known deposition process, as shown in FIG. In one example, the first insulating layer 112 is composed of, for example, silicon oxide formed by sputtering. The thickness of the first insulating layer 112 is sufficient to fill the opening on the side of the semiconductor fin 104' formed in the etching step of forming the semiconductor fin 104', and also to cover the insulating cap 109'. If desired, the surface of the first insulating layer 112 may be further planarized by in-situ sputtering or additional chemical mechanical polishing.

Then, the first insulating layer 112 and the shallow trench isolation 105 are etched back by a selective etching process (e.g., reactive ion etching). The etching not only removes the portion of the first insulating layer 112 on the top of the insulating cap 109', but also reduces the thickness of the portion of the first insulating layer 112 located in the opening on both sides of the semiconductor fin 104', as shown in FIG. . The etching time is controlled such that the surface of the first insulating layer 112 is higher than the top of the well regions 103a, 103b and exposes the sides of the semiconductor fins 104' located above the well regions. The shallow trench isolation 105 may also be etched when the first insulating layer 112 is removed.

As an optional step, dopants are implanted into the first insulating layer 112 by ion implantation, as shown in FIG. Due to ion scattering of the surface, the dopant can easily enter the lower portion of the semiconductor fin 104' from the vicinity of the surface of the first insulating layer 112 such that the lower portion of the semiconductor fin 104' forms the punch-through blocking layer 113. Alternatively, an additional thermal anneal may be used to drive dopants from the first insulating layer 112 into the semiconductor fins 104' to form the punch-through blocking layer 113. The punch-through blocking layer 113 may also include the well regions 103a, 103b located at the first insulation A portion near the surface of layer 112. For an opposite type of FET formed on the same semiconductor substrate, the active region of the FET of the second conductivity type may be masked by a mask, and the ion implantation described above is performed for the FET of the first conductivity type to form a second conductivity type The punch-through blocking layer 113. The active region of the FET of the first conductivity type is then masked by a mask, and the ion implantation described above is performed for the FET of the second conductivity type to form a punch-through blocking layer 113 of the first conductivity type.

Different dopants can be used for different types of FETs. A P-type dopant such as B may be used in the N-type FET, and an N-type dopant such as P, As may be used in the P-type FET. As a result, the punch-through blocking layer ₁₃ separates the semiconductor fins ₁₀₄ ' from the well regions _103a , 103b in the semiconductor substrate ₁₀ . Also, the doping type of the punch-through blocking layer 113 is opposite to that of the source and drain regions, and is higher than the doping concentration of the well regions 103a, 103b in the semiconductor substrate 101. Although the well regions 103a, 103b can open the leakage current path between the source and drain regions, to some extent function as a punch-through blocking layer, the additional highly doped punch-through blocking layer 113 underlying the semiconductor fins 104' The effect of suppressing leakage current between the source region and the drain region can be further improved.

Then, a front gate dielectric 114 (silicon oxide or silicon nitride) is formed on the surface of the semiconductor structure by the above-described known deposition process. In one example, the front gate dielectric 114 is a silicon oxide layer that is about 0.8-1.5 nm thick. Front gate dielectric 114 covers each of the sides of the two semiconductor fins 104'. Then, a front gate conductor 115 (e.g., doped polysilicon) is formed on the surface of the semiconductor structure by the above-described known deposition process, as shown in FIG. If necessary, the front gate conductor 115 can be subjected to chemical mechanical polishing (CMP) to obtain a flat surface.

The conductor layer is then patterned into a front gate conductor 115 that intersects the semiconductor fin 104' using a photoresist mask. The photoresist layer is then removed by dissolving or ashing in a solvent. A nitride layer is formed on the surface of the semiconductor structure by the above-described known deposition process. In one example, the nitride layer is a silicon nitride layer having a thickness of about 5-20 nm. The laterally extending portion of the nitride layer is removed by an anisotropic etching process (eg, reactive ion etching) such that a vertical portion of the nitride layer on the side of the front gate conductor 115 remains, thereby forming a gate spacer 116, This is shown in Figures 13a, 13b, 13c and 13d.

Typically, the nitride layer on the side of the semiconductor fin 104' is due to a form factor (eg, a gate conductor layer (eg, doped polysilicon) having a thickness greater than twice the height of the fin, or a top and bottom fin shape) The thickness is smaller than the thickness of the nitride layer on the side of the front gate conductor 115, so that the nitride layer on the side of the semiconductor fin 104' can be completely removed in this etching step. Otherwise, the nitride layer on the side of the semiconductor fin 104' will affect the formation of subsequent source/drain regions. An additional mask can be used to further remove the side of the semiconductor fin 104' Nitride layer.

The front gate conductor 115 and the front gate dielectric 114 together form a gate stack. In the examples shown in Figs. 13a, 13b, 13c and 13d, the front gate conductor 115 is in the form of a strip and extends in a direction perpendicular to the length of the semiconductor fin.

In a subsequent step, the source and drain regions associated with the channel regions provided by the semiconductor fins 104' may be formed in a conventional process with the front gate conductor 115 and the gate spacers 116 as hard masks. In one example, the source and drain regions can be doped regions formed by ion implantation or in situ doping across the semiconductor fins 104'. In another example, the source and drain regions may be doped regions formed by ion implantation or in-situ doping in an additional semiconductor layer in contact with both ends or sides of the semiconductor fins 104'.

An exemplary flow of a portion of a stage of a method of fabricating a semiconductor device in accordance with a further preferred embodiment of the present invention is described with reference to Figures 14-15, wherein the top and bottom views of the semiconductor structure are shown in Figures 14a and 15a, A cross-sectional view of the semiconductor structure taken along line AA in the width direction of the semiconductor fin is shown in FIGS. 14b and 15b, and a cross-sectional view of the semiconductor structure taken along line BB in the width direction of the semiconductor fin is shown in FIGS. 14c and 15c. A cross-sectional view of the semiconductor structure taken along line CC in the length direction of the semiconductor fin is shown in FIGS. 14d and 15d.

According to the preferred embodiment, the steps shown in Figs. 14 and 15 are further performed after the step shown in Fig. 13 to form a stress acting layer.

Then, a stress acting layer 117 is epitaxially grown on the exposed side of the semiconductor fin 104' by the above-described known deposition process, as shown in Figs. 14a, 14b, 14c and 14d. A stress acting layer 117 is also formed on the front gate conductor 115. The thickness of the stressed layer 117 should be sufficient to apply the desired stress on the semiconductor fins 104'.

Different stress layers 117 can be formed for different types of FinFETs. By applying a suitable stress to the channel region of the FinFET through the stress-applying layer 117, the carrier mobility can be increased, thereby reducing the on-resistance and increasing the switching speed of the device. To this end, the stressor layer 117 is formed using a semiconductor material different from the material of the semiconductor fin 104' to produce a desired stress. For the N-type FinFET, the stress acting layer 117 is, for example, a Si:C layer having a C content of about 0.2 to 2% by atom on the Si substrate, and a tensile stress is applied to the channel region along the longitudinal direction of the channel region. . For the P-type FinFET, the stress acting layer 117 is, for example, a SiGe layer having a Ge content of about 155% by atom on the Si substrate, and compressive stress is applied to the channel region along the longitudinal direction of the channel region.

Then, a second insulating layer 118 is formed on the surface of the semiconductor structure by the above-described known deposition process. In one example, the second insulating layer 118 is, for example, a silicon oxide layer and is thick enough to fill the semiconductor. The opening in the etching step of the fin 104' is located on the side of the semiconductor fin 104' and also covers the top surface of the front gate conductor 115. The second insulating layer 118 is chemically mechanically polished with the gate spacers 116 as a stop layer to obtain a flat surface as shown in Figs. 15a, 15b, 15c and 15d. The chemical mechanical polishing removes a portion of the stressor layer 117 above the front gate conductor 115 and exposes the top surface of the front gate conductor 115.

Further, as described above, in a subsequent step, the source of the channel region provided by the semiconductor fin 104' may be formed by using the conventional gate process 115 and the gate spacer 116 as a hard mask in a conventional process. Zone and drain zone. In one example, the source and drain regions can be doped regions formed by ion implantation or in-situ doping at both ends of the semiconductor fin 104'. In another example, the source and drain regions may be doped regions formed by ion implantation or in-situ doping in an additional semiconductor layer in contact with both ends or sides of the semiconductor fins 104'.

An exemplary flow of a portion of a stage of a method of fabricating a semiconductor device in accordance with a further preferred embodiment of the present invention is described with reference to Figures 16-18, wherein a top view of the semiconductor structure and a cut-out position of the cross-sectional view are shown in Figures 16a, 17a and 18a A cross-sectional view of the semiconductor structure taken along line AA in the width direction of the semiconductor fin is shown in FIGS. 16b, 17b, and 18b, and is shown in FIGS. 16c, 17c, and 18c along the line BB in the width direction of the semiconductor fin. A cross-sectional view of the semiconductor structure is shown in Figs. 16d, 17d and 18d as a cross-sectional view of the semiconductor structure taken along line CC in the length direction of the semiconductor fin.

According to the preferred embodiment, the sacrificial gate conductor 114' and the sacrificial gate dielectric 113' are formed in the step of FIG. 12, and the stress acting layer 117 is formed after the step shown in FIG. 17, and the source and drain regions have been formed, and then The steps of FIGS. 18 and 19 are further performed to replace the sacrificial gate stack including the sacrificial gate conductor 114' and the sacrificial gate dielectric 113' with a replacement gate stack including a replacement gate conductor and a replacement gate dielectric.

Using the second insulating layer 118 and the gate spacer 116 as a hard mask, the sacrificial gate conductor 114' is removed by the above-described known etching process (eg, reactive ion etching) to form a gate opening, as shown in FIGS. 16a, 16b, 16c. And shown in 16d. Alternatively, the portion of the sacrificial gate dielectric 113' located at the bottom of the gate opening may be further removed. In accordance with the back gate process, a replacement gate dielectric 119 is formed in the gate opening, as shown in Figures 17a, 17b, 17c and 17d, and the gate opening is filled with a conductive material to form a replacement gate conductor 120, as in Figures 18a, 18b, 18c And shown in 18d. The replacement gate conductor 120 and the replacement gate dielectric 119 together form a replacement gate stack. In one example, the replacement gate dielectric 119 is an HfO ₂ layer having a thickness of about 0.3 nm to 1.2 nm, and the replacement gate conductor 120 is, for example, a TiN layer.

According to various embodiments described above, after forming the source and drain regions, an interlayer insulating layer, a plug in the interlayer insulating layer, a wiring on the upper surface of the interlayer insulating layer, or Electricity Extremely, thereby completing other parts of the semiconductor device.

Figure 19 shows an exploded perspective view of a semiconductor device 100 in accordance with a preferred embodiment of the present invention, wherein the second insulating layer 118 is not shown for clarity. The semiconductor device 100 is formed using the steps illustrated in Figures 1-18 to include various preferred aspects of the present invention, but should not be construed as limiting the present invention to a combination of the various preferred aspects. Moreover, the materials already mentioned above are not repeated for the sake of brevity.

The semiconductor device 100 includes a semiconductor substrate 101, a back gate isolation structure composed of well regions 102a, 102b, 103a, 103b and a shallow trench isolation 105 in the semiconductor substrate 101. The semiconductor device 100 includes opposite types of FETs 100a, 100b formed in the semiconductor layers on the well regions 103a, 103b, respectively. The doping types of well regions 102a, 102b, 103a, and 103b are related to the conductivity type of the FET, and form a conductive path for the back gate and a back gate isolation structure that separates one FET from the adjacent FET and semiconductor substrate 101. The back gate isolation structure allows the paths formed by the well regions 103a-102a-102b-103b to always constitute a P PN junction or a P P junction. The well regions 103a, 103b also serve as part of the conductive path of the back gate conductor 111. The FETs 100a, 100b respectively include a sandwich structure on the well regions 103a, 103b. The sandwich structure includes a back gate conductor 111, two semiconductor fins 104' on either side of the back gate conductor 111, and a respective back gate dielectric 110 separating the back gate conductor 111 from the two semiconductor fins 104', respectively. The punch-through blocking layer 113 is located below the semiconductor fin 104'. The front gate stack intersects the semiconductor fins 104', which include a front gate dielectric and a front gate conductor, and the front gate dielectric separates the front gate conductors from the semiconductor fins 104'.

In the example shown in Figure 19, the front gate dielectric is a replacement gate dielectric 119 formed in accordance with a back gate process, which is a replacement gate conductor 120 formed in accordance with a back gate process. The gate spacers 116 are located on the side of the replacement gate conductor 120. During the back gate process, although the portion of the sacrificial gate dielectric 113' located within the gate opening is removed, the portion below the gate spacer 116 remains.

In addition, the insulating cap 109' is located above the back gate conductor 111 and separates the back gate conductor 111 from the replacement gate conductor 120. The first insulating layer 112 is located between the replacement gate dielectric 119 and the well regions 103a, 103b, and separates the replacement gate dielectric 119 from the well regions 103a, 103b.

Semiconductor device 100 also includes source and drain regions associated with the channel regions provided by semiconductor fins 104'. In the example shown in FIG. 19, the source and drain regions may be doped regions formed by ion implantation or in-situ doping at both ends of the semiconductor fin 104'. An additional stress active layer 117 is in contact with the side of the semiconductor fin 104'. The two opposite types of FETs 100a, 100b each include two semiconductor fins 104'. Plungers 121 are connected through the interlayer insulating layers to the source and drain regions of respective semiconductor fins 104' of each FET, respectively. Additional plungers 121 are connected to the alternate gate conductors 120 of each FET, and additional additional electrodes 121 are passed through the layers. The insulating layer and the first insulating layer 112 are connected to the well regions 102a, 102b, 103a, 103b, respectively, so that a voltage can be applied. The well regions 102a, 102b, 103a, 103b and the shallow trench isolation 105 form a back gate isolation structure such that different voltages can be applied to the back gates 111 of the two opposite types of FETs via the well regions 103a, 103b, respectively, thereby correspondingly Adjust the threshold voltage of each FET.

In the above description, detailed descriptions of the technical details such as patterning and etching of the respective layers have not been made. However, it will be understood by those skilled in the art that layers, regions, and the like of a desired shape can be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method that is not exactly the same as the method described above. In addition, although the respective embodiments have been described above, this does not mean that the measures in the respective embodiments are not advantageously used in combination.

The embodiments of the present invention have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the invention. The scope of the invention is defined by the appended claims and their equivalents. Numerous alternatives and modifications may be made by those skilled in the art without departing from the scope of the invention.

Claims

Rights request

1. A semiconductor device, including:

semiconductor substrate;

Back gate isolation structures in semiconductor substrates; and

adjacent field effect transistors on back gate isolation structures,

Wherein, each of the adjacent field effect transistors includes a sandwich structure located on a back gate isolation structure, the sandwich structure includes a back gate conductor, semiconductor fins located on both sides of the back gate conductor, and connecting the back gate conductor with The semiconductor fins are separated by their respective back gate dielectrics,

Wherein, the back gate isolation structure serves as a part of the conductive path of the back gate conductors of the adjacent field effect transistors, and a PPN junction or PP junction is formed between the back gate conductors of the adjacent field effect transistors.

2. The semiconductor device according to claim 1, further comprising a punch-through stopper layer located under the semiconductor fin.

3. The semiconductor device according to claim 2, wherein the doping type of the punch-through stopper layer is opposite to the conductivity type of the field effect transistor.

4. The semiconductor device of claim 1, further comprising an additional stressor layer in contact with the sides of the semiconductor fin.

5. The semiconductor device according to claim 1, wherein the back gate isolation structure includes:

laterally adjacent first well regions and second well regions;

third well regions and fourth well regions respectively located above the first well region and the second well region and adjacent to the first well region and the second well region respectively; and

The shallow trench that separates the third well region and the fourth well region is isolated,

Wherein, the back gate conductor of the first field effect transistor among the adjacent field effect transistors is in contact with the third well region, and the back gate conductor of the second field effect transistor is in contact with the fourth well region.

6. The semiconductor device according to claim 5, wherein the conductivity type of the first transistor is opposite to that of the second transistor, and the doping type of the first well region is the same as the conductivity type of the first field effect transistor, and the third The doping type of the well region is opposite to the conductivity type of the first field effect transistor, the doping type of the second well region is the same as the conductivity type of the second field effect transistor, and the doping type of the fourth well region is the same as the conductivity type of the second field effect transistor. The conductivity type is opposite.

7. The field effect transistor according to claim 6, wherein between the third well region-the first well region-the second well region, A P PN junction or PP junction is formed on the path of the fourth well region.

8. A method of manufacturing a semiconductor device, including:

Forming a back gate isolation structure in the semiconductor substrate such that the portion of the semiconductor substrate located above the back gate isolation structure forms a semiconductor layer; and

Adjacent field effect transistors are formed on the back gate isolation structure, including:

forming a plurality of mask layers on the semiconductor layer;

forming an opening in a topmost one of the plurality of mask layers;

Another mask layer in the form of side walls is formed on the inner wall of the opening;

Using the other mask layer as a hard mask, extend the opening through the plurality of mask layers and the semiconductor layer to the back gate isolation structure;

Form a back gate dielectric on the inner wall of the opening;

forming a back gate conductor in the opening;

forming an insulating cap including the other mask layer in the opening, the insulating cap covering the back gate dielectric and the back gate conductor;

Using an insulating cap as a hard mask, the semiconductor layer is patterned into a semiconductor fin; among them, a back gate conductor, semiconductor fins formed by the semiconductor layer located on both sides of the back gate conductor, and the back gate conductor and the semiconductor fin The respective spaced back gate dielectrics form a sandwich structure with an insulating cap separating the back gate conductor from the front gate conductor,

9. The semiconductor device according to claim 8, further comprising forming a punch-through blocking layer under the semiconductor fin between the steps of patterning the semiconductor layer and forming the front gate stack.

10. The method of claim 9, wherein forming the punch-through blocking layer includes performing ion implantation to introduce a dopant into a portion of the semiconductor fin adjacent to the well region.

11. The method of claim 10, wherein forming the punch-through blocking layer includes forming an insulating layer to define a position of the punch-through blocking layer before performing ion implantation.

12. The method of claim 10, wherein a dopant type used in the step of forming the punch-through stopper layer is opposite to a conductivity type of the field effect transistor.

13. The method of claim 8, further comprising forming an epitaxially grown stress layer on a side surface of the semiconductor fin.

14. The method of claim 8, wherein forming the back gate isolation structure includes:

forming a first well region in the semiconductor substrate;

forming a third well region on the first well region;

forming a second well region in the semiconductor substrate, the second well region being laterally adjacent to the first well region;

forming a fourth well region on the second well region;

Form shallow trench isolation to separate the third well region and the fourth well region,

15. The method according to claim 14, wherein a PPN junction or a PP junction is formed on a path from the third well region to the first well region to the second well region and the fourth well region.

16. The method according to claim 14, wherein the doping atom concentration of the first well region, the second well region, the third well region and the fourth well region is 10 ¹⁶ _C m lj 10 ¹⁹ cm- ³ .