WO2014121543A1

WO2014121543A1 - Semiconductor device and manufacturing method thereof

Info

Publication number: WO2014121543A1
Application number: PCT/CN2013/072813
Authority: WO
Inventors: 朱慧珑
Original assignee: 中国科学院微电子研究所
Priority date: 2013-02-08
Filing date: 2013-03-18
Publication date: 2014-08-14
Also published as: CN103985753A; CN103985753B

Abstract

Provided are a semiconductor device and manufacturing method thereof, the semiconductor device comprising: a semiconductor substrate (101), a well region (102) in the semiconductor substrate (101), a contact region (109) in the well region (102), a sandwich structure located on the well region (102), a front-gate stack intersecting with semiconductor fins (103'), an insulation cap (107') located above a metal back-gate (110) and the semiconductor fins (103'), and a source region and a drain region connected with a channel region provided by the semiconductor fins (103'). The sandwich structure comprises the metal back-gate (110), the semiconductor fins (103') located on the two sides of the metal back-gate (110), and respective back-gate dielectrics (108) each isolating the metal back-gate (110) from the semiconductor fins (103'); the contact region (109) and the well region (102) are part of the conductive path of the metal back-gate (110), and the metal back-gate (110) is connected to the well region (102) via the contact region (109); the front-gate stack comprises a front-gate dielectric (113) and a front-gate conductor (114), and the front-gate dielectric (113) isolates the front-gate conductor (114) from the semiconductor fins (103'); and the insulation cap (107') isolates the metal back-gate (110) from the front-gate conductor (114). The semiconductor device realizes high integration and low power consumption.

Description

The present application claims priority to Chinese Patent Application No. 201310050114.2, entitled "Semiconductor Device and Its Manufacturing Method", filed on February 8, 2013, the entire contents of In this application. Technical field

The present invention relates to semiconductor technology and, more particularly, to a semiconductor device including a fin (Fm) and a method of fabricating the same. Background technique

With the development of semiconductor technology, it is desirable to reduce the power consumption while reducing the size of a semiconductor device to improve integration. In order to suppress the short channel effect due to size reduction, a FinFET formed on an SOI wafer or a bulk semiconductor substrate has been proposed. The FinFET includes a channel region formed in the middle of the fin of the semiconductor material, and source/drain regions formed at both ends of the fin. The gate electrode surrounds the channel region (i.e., the double gate structure) at least on both sides of the channel region, thereby forming an inversion layer on each side of the channel. Since the entire channel region can be controlled by the gate, it is possible to suppress the short channel effect. In order to reduce power consumption due to leakage, a UTBB (Ultra-thin buried oxide body) type FET formed in a semiconductor substrate has been proposed. The UTBB type FET includes an ultra-thin buried oxide layer in a semiconductor substrate, a front gate and source/drain regions over the ultra-thin oxide buried layer, and a back gate under the ultra-thin buried oxide layer. In operation, by applying a bias voltage to the back gate, power consumption can be significantly reduced while maintaining the same speed.

Despite their respective advantages, a semiconductor device that combines the advantages of both has not been proposed because of the many difficulties in forming a back gate in a FinFET. In a bulk semiconductor substrate-based FinFET, since the contact area of the semiconductor fin to the semiconductor substrate is small, the formed back gate will cause a severe self-heating effect. In a FinFET based on an SOI wafer, a high cost problem arises due to the high price of the SOI wafer. Moreover, the formation of the back gate on the SOI wafer requires precise controlled ion implantation through the top semiconductor layer to form an implant region for the back gate under the buried insulating layer, resulting in process difficulties resulting in low yield, and due to the trench Unintentional doping Causes device performance to fluctuate. Summary of the invention

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device which utilizes fins and a back gate to improve performance and a method of fabricating the same.

According to an aspect of the present invention, a semiconductor device is provided, comprising: a semiconductor substrate; a well region in the semiconductor substrate; a contact region in the well region; a sandwich structure on the well region, the sandwich structure including the back gate metal a semiconductor fin on both sides of the back gate metal, and a respective back gate dielectric separating the back gate metal from the semiconductor fin, wherein the contact region and the well region are part of a conductive path of the back gate metal, and the back gate a metal is connected to the well region via the contact region; a front gate stack intersecting the semiconductor fin, the front gate stack including a front gate dielectric and a front gate conductor, and the front gate dielectric separating the front gate conductor from the semiconductor fin; An insulating cap over the metal and over the semiconductor fin, and the insulating cap separates the back gate metal from the front gate conductor; and source and drain regions connected to the channel region provided by the semiconductor fin.

According to another aspect of the present invention, a method of fabricating a semiconductor device is provided, comprising: forming a well region in a semiconductor substrate such that a portion of the semiconductor substrate above the well region forms a semiconductor layer; forming a plurality of layers on the semiconductor layer a mask layer; forming an opening in a topmost one of the plurality of mask layers; forming another mask layer in the form of a sidewall in the inner wall of the opening; using the other mask layer as a hard mask, Openings extend through the plurality of mask layers and the semiconductor layer to the well region; forming a contact region in the well region via the opening; forming a back gate dielectric in the inner wall of the opening; forming a back gate metal in the opening; forming in the opening An insulating cap comprising the another mask layer and covering the back gate dielectric and the back gate metal; using the insulating cap as a hard mask to pattern the semiconductor layer into semiconductor fins; forming and semiconductor fins An intersecting front gate stack, the front gate stack includes a front gate dielectric and a front gate conductor, and the front gate dielectric separates the front gate conductor from the semiconductor fin; and forms a half A source region connected to the body-provided fin and a drain region. metal. Since the back gate metal is not formed under the semiconductor fins, the contact area between the back gate metal and the well region as a part of the conductive path can be independently determined as needed to avoid the self-heating effect of the back gate metal. Also, since it is not necessary to perform through the semiconductor fins when forming the back gate metal Ion implantation can therefore avoid unintentional doping of the channel region and cause device performance fluctuations. Further, the back gate metal is connected to the well region via the contact region, so that the contact resistance between the back gate metal and the well region can be reduced. According to a preferred embodiment, the contact region is opposite to the conductivity type of the well region, thereby forming a PN junction, and the threshold voltage of the semiconductor device can be adjusted.

The semiconductor device combines the advantages of FinFET and UTBB type FETs. On the one hand, the back gate metal can be used to control or dynamically adjust the threshold voltage of the semiconductor device, and the power consumption can be significantly reduced while maintaining the speed. On the other hand, Fin can be utilized. The short channel effect is suppressed, and the performance of the semiconductor device is maintained when the semiconductor device is shrunk. Therefore, the semiconductor device can reduce power consumption while reducing the size of the semiconductor device to improve integration. Further, and the method of manufacturing the semiconductor device is compatible with the conventional semiconductor process, the manufacturing cost is low. DRAWINGS

The above and other objects, features and advantages of the present invention will become more apparent from

1-16 are schematic views showing semiconductor structures at various stages of a method of fabricating a semiconductor device in accordance with one embodiment of the present invention.

17-18 are schematic views of semiconductor structures at a portion of a stage of a method of fabricating a semiconductor device in accordance with a further preferred embodiment of the present invention.

19-20 are schematic diagrams showing semiconductor structures at a portion of a stage of a method of fabricating a semiconductor device in accordance with a further preferred embodiment of the present invention.

detailed description

The invention will be described in more detail below with reference to the accompanying drawings. In the respective drawings, the same elements are denoted by like reference numerals. For the sake of clarity, the various parts in the figures are not drawn to scale.

For the sake of brevity, the semiconductor structure obtained after several steps can be described in one figure. It should be understood that when describing a structure of a device, when a layer or a region is referred to as being "above" or "above" another layer, another region may be directly above another layer or another region, or Other layers or regions are also included between it and another layer. And if the device is to be Flip, the layer, one area will be located on the other layer, another area "below" or "below".

In the case of a description directly above another layer or another area, this document will use the expression "directly above" or "above and adjacent to".

In the present application, the term "semiconductor structure" refers to a general term for the entire semiconductor structure formed in the various steps of fabricating a semiconductor device, including all layers or regions that have been formed. Many specific details of the invention are described below, such as the structure, materials, dimensions, processing, and techniques of the invention, in order to provide a clear understanding of the invention. However, the invention may be practiced without these specific details, as will be understood by those skilled in the art.

Unless otherwise indicated below, various portions of the semiconductor device can be constructed from materials well known to those skilled in the art. The semiconductor material includes, for example, a group III-V semiconductor such as GaAs, InP, GaN, SiC, and a Group IV semiconductor such as Si, Ge. The gate conductor may be formed of various materials capable of conducting electricity, such as a metal layer, a doped polysilicon layer, or a stacked gate conductor including a metal layer and a doped polysilicon layer, or other conductive materials such as TaC, TiN, TaTbN, TaErN. , TaYbN, TaSiN, HfSiN, MoSiN, uTax, NiTax, MoNx, TiSiN, TiCN, TaAlC, Tihui, TaN, PtSix, Ni ₃ Si, Pt, Ru, Ir, Mo, W, Hf u, RuOx and each A combination of conductive materials. The gate dielectric may be composed of Si〇 ₂ or a material having a dielectric constant greater than Si〇 ₂ , including, for example, oxides, nitrides, oxynitrides, silicates, aluminates, titanates, wherein the oxide includes, for example, Si 〇 ₂ , Hf0 ₂ , Zr 〇 ₂ , A1 ₂ 0 ₃ , Ti 〇 ₂ , La ₂ 0 ₃ , the nitride includes, for example, Si ₃ N ₄ , the silicate includes, for example, HfSiOx, and the aluminate includes, for example, LaA10 ₃ , titanic acid The salt includes, for example, SrTi0 ₃ , and the oxynitride includes, for example, SiON. Also, the gate dielectric may be formed not only by materials well known to those skilled in the art, but also materials developed for the gate dielectric in the future.

The present invention can be embodied in various forms, some of which are described below.

An exemplary flow of a method of fabricating a semiconductor device in accordance with one embodiment of the present invention is described with reference to FIGS. 1-16, wherein a top view and a cross-sectional view of the cross-sectional view of the semiconductor structure are shown in FIG. 16a, in FIGS. 1-15 and 16b. A cross-sectional view of the semiconductor structure taken along line AA in the width direction of the semiconductor fin is shown, and a cross-sectional view of the semiconductor structure taken along line BB in the width direction of the semiconductor fin is shown in FIG. 16c, which is shown in FIG. 16d. A cross-sectional view of the semiconductor structure taken along line CC in the length direction of the semiconductor fin.

The method begins with a bulk semiconductor substrate 101. Forming a well in the bulk semiconductor substrate 101 The region 102, such that a portion of the semiconductor substrate 101 above the well region 102 forms a semiconductor layer 103, and the well region 102 separates the semiconductor layer 103 from the semiconductor substrate 101. A process of forming the well region 102 in the semiconductor substrate 101 is known, for example, by ion implantation to form a doped region in the semiconductor layer and then annealed to activate the dopant in the doped region. An N-type well region 102 may be formed for the P-type FET, and a P-type well region 102 may be formed for the N-type FET. Further, the first mask layer 104 is sequentially formed on the semiconductor layer 103 by a known deposition process such as electron beam evaporation (EBM), chemical vapor deposition (CVD), atomic layer deposition (ALD), sputtering, or the like. The second mask layer 105 and the third mask layer 106. Then, a photoresist layer PR is formed on the third mask layer 106, for example, by spin coating, and the photoresist layer PR is formed to define a pattern of the back gate by a photolithography process including exposure and development therein. (For example, an opening having a width of about 15 nm to 100 nm), as shown in FIG.

The semiconductor substrate 101 is composed of one selected from the group consisting of Si, Ge, SiGe, GaAs, GaSb, AlAs, InAs, MP, GaN, SiC, InGaAs, InSb, and InGaSb. In one example, the semiconductor substrate 101 is, for example, a single crystal silicon substrate. As will be described below, the semiconductor layer 103 will form semiconductor fins and determine the approximate height of the semiconductor fins. Process parameters that control ion implantation and annealing can be controlled as needed to control the depth and extent of well region 102. As a result, the semiconductor layer 103 of a desired thickness can be obtained.

The first mask layer 104, the second mask layer 105, and the third mask layer 106 may be composed of materials of desired chemical and physical properties to achieve desired etch selectivity in the etching step, and/or in chemistry Mechanical polishing (CMP) acts as a stop layer, and/or as an insulating layer in the final semiconductor device. Also, the first mask layer 104, the second mask layer 105, and the third mask layer 106 may be formed using the same or different deposition processes described above, depending on the materials used. In one example, the first mask layer 104 is a silicon oxide layer having a thickness of about 5-15 nm formed by thermal oxidation, and the second mask layer 105 is amorphous silicon having a thickness of about 50 nm to 200 nm formed by sputtering. The third mask layer 106 is a silicon nitride layer formed by sputtering and having a thickness of about 5-15 awake.

Then, using the photoresist layer PR as a mask, by dry etching, such as ion milling etching, plasma etching, reactive ion etching, laser ablation, or by wet etching using an etchant solution, from top to bottom The exposed portions of the third mask layer 106 and the second mask layer 105 are removed to form openings, as shown in FIG. The etching step is stopped at the top of the first mask layer due to the selectivity of the etching, or by controlling the etching time. Different layers can be etched separately by etching in multiple steps. In one example, the first The one-step etching includes removing the exposed portion of the third mask layer 106, for example, composed of silicon nitride, with respect to, for example, a second mask layer 105 composed of amorphous silicon using a reactive etchant using a suitable etchant. The second etching comprises removing the upper second mask layer 105, for example composed of amorphous silicon, with respect to a first mask layer 104 consisting of, for example, silicon oxide, using reactive ion etching, using another suitable etchant. The exposed part.

Then, the photoresist layer PR is removed by dissolving or ashing in a solvent. A conformal fourth mask layer 107 is formed on the surface of the semiconductor structure by the above-described known deposition process. The portion of the fourth mask layer 107 that extends laterally over the third mask layer 106 and the bottom portion of the opening (ie, the first mask layer 104) are removed by an anisotropic etching process (eg, reactive ion etching). In part, the portion of the fourth mask layer 107 on the inner wall of the opening is left to form a side wall, as shown in FIG. As will be described below, the fourth mask layer 107 will be used to define the width of the semiconductor fins. The thickness of the fourth mask layer 107 can be controlled in accordance with the desired width of the semiconductor fins. In one example, the fourth mask layer 107 is a silicon nitride layer having a thickness of about 3 nm to 28 nm formed by atomic layer deposition.

Then, using the third mask layer 106 and the fourth mask layer 107 as a hard mask, the exposed portion of the first mask layer 104 is removed through the opening by the above-described known etching process. And the exposed portions of the semiconductor layer 103 and the well region 102 are further etched until passing through the semiconductor layer 103 and reaching a predetermined depth in the well region 102, as shown in FIG. The depth of the portion of the opening in the well region 102 can be determined according to design requirements, and the depth of the portion can be controlled by controlling the etching time. In one example, the depth of the portion is, for example, about 10 nm to 30 nm, and thus may be large enough to prevent dopants in the well region 102 from diffusing into the semiconductor fins in subsequent steps.

A conformal dielectric layer is then formed over the surface of the semiconductor structure by the known deposition process described above. Removing the portion of the dielectric layer that extends laterally over the third mask layer 106 and the bottom portion of the opening (ie, the exposed surface of the well region 102 within the opening) is removed by an anisotropic etch process (eg, reactive ion etching) In part, the portion of the dielectric layer on the inner wall of the opening remains such that a back gate dielectric 108 in the form of a sidewall is formed, as shown in FIG. Instead of the process in which the dielectric layer is deposited, the back gate dielectric 108 in the form of an oxide spacer can be formed directly on the sidewalls of the semiconductor layer 103 and the well region 102 located within the opening by thermal oxidation, thereby eliminating the need for subsequent anisotropic etching. This can be further cylinderized. In one example, back gate dielectric 108 is a silicon oxide layer having a thickness of between about 10 nm and 30 nm. Then, using the third mask layer 106 and the fourth mask layer 107 as a hard mask, a dopant is implanted into the well region 102 through the opening by ion implantation, thereby forming a contact region 109 in the well region 102 at the bottom of the opening, As shown in Figure 6. The doping type of the contact region 109 may be the same as or opposite to the doping type of the well region 102. In the case where the doping types are the same, the doping type of the contact region 109 but the doping concentration is higher than that of the well region 102. In one example, the doping concentration of the contact region 109 is, for example, Ι χ ΙΟ ¹⁸ cm" ^{3 -} l χ 10 ²¹ cm" _0. As will be described later, the well region 102 serves as a conductive material of the back gate metal to be formed in the opening. Part of the path. The highly doped contact region 109 at the bottom of the opening can reduce the contact resistance between the back gate metal and the well region 102. In the case where the doping types of the two are opposite, the contact region 109 forms a PN junction with the well region 102, and the electric field generated in the back gate metal can be adjusted during operation to further adjust the threshold voltage of the semiconductor device.

Then, a conductor layer is formed on the surface of the semiconductor structure by the above-described known deposition process. The conductor layer fills at least the opening. The conductor layer is etched back to remove portions located outside the opening, and a portion of the conductor layer located within the opening is further removed to form a back gate metal 110 within the opening, as shown in FIG. The back gate metal 110 and the semiconductor layer 103 are separated by a back gate dielectric 108. The back gate metal 110 is selected from the group consisting of TaC, TiN, TaTbN, TaErN, TaYbN, TaSiN, HfSiN, MoSiN, RuTax, NiTax, MoNx, TiSiN, TiCN, TaAlC, TiAlN, TaN, RSix, Ni ₃ Si, Pt, Ru, Ir At least one of Mo, W, Hf u, and RuOx. In one example, the back gate metal 110 is composed of TiN.

The etch back used to form the back gate metal 110 is such that the top of the back gate metal 110 is below the back gate dielectric 108. Alternatively, the back gate dielectric 108 can be selectively etched back relative to the back gate metal 110 such that the tops of the back gate dielectric 108 and the back gate metal 110 are flush.

Then, in the case where the mask is not used, the third mask layer 106 located above the second mask layer 105 is selectively completely removed with respect to the second mask layer 105 by the above-described known etching process, thereby The surface of the second mask layer 105 is exposed. In one example, in the case where the second mask layer 105 is composed of amorphous silicon and the third mask layer 106 is composed of silicon oxide, silicon oxide can be selectively removed using hydrofluoric acid as an etchant. An insulating layer is formed on the surface of the semiconductor structure by the above-described known deposition process. The insulating layer fills at least the opening to cover the top surface of the back gate metal 110. The insulating layer is etched back to remove a portion located outside the opening. In one example, the insulating layer is a silicon nitride layer formed by sputtering. The insulating layer and the fourth mask layer 107 together form an insulating cap 107', as shown in the figure 8 is shown. The etch may further remove a portion of the insulating layer that is within the opening. By controlling the time of the etch back, the portion of the insulating layer that is within the opening covers the top of the back gate metal 110 and provides the desired electrical insulation properties.

Then, in the case where the mask is not used, the second mask layer 105 is selectively completely removed with respect to the insulating cap 107' and the first mask layer 104 by the above-described known etching process, thereby exposing the first The surface of the mask layer 104 is as shown in FIG. In one example, in the case where the first mask layer 104 is composed of silicon oxide, the second mask layer 105 is composed of amorphous silicon, and the insulating cap 107' is composed of silicon nitride, tetramethyl hydroxide can be used. The amorphous silicon is selectively removed by using (TMAH) as an etchant.

Then, using the insulating cap 107' as a hard mask, the exposed portion of the semiconductor layer 103 is completely removed by the above-described known etching process. And the exposed portion of the well region 102 is further etched until a predetermined depth is reached, as shown in FIG. As will be described below, well region 102 will be part of the conductive path of the back gate. The depth of the etch can be controlled by controlling the etch time such that the well region 102 maintains a certain thickness to reduce the associated parasitic resistance.

The etch engraves the semiconductor layer 103 into two fins 103 on both sides of the back gate metal 110. The back gate metal 110 and the two semiconductor fins 103' are separated by respective back gate dielectrics 108 to form fins. The sandwich structure of the Fin-Back Gate-Fm. The semiconductor fin 103' is a part of the initial semiconductor substrate 101, and thus is also composed of a group selected from the group consisting of Si, Ge, SiGe, GaAs, GaSb, AlAs, InAs, InP, GaN, SiC, InGaAs, InSb, and InGaSb. A composition. In the example shown in FIG. 10, the shape of the semiconductor fin 103' is a strip having a length along a direction perpendicular to the plane of the paper, a width along a lateral direction in the plane of the paper, and a height along the plane of the paper. Vertical direction. The height of the semiconductor fin 103' is substantially determined by the thickness of the initial semiconductor layer 103, the width of the semiconductor fin 103' is substantially determined by the thickness of the initial fourth mask layer 107, and the length of the semiconductor fin 103' can be designed according to the design. Need to be defined by an additional etching step. In this etching step and subsequent process steps, the previously formed back gate metal 110 provides mechanical support and protection for the semiconductor fins 103', so that high yield can be obtained.

Then, a first insulating layer 111 is formed on the surface of the semiconductor structure by the above-described known deposition process, as shown in FIG. In one example, the first insulating layer 111 is composed of, for example, silicon oxide formed by sputtering. The thickness of the first insulating layer 111 is sufficient to fill the opening formed on the side of the semiconductor fin 103' in the etching step of forming the semiconductor fin 103', and also covers the insulating cap 107'. in case If desired, the surface of the first insulating layer 111 may be further planarized by in-situ sputtering or additional chemical mechanical polishing.

Then, the first insulating layer 111 is etched back by a selective etching process (e.g., reactive ion etching). This etching not only removes the portion of the first insulating layer 111 on the top of the insulating cap 107', but also reduces the thickness of the portion of the first insulating layer 111 located in the opening on both sides of the semiconductor fin 103'. The etching time is controlled such that the surface of the first insulating layer 111 is higher than the top of the well region 102 and exposed to the side of the semiconductor fin 103' above the well region.

As an optional step, a dopant is implanted into the first insulating layer 111 by ion implantation as shown in FIG. Due to the ion scattering of the surface, the dopant can easily enter the lower portion of the semiconductor fin 103' from the vicinity of the surface of the first insulating layer 111 such that the lower portion of the semiconductor fin 103' forms the punch-through blocking layer 112, as shown in FIG. Alternatively, an additional thermal anneal may be employed to drive dopants from the first insulating layer 111 into the semiconductor fins 103' to form the punch-through blocking layer 112. The punch-through blocking layer 112 may also include a portion of the well region 101 located near the surface of the first insulating layer 111.

Different dopants can be used for different types of FETs. A P-type dopant such as B can be used in the N-type FET, and an N-type dopant such as P, As can be used in the P-type FET. As a result, the punch-through blocking layer 112 separates the semiconductor fins 103' from the well regions 102 in the semiconductor substrate 101. Also, the doping type of the punch-through blocking layer 112 is opposite to that of the source and drain regions, and is higher than the doping concentration of the well region 102 in the semiconductor substrate 101. Although the well region 102 can break the leakage current path between the source region and the drain region to a certain extent functioning as a punch-through blocking layer, the additional highly doped through-blocking layer 112 located under the semiconductor fin 103' can further The effect of suppressing leakage current between the source and drain regions is improved.

Then, a front gate dielectric is formed on the surface of the semiconductor structure by the above-described known deposition process

113 (silicon oxide or silicon nitride), as shown in Figure 14. In one example, the front gate dielectric 113 is a silicon oxide layer that is about 0.8-1.5 nm thick. A front gate dielectric 113 covers one side of each of the two semiconductor fins 103.

Then, a front gate conductor is formed on the surface of the semiconductor structure by the above-described known deposition process

114 (for example, doped polysilicon), as shown in Figure 15. If necessary, the front gate conductor 114 can be chemical mechanically polished (CMP) to obtain a flat surface.

The conductor layer is then patterned to intersect the semiconductor fin 103' using a photoresist mask. Front gate conductor 114. The photoresist layer is then removed by dissolving or ashing in a solvent. A nitride layer is formed on the surface of the semiconductor structure by the above-described known deposition process. In one example, the nitride layer is a silicon nitride layer having a thickness of about 5-20 nm. The laterally extending portion of the nitride layer is removed by an anisotropic etching process (eg, reactive ion etching) such that a vertical portion of the nitride layer on the side of the front gate conductor 114 remains, thereby forming a gate spacer 115, This is shown in Figures 16a, 16b, 16c and 16d.

Typically, the nitride layer on the side of the semiconductor fin 103' is due to a form factor (eg, a gate conductor layer (eg, doped polysilicon) having a thickness greater than twice the height of the fin, or a top and bottom fin shape) The thickness is smaller than the thickness of the nitride layer on the side of the front gate conductor 114, so that the nitride layer on the side of the semiconductor fin 103' can be completely removed in this etching step. Otherwise, the nitride layer on the side of the semiconductor fin 103' will affect the formation of subsequent source/drain regions. An additional mask can be used to further remove the nitride layer on the side of the semiconductor fins 103.

The front gate conductor 114 and the front gate dielectric 113 together form a gate stack. In the examples shown in Figs. 16a, 16b, 16c, and 16d, the front gate conductor 114 is in the form of a strip and extends in a direction perpendicular to the length of the semiconductor fin.

In a subsequent step, the source and drain regions connected to the channel region provided by the semiconductor fin 103' may be formed in a conventional process with the previous gate conductor 114 and the gate spacer 115 as hard masks. In one example, the source and drain regions can be doped regions formed by ion implantation or in-situ doping across the semiconductor fins 103'. In another example, the source and drain regions may be doped regions formed by ion implantation or in-situ doping in an additional semiconductor layer in contact with both ends or sides of the semiconductor fin 103.

An exemplary flow of a portion of a stage of a method of fabricating a semiconductor device in accordance with a further preferred embodiment of the present invention is described with reference to Figures 17-18, wherein the top and bottom views of the semiconductor structure are shown in Figures 17a and 18a, 17b and 18b are cross-sectional views of the semiconductor structure taken along line AA in the width direction of the semiconductor fin, and sectional views of the semiconductor structure taken along line BB in the width direction of the semiconductor fin are shown in Figs. 17c and 18c. A cross-sectional view of the semiconductor structure taken along line CC in the length direction of the semiconductor fin is shown in FIGS. 17d and 18d.

According to the preferred embodiment, the steps shown in Figs. 17 and 18 are further performed after the step shown in Fig. 16 to form a stress acting layer.

Epitaxial growth stress on the exposed side of the semiconductor fin 103' by the above known deposition process The active layer 116 is shown in Figures 17a, 17b, 17c and 17d. A stress active layer 116 is also formed on the front gate conductor 114. The thickness of the stressor layer 116 should be sufficient to apply the desired stress on the semiconductor fins 103'.

Different stress active layers 116 can be formed for different types of FinFETs. Applying a suitable stress to the channel region of the FmFET through the stress-applying layer 116 can increase the carrier mobility, thereby reducing the on-resistance and increasing the switching speed of the device. To this end, the stressor layer 116 is formed using a semiconductor material different from the material of the semiconductor fin 103' to produce a desired stress. For the N-type FinFET, the stress acting layer 116 is, for example, a Si:C layer having a C content of about 0.2 to 2% by atom formed on the Si substrate, and a tensile stress is applied to the channel region along the longitudinal direction of the channel region. . For the P-type FinFET, the stress acting layer 116 is, for example, a SiGe layer having a Ge content of about 155% by atom on the Si substrate, and a compressive stress is applied to the channel region along the longitudinal direction of the channel region.

Then, a second insulating layer 117 is formed on the surface of the semiconductor structure by the above-described known deposition process. In one example, the second insulating layer 117 is, for example, a silicon oxide layer and has a thickness sufficient to fill an opening formed on the side of the semiconductor fin 103' in the etching step of forming the semiconductor fin 103', and also covers the front gate conductor 114. The top surface. The second insulating layer 117 is chemically mechanically polished with the gate spacer 115 as a stop layer to obtain a flat surface as shown in Figs. 18a, 18b, 18c and 18d. The chemical mechanical polishing removes a portion of the stressor layer 116 above the front gate conductor 114 and exposes the top surface of the front gate conductor 114.

Further, as described above, in the subsequent steps, the source connected to the channel region provided by the semiconductor fin 103' may be formed by using the conventional gate process 114 and the gate spacer 115 as a hard mask in a conventional process. Zone and drain zone. In one example, the source and drain regions may be semiconductor fins 103, doped regions formed by ion implantation or in-situ doping at both ends. In another example, the source and drain regions may be doped regions formed by ion implantation or in-situ doping in an additional semiconductor layer in contact with both ends or sides of the semiconductor fins 103.

An exemplary flow of a portion of a stage of a method of fabricating a semiconductor device in accordance with a further preferred embodiment of the present invention is described with reference to Figures 19-20, wherein the top and bottom views of the semiconductor structure are shown in Figures 19a and 20a, A cross-sectional view of the semiconductor structure taken along line AA in the width direction of the semiconductor fin is shown in FIGS. 19b and 20b, and a cross-sectional view of the semiconductor structure taken along line BB in the width direction of the semiconductor fin is shown in FIGS. 19c and 20c. , shown in Figures 19d and 20d A cross-sectional view of the semiconductor structure taken along line cc in the length direction of the semiconductor fin. According to the preferred embodiment, the sacrificial gate conductor 114' and the sacrificial gate dielectric 113' are formed in the step of FIG. 16, and the stress acting layer 116 is formed after the step shown in FIG. 18, and the source and drain regions have been formed, and then The steps of FIGS. 19 and 20 are further performed to replace the sacrificial gate stack including the sacrificial gate conductor 114' and the sacrificial gate dielectric 113' with a replacement gate stack including a replacement gate conductor and a replacement gate dielectric.

Using the second insulating layer 117 and the gate spacer 115 as a hard mask, the sacrificial gate conductor 114' is removed by the above-described known etching process (for example, reactive ion etching) to form a gate opening, as shown in FIGS. 19a, 19b, 19c. And shown in 19d. Alternatively, the sacrificial gate dielectric 113 may be further removed, the portion located at the bottom of the gate opening. In accordance with the back gate process, a replacement gate dielectric 118 and a replacement gate conductor 119 are formed in the gate opening as shown in Figures 20a, 20b, 20c and 20d. The replacement gate conductor 119 and the replacement gate dielectric 118 together form a replacement gate stack. In one example, the replacement gate dielectric 118 is a Hf 〇 ₂ layer having a thickness of about 0.3 nm to 1.2 nm, and the replacement gate conductor 119 is, for example, a TiN layer.

According to various embodiments described above, after forming the source and drain regions, an interlayer insulating layer, a plug in the interlayer insulating layer, a wiring on the upper surface of the interlayer insulating layer, or The electrodes, thereby completing other parts of the semiconductor device.

Figure 21 shows an exploded perspective view of a semiconductor device 100 in accordance with a preferred embodiment of the present invention, wherein the second insulating layer 117 is not shown for clarity. The semiconductor device 100 is formed using the steps illustrated in Figures 1-20 to include various preferred aspects of the present invention, but should not be construed as limiting the present invention to combinations of the various preferred aspects. In addition, the materials already mentioned above will not be repeated for the sake of clarity.

The semiconductor device 100 includes a semiconductor substrate 101, a well region 102 in the semiconductor substrate 101, and a sandwich structure on the well region 102. The sandwich structure includes a back gate metal 110, two semiconductor fins 103 on either side of the back gate metal 110, and respective back gate dielectrics 108 separating the back gate metal 110 from the two semiconductor fins 103', respectively. Contact region 109 and well region 102 are part of the conductive path of back gate metal 110, and back gate metal 110 is coupled to well region 102 via contact region 109. The punch-through blocking layer 112 is located below the semiconductor fin 103'. The front gate stack intersects the semiconductor fins 103, which include a front gate dielectric and a front gate conductor, and the front gate dielectric separates the front gate conductor from the semiconductor fins 103'. In the example shown in FIG. 21, the front gate dielectric is a replacement gate dielectric 118 formed in accordance with a back gate process, which is a replacement gate conductor 119 formed in accordance with a back gate process. The gate spacer 115 is located on the side of the replacement gate conductor 119. During the back gate process, although the portion of the sacrificial gate electrode 113' located within the gate opening is removed, the portion under the gate spacer 115 remains.

In addition, an insulating cap 107' is positioned over the back gate metal 110 and separates the back gate metal 110 from the replacement gate conductor 119. The first insulating layer 111 is located between the replacement gate dielectric 118 and the well region 102 and separates the replacement gate dielectric 118 from the well region 102.

The semiconductor device 100 further includes a source region 121a and a drain region 121b connected to the channel region provided by the semiconductor fin 103'. In the example shown in Fig. 21, the source region 121a and the drain region 121b may be doped regions formed by ion implantation or in-situ doping at both ends of the semiconductor fin 103'. An additional stressor layer 116 is in contact with the side of the semiconductor fin 103'. Four plungers 120 are connected to the source and drain regions of the two semiconductor fins 103, respectively, through the interlayer insulating layer. An additional ram 120 is coupled to the replacement gate conductor 119, and another additional ram 120 is coupled to the well region 102 through the interlayer insulating layer and the first insulating layer 111 to pass through the contact region 109 and the well region 102 and the back gate The metal 110 is connected.

In the above description, detailed descriptions of the technical details such as patterning and etching of the respective layers have not been made. However, it will be understood by those skilled in the art that layers, regions, and the like of a desired shape can be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method that is not exactly the same as the method described above. In addition, although the respective embodiments have been described above, this does not mean that the measures in the respective embodiments are not advantageously used in combination.

The embodiments of the present invention have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the invention. The scope of the invention is defined by the appended claims and their equivalents. Numerous alternatives and modifications can be made by those skilled in the art without departing from the scope of the invention, and such alternatives and modifications are intended to fall within the scope of the invention.

Claims

claims

1. A semiconductor device, including:

semiconductor substrate;

Well regions in semiconductor substrates;

Contact area in well area;

A sandwich structure located on the well region, the sandwich structure including a back gate metal, semiconductor fins located on both sides of the back gate metal, and respective back gate dielectrics respectively separating the back gate metal and the semiconductor fins, wherein the contact region and The well region serves as a part of the conductive path of the back gate metal, and the back gate metal is connected to the well region via the contact region;

a front gate stack intersecting the semiconductor fins, the front gate stack including a front gate dielectric and a front gate conductor, and the front gate dielectric separating the front gate conductor and the semiconductor fin;

an insulating cap located over the back gate metal and over the semiconductor fins, and isolating the back gate metal from the front gate conductor; and

Source and drain regions connected to the channel region provided by the semiconductor fin.

2. The semiconductor device according to claim 1, further comprising a punch-through blocking layer located under the semiconductor fin.

3. The semiconductor device according to claim 2, wherein the semiconductor device is N-type, and the punch-through stopper layer, the well region and the contact region are P-type.

4. The semiconductor device according to claim 2, wherein the semiconductor device is N-type, the punch-through stopper layer and the well region are P-type, and the contact region is N-type.

5. The semiconductor device according to claim 2, wherein the semiconductor device is P-type, and the punch-through stopper layer, the well region and the contact region are N-type.

6. The semiconductor device according to claim 2, wherein the semiconductor device is P-type, the well region and the contact region are N-type, and the contact region is P-type.

7. The semiconductor device according to claim 1, the contact region is a doped region with a doping concentration of 1 × 10 ¹⁸ cm" ³ -1 × 10 ²¹ cm ^-3 .

8. The semiconductor device according to claim 1, wherein the back gate metal is selected from the group consisting of TaC, TiN, TaTbN, TaErN, TaYN, TaSiN, HfSiN, MoSiN, RuTax, NiTax, MoNx, At least one composition of TiSiN, TiCN, TaAlC, TiAlN, TaN, RSix, Ni ₃ Si, Pt, Ru, Ir, Mo, W, HfRu, and RuOx.

9. A method of manufacturing a semiconductor device, including:

Forming a well region in the semiconductor substrate such that the portion of the semiconductor substrate located above the well region forms a semiconductor layer;

forming a plurality of mask layers on the semiconductor layer;

forming an opening in a topmost one of the plurality of mask layers;

Another mask layer in the form of side walls is formed on the inner wall of the opening;

Using the other mask layer as a hard mask, extend an opening through the plurality of mask layers and the semiconductor layer to the well region;

forming a contact region in the well region via the opening;

Form a back gate dielectric on the inner wall of the opening;

forming back gate metal in the opening;

forming an insulating cap in the opening, the insulating cap including the other mask layer and covering the back gate dielectric and the back gate metal;

Using an insulating cap as a hard mask, the semiconductor layer is patterned into semiconductor fins;

forming a front gate stack intersecting the semiconductor fin, the front gate stack including a front gate dielectric and a front gate conductor, and the front gate dielectric separating the front gate conductor and the semiconductor fin; and

10. The semiconductor device according to claim 9, further comprising forming a punch-through blocking layer under the semiconductor fin between the steps of patterning the semiconductor layer and forming the front gate stack.

11. The method of claim 10, wherein forming the punch-through blocking layer includes performing ion implantation to introduce a dopant into a portion of the semiconductor fin adjacent to the well region.

12. The method of claim 11, wherein forming the punch-through blocking layer includes forming an insulating layer to define the position of the punch-through blocking layer before performing ion implantation.

13. The method of claim 11, wherein the semiconductor device is N-type, and a P-type dopant is used in the step of forming the well region, and a P-type dopant is used in the step of forming the punch-through stopper layer , and using a P-type dopant in the step of forming the contact region.

14. The method of claim 11, wherein the semiconductor device is N-type, and A P-type dopant is used in the step of forming the well region, a P-type dopant is used in the step of forming the punch-through stopper layer, and an N-type dopant is used in the step of forming the contact region.

15. The method of claim 11, wherein the semiconductor device is P-type, and an N-type dopant is used in the step of forming the well region, and an N-type dopant is used in the step of forming the punch-through stopper layer. , and using an N-type dopant in the step of forming the contact region.

16. The method of claim 1, wherein the semiconductor device is P-type, and an N-type dopant is used in the step of forming the well region, and an N-type dopant is used in the step of forming the punch-through stopper layer , and using a P-type dopant in the step of forming the contact region.

17. The method according to claim 9, wherein the contact region is a doped region with a doping concentration of 1 × 10 ¹⁸ cm_ ³ - 1 × 10 ²¹ cm- ³ .

18. The method of claim 9, wherein the back gate metal is selected from the group consisting of TaC, TiN, TaTbN, TaErN, TaYN, TaSiN, HfSiN, MoSiN, RuTax, NiTax, MoNx, TiSiN, TiCN, TaAlC, TiAlN , TaN, RSix, Ni ₃ Si, Pt, Ru, Ir, Mo, W, Hfu, RuOx.