CN105304715A - Finfet and manufacturing method thereof - Google Patents

Finfet and manufacturing method thereof Download PDF

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Publication number
CN105304715A
CN105304715A CN201510612319.4A CN201510612319A CN105304715A CN 105304715 A CN105304715 A CN 105304715A CN 201510612319 A CN201510612319 A CN 201510612319A CN 105304715 A CN105304715 A CN 105304715A
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layer
semiconductor
semiconductor device
fin structure
break
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CN105304715B (en
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朱慧珑
许淼
梁擎擎
尹海洲
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7856—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with an non-uniform gate, e.g. varying doping structure, shape or composition on different sides of the fin, or different gate insulator thickness or composition on opposing fin sides

Abstract

The invention discloses a semiconductor device. The semiconductor device comprises a semiconductor substrate; a semiconductor fin structure which is formed on the semiconductor substrate; and a punch-through-stopper layer which is formed at the position of being away from the top surface of the fin structure for a certain distance in the fin structure. A doping concentration interface is arranged between the parts, which are arranged above the punch-through-stopper layer, of the punch-through-stopper layer and the fin structure.

Description

FinFET and manufacture method thereof
The application is the divisional application being entitled as the application for a patent for invention No.201210507134.3 of " FinFET and manufacture method thereof " submitted to Patent Office of the People's Republic of China on November 30th, 2012.
Technical field
The present invention relates to semiconductor technology, more specifically, relate to FinFET and preparation method thereof.
Background technology
Along with the size of semiconductor device is more and more less, short-channel effect is further obvious.In order to suppress short-channel effect, propose the FinFET formed in SOI wafer or bulk semiconductor substrate.FinFET is included in the middle channel region formed of the fin (fin) of semi-conducting material, and the source/drain region formed at fin two ends.Gate electrode in encirclement channel region, two sides (i.e. double-gate structure) of channel region, thus forms inversion layer on each side of raceway groove.Because whole channel region can be subject to the control of grid, therefore, it is possible to play the effect suppressing short-channel effect.
In batch production, compared with use SOI wafer, the FinFET cost efficiency using Semiconductor substrate to manufacture is higher, thus extensively adopts.But, in the FinFET using Semiconductor substrate, be difficult to the height controlling semiconductor fin, and the conductive path via Semiconductor substrate may be formed between source region and drain region, thus produce the problem of leakage current.
Below semiconductor fin, form doping break-through trapping layer (punch-through-stopperlayer), the leakage current between source region and drain region can be reduced.But the ion implantation performed to form break-through trapping layer may introduce less desirable dopant in the channel region of semiconductor fin.This additional doping makes to there is random doping fluctuation of concentration in the channel region of FinFET.
Due to height change and the random doping fluctuation of concentration of semiconductor fin, there is change at random in the threshold voltage of FinFET undesirably.
Summary of the invention
The object of the invention is the leakage current reduced in the FinFET of based semiconductor substrate between source region and drain region, and reduce the change at random of threshold voltage.
According to an aspect of the present invention, a kind of semiconductor device is provided, comprises: Semiconductor substrate; The semiconductor fin structure formed on a semiconductor substrate; And at the break-through trapping layer that the end face certain distance of fin structure middle distance fin structure is formed, wherein, between break-through trapping layer and the part of fin structure on break-through trapping layer, there is doping content interface.
In FinFET of the present invention, adopt doping break-through trapping layer semiconductor fin and Semiconductor substrate to be separated, thus the drain current path via Semiconductor substrate between source region and drain region can be disconnected.In the process forming this FinFET, the less desirable doping that top protective layer and/or side wall protective layer are avoided semiconductor fin can be adopted, thus the change at random of threshold voltage can be reduced.In a preferred embodiment, the source region formed in effect of stress layer and drain region can apply suitable stress to provide the mobility of charge carrier to the channel region in semiconductor fin.In another or further preferred embodiment, after adopting, grid technique formation grid are stacking, thus obtain the work function of high-quality gate-dielectric and expectation.
Accompanying drawing explanation
By referring to the description of accompanying drawing to the embodiment of the present invention, above-mentioned and other objects of the present invention, feature and advantage will be more clear, in the accompanying drawings:
Fig. 1-11 shows the schematic diagram of the semiconductor structure in each stage of the method for the manufacture semiconductor device according to the first embodiment of the present invention.
Figure 12-13 shows the schematic diagram of the semiconductor structure in a part of stage of the method for manufacture semiconductor device according to a second embodiment of the present invention.
Figure 14-16 shows the schematic diagram of the semiconductor structure in a part of stage of the method for manufacture semiconductor device according to the third embodiment of the invention.
Figure 17-20 shows the schematic diagram of the semiconductor structure in a part of stage of the method for manufacture semiconductor device according to a fourth embodiment of the invention.
Figure 21-22 shows the schematic diagram of the semiconductor structure in a part of stage of the method for manufacture semiconductor device according to a fifth embodiment of the invention.
Figure 23 shows the schematic diagram of the semiconductor structure in a part of stage of the method for manufacture semiconductor device according to a sixth embodiment of the invention.
Embodiment
In more detail the present invention is described hereinafter with reference to accompanying drawing.In various figures, identical element adopts similar Reference numeral to represent.For the sake of clarity, the various piece in accompanying drawing is not drawn in proportion.
For brevity, in a width figure, the semiconductor structure obtained after several step can be described.
Be to be understood that, when the structure of outlines device, when one deck, region are called be positioned at another layer, another region " above " or " top " time, can refer to be located immediately at another layer, another over, or itself and another layer, also comprise other layer or region between another region.Further, if overturn by device, this one deck, a region will be positioned at another layer, another region " below " or " below ".
If in order to describe the situation being located immediately at another layer, another over, will adopt herein " directly exist ... above " or " ... above and adjoin with it " form of presentation.
In this application, term " semiconductor structure " refers to, in the general designation manufacturing the whole semiconductor structure formed in each step of semiconductor device, comprise all layers or region that have been formed.Describe hereinafter many specific details of the present invention, the structure of such as device, material, size, treatment process and technology, more clearly to understand the present invention.But just as the skilled person will understand like that, the present invention can be realized not in accordance with these specific details.
Unless particularly pointed out hereinafter, the various piece of FinFET can be made up of the known material of those skilled in the art.Semi-conducting material such as comprises Group III-V semiconductor, as GaAs, InP, GaN, SiC, and IV race semiconductor, as Si, Ge.Grid conductor can be formed by the various materials that can conduct electricity, such as metal level, doped polysilicon layer or comprise stacked gate conductor or other electric conducting materials of metal level and doped polysilicon layer, be such as TaC, TiN, TaTbN, TaErN, TaYbN, TaSiN, HfSiN, MoSiN, RuTax, NiTax, MoNx, TiSiN, TiCN, TaAlC, TiAlN, TaN, PtSix, Ni 3the combination of Si, Pt, Ru, Ir, Mo, HfRu, RuOx and described various electric conducting material.Gate-dielectric can by SiO 2or dielectric constant is greater than SiO 2material form, such as comprise oxide, nitride, oxynitride, silicate, aluminate, titanate, wherein, oxide such as comprises SiO 2, HfO 2, ZrO 2, A1 2o 3, TiO 2, La 2o 3, nitride such as comprises Si 3n 4, silicate such as comprises HfSiOx, and aluminate such as comprises LaAlO 3, titanate such as comprises SrTiO 3, oxynitride such as comprises SiON.Further, gate-dielectric not only can be formed by the known material of those skilled in the art, also can adopt the material for gate-dielectric of exploitation in the future.
The present invention can present in a variety of manners, below will describe some of them example.
With reference to Fig. 1-11, the example flow according to the method for the manufacture semiconductor device of the first embodiment of the present invention is described, wherein, the vertical view of semiconductor structure and the interception position of sectional view have been shown in Figure 10 a-11a, the sectional view of the semiconductor structure intercepted at the Width ascender line A-A of semiconductor fin shown in Fig. 1-9,10b-11b, the sectional view of the semiconductor structure intercepted at the A length direction ascender line B-B of semiconductor fin shown in Figure 10 c-11c.
As shown in Figure 1; by known depositing operation; as electron beam evaporation (EBM), chemical vapour deposition (CVD) (CVD), ald (ALD), sputtering etc.; in Semiconductor substrate 101 (such as Si substrate) upper formation top protective layer 102 (such as, silicon nitride).In one example, top protective layer 102 is such as the silicon nitride layer that thickness is about 50-100nm.Just as will be described, will semiconductor fin be formed in Semiconductor substrate 101.
Then; such as form photoresist oxidant layer PR1 by being spin-coated on top protective layer 102; and by photoresist oxidant layer PR1 being formed comprising the photoetching process of exposure and development the pattern being used for the shape (such as, band) limiting semiconductor fin.
Adopt photoresist oxidant layer PR1 as mask; pass through dry etching; as ion beam milling etching, plasma etching, reactive ion etching, laser ablation; or by using the wet etching of etchant solutions; remove the expose portion of top protective layer 102; and etching semiconductor substrate 101 is to the predetermined degree of depth further, as shown in Figure 2.By controlling the time of etching, the etch depth in Semiconductor substrate 101 can be controlled, thus form opening in Semiconductor substrate 101, and limit ridge between opening.Top protective layer 102 is positioned on the top surface of ridge.
Then, by dissolving in a solvent or ashing removal photoresist oxidant layer PR1.By above-mentioned known depositing operation, the surface of semiconductor structure forms the first insulating barrier 103 (such as, silica), with the opening in filling semiconductor substrate 101.In one example, suitable depositing operation (such as high density plasma CVD HDP-CVD) is adopted to make the thickness of the part of the first insulating barrier 103 in opening be greater than the thickness that the first insulating barrier 103 is positioned at the part on top protective layer 102.In another example; first insulating barrier 103 is positioned at the thickness of the part on top protective layer 102 may be too large; can by the surface of additional chemico-mechanical polishing (CMP) smooth semiconductor structure; thus reduce the thickness of this part, or remove this part completely using top protective layer 102 as stop-layer.
Adopt top protective layer 102 as hard mask, by optionally etch process (such as, reactive ion etching), etch-back first insulating barrier 103, as shown in Figure 3.This etching is not only removed the first insulating barrier 103 and is positioned at part on top protective layer 102, and reduces the thickness that the first insulating barrier 103 is positioned at the part of opening.Control the time of etching, the part making the first insulating barrier 103 be positioned at opening is used as separator, and limits the degree of depth of opening.This opening exposes the side on the top of ridge, and the degree of depth of opening should be substantially equal to the height of the semiconductor fin that will be formed.
Then, by above-mentioned known depositing operation, the surface of semiconductor structure forms conformal nitride layer (such as, silicon nitride).In one example, the thickness of this nitride layer is about 10-20nm.
By anisotropic etch process (such as; reactive ion etching); remove the part of nitride layer horizontal expansion on the exposed surface of the first insulating barrier 103; the vertical component that nitride layer is positioned on the side of ridge retains; thus form side wall protective layer 104, as shown in Figure 4.As a result, the top of ridge is coated with top protective layer 102, and the side on the top of ridge is coated with side wall protective layer 104, and side and first insulating barrier 103 of the bottom of ridge adjoin.
Then, adopt top protective layer 102 and side wall protective layer 104 as hard mask, by optionally etch process (such as, reactive ion etching), etch-back first insulating barrier 103, as shown in Figure 5.This etching reduces the thickness of the first insulating barrier 103, and exposes a part for the side of the bottom of ridge.Control the time of etching, make the height h of the exposed side of the bottom of ridge (i.e. the decrease of the thickness of the first insulating barrier 103) be predetermined value.
Then, conformal doping (conformaldoping) is adopted to form conformal dopant layer 105 on the surface of a semiconductor substrate, as shown in Figure 6.Dopant layer 105 comprises the superficial layer comprising dopant in the exposed side of top protective layer 102, the surface of side wall protective layer 104, first insulating barrier 103 and the bottom of ridge.
Different dopants can be adopted for dissimilar FinFET.Can P-type dopant be used in N-type FinFET, such as B, N-type dopant can be used in P type FinFET, such as P, As.Dopant layer 105 for the formation of doping break-through trapping layer, will make the doping type of break-through trapping layer contrary with the doping type in source region and drain region, thus can disconnect the drain current path between source region and drain region.
Then, by above-mentioned known depositing operation, the surface of semiconductor structure forms the second insulating barrier 106 (such as, silica).Adopt top protective layer 102 and side wall protective layer 104 as hard mask, by optionally etch process (such as, reactive ion etching), etch-back second insulating barrier 106, as shown in Figure 7.This etching reduces the thickness of the second insulating barrier 106.Control the time of etching, make the top surface of the second insulating barrier 106 at least higher than the bottom of side wall protective layer 104, thus the second insulating barrier 106 at least covers dopant layer 105 is positioned at part on the side of ridge.
Then, by optionally etch process (such as, reactive ion etching), relative to the second insulating barrier 106, remove top protective layer 102 and side wall protective layer 104, as shown in Figure 8.This etching also eliminates dopant layer 105 and is positioned at part on the surface of top protective layer 102 and side wall protective layer 104.
Then, adopt thermal annealing, part dopant layer 105 be positioned on the side of ridge inwardly pushes until be communicated with, thus in the ridge of Semiconductor substrate 101, form doping break-through trapping layer 107, as shown in Figure 9.The part that this ridge is positioned on doping break-through trapping layer 107 forms semiconductor fin 108.Further, separated by the break-through trapping layer 107 that adulterates between semiconductor fin 108 and Semiconductor substrate 101.Due on the Width of ridge, the dopant that thermal annealing pushes spreads in the middle of two side direction, therefore the break-through trapping layer 107 that adulterates also exists the doping concentration distribution of the Width along semiconductor fin, makes the doping content of doping break-through trapping layer 107 mid portion be less than the doping content of two end portions.
Then, by above-mentioned known depositing operation, the surface of semiconductor structure forms gate-dielectric 109 (such as, silica or silicon nitride).In one example, this gate-dielectric 109 is the silicon oxide layer that about 0.8-1.5nm is thick.Gate-dielectric 109 covers top surface and the side of semiconductor fin 108.
By above-mentioned known depositing operation, the surface of semiconductor structure forms conductor layer (such as, doped polycrystalline silicon).If needed, chemico-mechanical polishing (CMP) can be carried out, to obtain even curface to conductor layer.
Adopt photoresist mask, this conductor layer is patterned as the grid conductor 110 across semiconductor fin, and remove the expose portion of gate-dielectric 109 further, as shown in Figure 10 a, 10b and 10c.It is stacking that grid conductor 110 forms grid together with gate-dielectric 109.In the example shown in Figure 10 a, 10b and 10c, the shape of grid conductor 110 is band, and extends along the direction vertical with the length of semiconductor fin.
Then, by above-mentioned known depositing operation, the surface of semiconductor structure forms nitride layer.In one example, this nitride layer is the silicon nitride layer that thickness is about 5-20nm.By anisotropic etch process (such as, reactive ion etching), remove the part of the horizontal expansion of nitride layer, the vertical component that nitride layer is positioned on the side of grid conductor 110 retains, thus forms grid curb wall 111.Usually, due to form factor, the nitride layer thickness on semiconductor fin 108 side is less than the nitride layer thickness on the side of grid conductor 110, thus can remove the nitride layer on semiconductor fin 108 side in this etching step completely.Otherwise the nitride layer thickness on semiconductor fin 108 side is too large may hinder formation grid curb wall.Additional mask can be adopted to remove nitride layer on semiconductor fin 108 side further.
This etch exposed semiconductor fin 108 is positioned at top surface and the side of the part of grid conductor 110 both sides.Then, technique conveniently source region and drain region can be formed in the expose portion of semiconductor fin 103.
The example flow in a part of stage of the method for manufacture semiconductor device is according to a second embodiment of the present invention described, the sectional view of the semiconductor structure intercepted on the Width of semiconductor fin shown in it with reference to Figure 12-13.
According to the second embodiment, after the step shown in Fig. 5, perform following steps.
Pushed (gasphasedrive-in) by gas phase, dopant is internally spread until be communicated with from the exposed side of the bottom of ridge, thus in the ridge of Semiconductor substrate 101, form doping break-through trapping layer 107, as shown in figure 12.The part that this ridge is positioned on doping break-through trapping layer 107 forms semiconductor fin 108.Further, separated by the break-through trapping layer 107 that adulterates between semiconductor fin 108 and Semiconductor substrate 101.Due on the Width of ridge, the dopant that gas phase pushes spreads in the middle of two side direction, therefore, doping break-through trapping layer 107 also exists the doping concentration distribution of the Width along semiconductor fin, makes the doping content of doping break-through trapping layer 107 mid portion be less than the doping content of two end portions.
In gas phase pushes, different dopants can be adopted for dissimilar FinFET.Can P-type dopant be used in N-type FinFET, such as B, N-type dopant can be used in P type FinFET, such as P, As.The doping type of doping break-through trapping layer 107 is contrary with the doping type in source region and drain region, thus can disconnect the drain current path between source region and drain region.
Then, by above-mentioned known depositing operation, the surface of semiconductor structure forms the second insulating barrier 106 (such as, silica).Adopt top protective layer 102 and side wall protective layer 104 as hard mask, by optionally etch process (such as, reactive ion etching), etch-back second insulating barrier 106.This etching reduces the thickness of the second insulating barrier 106.Control the time of etching, make the top surface of the second insulating barrier 106 at least higher than the interface between doping break-through trapping layer 107 and Semiconductor substrate 101.
Then, by optionally etch process (such as, reactive ion etching), relative to the second insulating barrier 106, remove top protective layer 102 and side wall protective layer 104, as shown in figure 13.
Then, continue the step shown in Figure 10 and 11 grid be stacking to be formed, grid curb wall, source region and drain region.
The example flow in a part of stage of the method for manufacture semiconductor device is according to the third embodiment of the invention described, the sectional view of the semiconductor structure intercepted on the Width of semiconductor fin shown in it with reference to Figure 14-16.
According to the 3rd embodiment, after the step shown in Fig. 5, perform following steps.
Then, adopt top protective layer 102 and side wall protective layer 104 as hard mask, injected by angle-tilt ion, in the exposed side of the bottom of ridge, form dopant layer 105, as shown in figure 14.Control the parameter of ion implantation, dopant is not entered in other parts of ridge through top protective layer 102 and side wall protective layer 104.In fig. 14 ion implantation being described as in two directions (as shown by arrows) carries out.Should be appreciated that this ion implantation can comprise and carry out ion implantation along first direction in a first step, carry out ion implantation along second direction in the second step.
In ion implantation, different dopants can be adopted for dissimilar FinFET.Can P-type dopant be used in N-type FinFET, such as B, N-type dopant can be used in P type FinFET, such as P, As.Dopant layer 105 for the formation of doping break-through trapping layer, will make the doping type of break-through trapping layer contrary with the doping type in source region and drain region, thus can disconnect the drain current path between source region and drain region.
Then, by above-mentioned known depositing operation, the surface of semiconductor structure forms the second insulating barrier 106 (such as, silica).Adopt top protective layer 102 and side wall protective layer 104 as hard mask, by optionally etch process (such as, reactive ion etching), etch-back second insulating barrier 106, as shown in figure 15.This etching reduces the thickness of the second insulating barrier 106.Control the time of etching, make the top surface of the second insulating barrier 106 at least higher than the bottom of side wall protective layer 104, thus the second insulating barrier 106 at least covers dopant layer 105.
Then, by optionally etch process (such as, reactive ion etching), relative to the second insulating barrier 106, remove top protective layer 102 and side wall protective layer 104.Adopt thermal annealing, part dopant layer 105 be positioned on the side of ridge inwardly pushes until be communicated with, thus in the ridge of Semiconductor substrate 101, form doping break-through trapping layer 107, as shown in figure 16.The part that this ridge is positioned on doping break-through trapping layer 107 forms semiconductor fin 108.Further, separated by the break-through trapping layer 107 that adulterates between semiconductor fin 108 and Semiconductor substrate 101.Due on the Width of ridge, the dopant that gas phase pushes spreads in the middle of two side direction, therefore the break-through trapping layer 107 that adulterates also exists the doping concentration distribution of the Width along semiconductor fin, makes the doping content of doping break-through trapping layer 107 mid portion be less than the doping content of two end portions.
Then, continue the step shown in Figure 10 and 11 grid be stacking to be formed, grid curb wall, source region and drain region.
The example flow in a part of stage of the method for manufacture semiconductor device is according to a fourth embodiment of the invention described, the sectional view of the semiconductor structure intercepted on the Width of semiconductor fin shown in it with reference to Figure 17-20.
As shown in figure 17, form doped region by the desired depth of ion implantation in Semiconductor substrate 101 (such as Si substrate), thus form doping break-through trapping layer 107.The part that Semiconductor substrate 101 is positioned on doping break-through trapping layer 107 will form semiconductor layer 108 '.Further, separated by the break-through trapping layer 107 that adulterates between semiconductor layer 108 ' and Semiconductor substrate 101.Doping break-through trapping layer 107 also exists the doping concentration distribution of the Width along semiconductor fin, makes the doping content of doping break-through trapping layer 107 mid portion be less than the doping content of two end portions.
In ion implantation, different dopants can be adopted for dissimilar FinFET.Can P-type dopant be used in N-type FinFET, such as B, N-type dopant can be used in P type FinFET, such as P, As.The doping type of doping break-through trapping layer 107 is contrary with the doping type in source region and drain region, thus can disconnect the drain current path between source region and drain region.
By above-mentioned known depositing operation, at semiconductor layer 108 ' upper formation top protective layer 102 (such as, silicon nitride), as shown in figure 17.
Then; such as form photoresist oxidant layer PR1 by being spin-coated on top protective layer 102; and by photoresist oxidant layer PR1 being formed comprising the photoetching process of exposure and development the pattern being used for the shape (such as, band) limiting semiconductor fin.
Adopt photoresist oxidant layer PR1 as mask; pass through dry etching; as ion beam milling etching, plasma etching, reactive ion etching, laser ablation; or by using the wet etching of etchant solutions; remove the expose portion of top protective layer 102, semiconductor layer 108 ', doping break-through trapping layer 107 from top to bottom; and can further etching semiconductor substrate 101 to the predetermined degree of depth, as shown in figure 18.By controlling the time of etching, the etch depth in Semiconductor substrate 101 can be controlled, thus form opening in Semiconductor substrate 101.The part of semiconductor layer 108 ' between opening retains to form semiconductor fin 108.Top protective layer 102 is positioned on the surface of semiconductor fin 108.
Then, by dissolving in a solvent or ashing removal photoresist oxidant layer PR1.By above-mentioned known depositing operation, the surface of semiconductor structure forms the first insulating barrier 103 (such as, silica), with the opening in filling semiconductor substrate 101.In one example, suitable depositing operation (such as high density plasma CVD HDP-CVD) is adopted to make the thickness of the part of the first insulating barrier 103 in opening be greater than the thickness that the first insulating barrier 103 is positioned at the part on top protective layer 102.In another example; first insulating barrier 103 is positioned at the thickness of the part on top protective layer 102 may be too large; can by the surface of additional chemico-mechanical polishing (CMP) smooth semiconductor structure; thus reduce the thickness of this part, or remove this part completely using top protective layer 102 as stop-layer.
Adopt top protective layer 102 as hard mask, by optionally etch process (such as, reactive ion etching), etch-back first insulating barrier 103.This etching reduces the thickness of the first insulating barrier 103.Control the time of etching, make the top surface of the first insulating barrier 103 at least higher than the interface between doping break-through trapping layer 107 and Semiconductor substrate 101.
Then, by optionally etch process (such as, reactive ion etching), relative to the first insulating barrier 103, remove top protective layer 102, as shown in figure 20.
Then, continue the step shown in Figure 10 and 11 grid be stacking to be formed, grid curb wall, source region and drain region.It should be noted that and do not need in this embodiment to form side wall protective layer 104 and the second insulating barrier 106.
The example flow in a part of stage of the method for manufacture semiconductor device is according to a fifth embodiment of the invention described with reference to Figure 21-22, wherein, the vertical view of semiconductor structure and the interception position of sectional view have been shown in Figure 21 a-22a, the sectional view of the semiconductor structure intercepted at the Width ascender line A-A of semiconductor fin shown in Figure 21 b-22b, the sectional view of the semiconductor structure intercepted at the A length direction ascender line B-B of semiconductor fin shown in Figure 21 c-22c.
According to the preferred embodiment, after the step shown in Figure 11, perform the step shown in Figure 21 and 22 further to form effect of stress layer, and form source region and drain region in effect of stress layer.
By above-mentioned known etch process (such as, reactive ion etching), optionally remove the part that semiconductor fin 108 is positioned at grid conductor 110 both sides, as shown in Figure 21 a, 21b and 21c relative to grid curb wall 111.This etching can stop at the top surface of doping break-through trapping layer 107, or removes a part (as shown in Figure 21 c) for doping break-through trapping layer 107 further.This etching also may remove a part for grid conductor 110.Because the thickness of grid conductor 110 can be more much larger than the height of semiconductor fin 108, therefore, this etching only only reduces the thickness of grid conductor 110, and does not remove grid conductor 110 (as shown in Figure 21 c) completely.
Then, by above-mentioned known depositing operation, at doping break-through trapping layer 107 Epitaxial growth effect of stress layer 112, as shown in Figure 22 a, 22b and 22c.Effect of stress layer 112 is also formed on grid conductor 110.The thickness of this effect of stress layer 112 should be enough large, makes the top surface of effect of stress layer 112 greater than or equal to the top surface of semiconductor fin 108, to maximize the stress applied in semiconductor fin 108.
Different effect of stress layers 112 can be formed for dissimilar FinFET.Apply suitable stress by effect of stress layer to the channel region of FinFET, the mobility of charge carrier can be improved, thus reduce conducting resistance and improve the switching speed of device.For this reason, adopt the semi-conducting material different from the material of semiconductor fin 108 to form source region and drain region, the stress of expectation can be produced.For N-type FinFET, effect of stress layer 112 is such as the Si:C layer that the content of the C formed on a si substrate is about atomic percent 0.2-2%, and the longitudinal direction along channel region applies tension stress to channel region.For P type FinFET, effect of stress layer 112 is such as the SiGe layer that the content of the Ge formed on a si substrate is about atomic percent 15-75%, and the longitudinal direction along channel region applies compression to channel region.
The example flow in a part of stage of the method for manufacture semiconductor device is according to a sixth embodiment of the invention described with reference to Figure 23, wherein, the vertical view of semiconductor structure and the interception position of sectional view have been shown in Figure 23 a, the sectional view of the semiconductor structure intercepted at the Width ascender line A-A of semiconductor fin shown in Figure 23 b, the sectional view of the semiconductor structure intercepted at the A length direction ascender line B-B of semiconductor fin shown in Figure 23 c.
According to the preferred embodiment, after the step shown in Figure 22, perform the step shown in Figure 23 further stacking to form the alternative gate comprising replacement gate conductor and alternative gate medium.
By above-mentioned known depositing operation, the surface of semiconductor structure forms the 3rd insulating barrier 113 (such as, silica).Chemico-mechanical polishing is carried out to semiconductor structure, to obtain even curface.This chemico-mechanical polishing eliminates the 3rd insulating barrier 113 and is positioned at a part above grid conductor 110, thus the effect of stress layer 112 exposed above grid conductor 110 and grid curb wall 111.Further, this chemico-mechanical polishing can remove a part for effect of stress layer 112 and grid curb wall 111.
Adopt the 3rd insulating barrier 113 and grid curb wall 111 as hard mask, the effect of stress layer 112 above grid conductor 110 is removed by above-mentioned known etch process (such as reactive ion etching), and remove grid conductor 110 further, thus form gate openings.Alternatively, gate-dielectric 107 can be removed further and be positioned at part bottom gate openings.According to rear grid technique, in gate openings, form replacement gate dielectric 114 (such as, HfO 2) and replacement gate conductor 115 (such as, TiN), as shown in Figure 23 a, 23b and 23c.It is stacking that replacement gate conductor 115 forms alternative gate together with replacement gate dielectric 114.
According to each above-mentioned embodiment, after formation source region and drain region, interlayer insulating film can be formed on obtained semiconductor structure, be arranged in the through hole of interlayer insulating film, the wiring being positioned at interlayer insulating film upper surface or electrode, thus complete other parts of FinFET.
In the above description, the ins and outs such as composition, etching for each layer are not described in detail.But it will be appreciated by those skilled in the art that and by various technological means, the layer of required form, region etc. can be formed.In addition, in order to form same structure, those skilled in the art can also design the not identical method with method described above.In addition, although respectively describing each embodiment above, this is not also meaning that the measure in each embodiment can not advantageously be combined.
Above embodiments of the invention are described.But these embodiments are only used to the object illustrated, and are not intended to limit the scope of the invention.Scope of the present invention is by claims and equivalents thereof.Do not depart from the scope of the present invention, those skilled in the art can make multiple substituting and amendment, and these substitute and amendment all should fall within the scope of the present invention.

Claims (10)

1. a semiconductor device, comprising:
Semiconductor substrate;
The semiconductor fin structure formed on a semiconductor substrate; And
At the break-through trapping layer that the end face certain distance of fin structure middle distance fin structure is formed, wherein, between break-through trapping layer and the part of fin structure on break-through trapping layer, there is doping content interface.
2. semiconductor device according to claim 1, also comprises:
The dopant layer that fin structure sidewall is formed, wherein, the end face of dopant layer is lower than the end face of fin structure, and the position of break-through trapping layer corresponds to the position of dopant layer.
3. semiconductor device according to claim 1 and 2, wherein, break-through trapping layer has doping concentration distribution along the Width of fin structure, makes the doping content of doping content lower than two end portions of break-through trapping layer mid portion.
4. semiconductor device according to claim 1, wherein, fin structure and Semiconductor substrate one.
5. semiconductor device according to claim 2, also comprises:
Formed on a semiconductor substrate and end face lower than the separator of the end face of semiconductor fin structure, wherein, dopant layer is on separator.
6. semiconductor device according to claim 2, wherein, dopant layer is included in the part that the side of fin structure extends and the part extended in the lateral surfaces of Semiconductor substrate.
7. semiconductor device according to claim 6, also comprises: the separator in described dopant layer.
8. the semiconductor device according to claim 5 or 7, also comprises:
The grid across fin structure that separator is formed are stacking, and these grid are stacking comprises gate dielectric layer and grid conductor layer;
At the source-drain area that the semiconductor fin structure being arranged in the stacking both sides of grid is formed.
9. semiconductor device according to claim 2, wherein,
Described semiconductor device is N-type device, and described dopant layer comprises P-type dopant; Or
Described semiconductor device is P type device, and described dopant layer comprises N-type dopant.
10. semiconductor device according to claim 9, wherein, described P-type dopant comprises B, and described N-type dopant comprises P or As.
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