CN112259449B - N-type work function layer of NMOS (N-channel metal oxide semiconductor) device, forming method thereof and MOSFET (metal oxide semiconductor field effect transistor) structure - Google Patents

N-type work function layer of NMOS (N-channel metal oxide semiconductor) device, forming method thereof and MOSFET (metal oxide semiconductor field effect transistor) structure Download PDF

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CN112259449B
CN112259449B CN202011084286.8A CN202011084286A CN112259449B CN 112259449 B CN112259449 B CN 112259449B CN 202011084286 A CN202011084286 A CN 202011084286A CN 112259449 B CN112259449 B CN 112259449B
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layer
temperature
tial
work function
nmos
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CN112259449A (en
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鲍宇
徐建华
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Shanghai Huali Integrated Circuit Manufacturing Co Ltd
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by physical means, e.g. sputtering, evaporation
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28088—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a composite, e.g. TiN
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H—ELECTRICITY
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2

Abstract

The application provides a method for forming an N-type work function layer of an NMOS device, which relates to the manufacturing technology of a semiconductor integrated circuit, and aims at the PVD process of the N-type work function layer of the NMOS, a groove of the NMOS for forming a metal grid is formed firstly, then a thin TiAl layer is deposited by adopting a low-temperature PVD process and used as a buffer layer to reduce aluminum diffusion caused by high temperature, then high-temperature annealing is carried out, then a TiAl main body layer is deposited by adopting a high-temperature PVD process, the mobility of deposited TiAl particles on the surface of a substrate can be enhanced at higher temperature, a backflow phenomenon is generated, the overlap of PVD is reduced, a process window of subsequent metal grid filling is improved, namely two-step PVD deposition is adopted, and the inhibition and buffering capacity of low-temperature TiAl diffusion and the overlap of high-temperature TiAl are taken into consideration to improve the filling effect.

Description

N-type work function layer of NMOS (N-channel metal oxide semiconductor) device, forming method thereof and MOSFET (metal oxide semiconductor field effect transistor) structure
Technical Field
The application relates to a semiconductor integrated circuit manufacturing technology, in particular to a method for forming an N-type work function layer of an NMOS device.
Background
With the development of semiconductor technology, a Metal Gate (MG) is generally used in a gate structure of a semiconductor device with a high process node, and a high dielectric constant layer (HK) is generally used in a gate dielectric layer, and the HK and the MG are stacked to form an HKMG structure. With the further reduction of the size of the semiconductor device, the semiconductor device adopts a fin transistor structure, the fin transistor comprises a fin body, the fin body is in a nano-strip or nano-sheet structure, and the fin body is formed by etching the semiconductor substrate. The gate structure covers the top surface and the side surfaces of the fin body with partial length. And the source region and the drain region are formed in the fin bodies on two sides of the grid structure. The gate structure of HKMG is typically implemented using a gate replacement process. Namely, the pseudo grid structure is formed in the forming area of the grid structure by deposition, photoetching and etching processes. The dummy gate structure is generally formed by overlapping a gate oxide layer and a polysilicon gate, then side walls are formed on the side faces of the dummy gate structure, and a source region and a drain region are formed on two sides of the dummy gate structure by adopting a source-drain ion implantation process. After all front-side processes before HKMG are completed, the dummy gate structure is removed, a groove is formed in the dummy gate structure removal region, and then the HKMG is formed in the groove. As the device size shrinks, the recess shrinks and the HKMG fill thickness is limited. Generally, in the HKMG, a work function layer is required, an N-type work function layer such as TiAl is used for an N-type semiconductor device, and a work function of the N-type work function layer is close to a conduction band of a semiconductor substrate such as a silicon substrate, which is advantageous for reducing a threshold voltage of the N-type semiconductor device; the P-type semiconductor device adopts a P-type work function layer such as TiN, the work function of the P-type work function layer is close to the valence band of a semiconductor substrate such as a silicon substrate, and the threshold voltage, namely the absolute value of the threshold voltage, of the P-type semiconductor device is favorably reduced. In general, it is necessary to integrate an N-type semiconductor device and a P-type semiconductor device simultaneously on the same semiconductor substrate. At this time, it is necessary to form the P-type work function layer first, then remove the P-type work function layer in the N-type semiconductor device formation region, and then form the N-type work function layer, at this time, the N-type work function layer in the P-type semiconductor device formation region is overlapped on the surface of the P-type work function layer, and then the metal gate is formed.
The work function layer TiAl of the existing N-type semiconductor device is generally formed by a physical Vapor deposition pvd (physical Vapor deposition) process. Because Al in TiAl has a certain diffusion capability, thermal budget (thermal budget) needs to be strictly controlled, and a low-temperature process is generally adopted, but the disadvantage is that low-temperature PVD generates a relatively obvious suspended film (overlap) and is not beneficial to subsequent metal gate filling.
Disclosure of Invention
The application provides a method for forming a high dielectric metal gate MOSFET structure, which comprises the following steps: s1: providing a semiconductor substrate, wherein the semiconductor substrate comprises an NMOS forming area and a PMOS forming area, the process before metal gate is finished on the semiconductor substrate by adopting a process method of a pseudo polysilicon gate, a polysilicon gate structure of NMOS is formed on the surface of the NMOS forming area of the semiconductor substrate, the polysilicon gate structure of PMOS is formed on the surface of the PMOS forming area of the semiconductor substrate, interlayer dielectric layers are filled among the polysilicon gate structures, each polysilicon gate structure comprises gate dielectric layers formed by an interface layer, a high dielectric constant layer and a bottom barrier layer which are sequentially overlapped, and a polysilicon gate is formed on the gate dielectric layers; s2: removing polysilicon gates to form a first work function layer, wherein the first work function layer covers the side surfaces and the bottom surfaces of the polysilicon gate removal regions and extends out of the polysilicon gate removal regions, part of the first work function layer is removed, the first work function layer in the polysilicon gate removal regions of the PMOS is reserved, and the first work function layer forms a P-type work function layer of the PMOS; s3: depositing a first TiAl layer by using a low-temperature PVD (physical vapor deposition) process; s4: carrying out a high-temperature annealing process; s5: depositing a second TiAl layer by a high-temperature PVD process, wherein the second TiAl layer forms a TiAl main body layer, and the first TiAl layer and the second TiAl layer which are subjected to a high-temperature annealing process form N-type work function layers of an NMOS region and a PMOS region; and S6: and forming a top blocking layer by overlapping the N-type work function layer of the NMOS, and forming a top blocking layer by overlapping the N-type work function layer of the PMOS to form a metal layer, wherein the polysilicon gate removing area is completely filled by the metal layer and is flattened to form a metal gate of the NMOS and a metal gate of the PMOS.
Furthermore, the temperature range of the low-temperature PVD process is 0-100 ℃.
Furthermore, the thickness of the first TiAl layer is 1 angstrom-10 m.
Furthermore, the temperature range of the high-temperature annealing process is 100-400 ℃.
Furthermore, the temperature range of the high-temperature PVD process is 200-400 ℃.
Furthermore, the thickness of the second TiAl layer is 10 angstrom-100 m.
Further, in the low-temperature PVD process, Ti: the Al atomic ratio is larger than that of Ti in the high-temperature PVD process: atomic ratio of Al.
Further, the temperature of the low temperature PVD process and the high temperature PVD process is fixed or graded.
The present application further provides a method for forming an N-type work function layer of an NMOS device, including: s1: providing a semiconductor substrate, wherein the semiconductor substrate comprises an NMOS forming area, the process before metal gate is finished on the semiconductor substrate by adopting a process method of a pseudo polysilicon gate, a polysilicon gate structure of the NMOS is formed on the surface of the NMOS forming area of the semiconductor substrate, and the polysilicon gate is removed to form a groove; s2: depositing a first TiAl layer on the bottom and the side wall of the groove by using a low-temperature PVD process; s3: carrying out a high-temperature annealing process; and S4: and depositing a second TiAl layer by using a high-temperature PVD (physical vapor deposition) process, wherein the second TiAl layer forms a TiAl main body layer, and the first TiAl layer and the second TiAl layer which are subjected to a high-temperature annealing process form N-type work function layers in NMOS (N-channel metal oxide semiconductor) and PMOS (P-channel metal oxide semiconductor) regions.
Furthermore, the temperature range of the low-temperature PVD process is 0-100 ℃, and the thickness of the first TiAl layer is 1 angstrom-10 m.
Further, the following steps: the temperature range of the high-temperature annealing process is 100-400 ℃.
Furthermore, the temperature range of the high-temperature PVD process is 200-400 ℃, and the thickness of the second TiAl layer is 10-100 meters.
Further, in the low-temperature PVD process, Ti: the Al atomic ratio is larger than that of Ti in the high-temperature PVD process: atomic ratio of Al.
The present application further provides an N-type work function layer of an NMOS device, comprising: the PVD device comprises a first TiAl layer and a second TiAl layer, wherein the first TiAl layer is formed at the bottom and the side wall of a groove for forming a metal gate, the second TiAl layer is formed on the first TiAl layer, the temperature of the PVD process for forming the first TiAl layer is lower than that of the PVD process for forming the second TiAl layer, the thickness of the first TiAl layer is smaller than that of the second TiAl layer, and Ti: and the Al atomic ratio is larger than that of Ti: atomic ratio of Al.
Furthermore, the thickness of the first TiAl layer is 1 to 10 meters, and the thickness of the second TiAl layer is 10 to 100 meters.
As described above, aiming at the PVD process of the N-type work function layer of the NMOS, firstly, a groove of the NMOS, which is used for forming the metal gate, is formed, then, a thin TiAl layer is deposited by adopting a low-temperature PVD process to be used as a buffer layer so as to reduce aluminum diffusion caused by high temperature, then, high-temperature annealing is carried out, then, a TiAl main body layer is deposited by adopting a high-temperature PVD process, the mobility of the deposited TiAl particles on the surface of a substrate can be enhanced by adopting higher temperature, a backflow phenomenon is generated, the overlap of PVD is reduced, the process window of subsequent metal gate filling is improved, namely, two-step PVD deposition is adopted, and the inhibition and buffering capacity of Al diffusion and the overlap with smaller high-temperature TiAl are taken into consideration so as to improve the filling effect.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1a to fig. 1e are schematic views illustrating a process of forming a high-k metal gate MOSFET structure according to an embodiment of the invention.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some, but not all, embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It should be understood that the terms "first", "second", etc. in the claims, description, and drawings of the present application are used for distinguishing between different objects and not for describing a particular order. The terms "comprises" and "comprising," when used in the specification and claims of this application, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
In an embodiment of the present invention, a method for forming a high-k metal gate MOSFET structure is further provided, referring to fig. 1a to 1e, where fig. 1a to 1e are schematic diagrams of a forming process of a high-k metal gate MOSFET structure according to an embodiment of the present invention, and the method for forming a high-k metal gate MOSFET structure includes:
s1: referring to fig. 1a, a semiconductor substrate 100 is provided, the semiconductor substrate 100 includes an NMOS forming region 101 and a PMOS forming region 102, a process before a metal gate is completed on the semiconductor substrate by using a dummy polysilicon gate process method, a polysilicon gate structure of an NMOS is formed on a surface of the NMOS forming region 101 of the semiconductor substrate 100, a polysilicon gate structure of a PMOS is formed on a surface of the PMOS forming region 102 of the semiconductor substrate 100, and an interlayer dielectric layer 230 is filled between the polysilicon gate structures, wherein each polysilicon gate structure includes a gate dielectric layer composed of an interface layer 211 or 221, a high-k layer 212 or 222, and a bottom barrier layer 213 or 223, which are sequentially stacked, and a polysilicon gate 310 or 320 formed on the gate dielectric layer;
in one embodiment, in general, a P well is formed in the NMOS formation region 101, and a polysilicon gate structure of an NMOS device is formed over the P well of a semiconductor substrate; an N-well is formed in the PMOS formation region 102, and a polysilicon gate structure of a PMOS device is formed over the N-well of the semiconductor substrate.
As shown in fig. 1a, a shallow trench isolation structure 103 is also formed in the semiconductor substrate 100 in step S1, and the shallow trench isolation structure 103 isolates the NMOS formation region 101 and the PMOS formation region 102.
In one embodiment, the material of the interface layers 211 and 221 includes silicon oxide. To increase the adhesion between the high dielectric constant layers 212 and 222 and the semiconductor substrate 100.
The materials of the high dielectric constant layers 212 and 222 include silicon dioxide (SiO2), silicon nitride (Si3N4), aluminum oxide (Al2O3), tantalum pentoxide (Ta2O5), yttrium oxide (Y2O3), hafnium silicate oxide (HfSiO4), hafnium dioxide (HfO2), lanthanum oxide (La2O3), zirconium dioxide (ZrO2), strontium titanate (SrTiO3), zirconium silicate oxide (ZrSiO4), and the like.
In one embodiment of the present invention, the bottom barrier layers 213 and 223 include metal nitrides, such as titanium nitride layers 213a and 223a and tantalum nitride layers 213b and 223 b. The bottom barrier layers 213 and 223 are used to prevent the high dielectric constant layers 212 and 222 and the subsequent work function layers from reacting and thereby affecting the work function value.
As shown in fig. 1a, spacers 240 and 250 are further formed on two sides of the polysilicon gate structure.
S2: as shown in fig. 1b, removing the polysilicon gates 310 or 320, forming a first work function layer 11, wherein the first work function layer 11 covers the lateral and bottom surfaces of the removed region of each of the polysilicon gates 310 and 320 and extends to the outside of the removed region of the polysilicon gate 310 or 320, removing a portion of the first work function layer 11, leaving the first work function layer 11 in the removed region of the polysilicon gate 320 of the PMOS, and forming a P-type work function layer of the PMOS from the first work function layer 11;
in one embodiment, the first work function layer 11 is a P-type work function layer made of TiN.
In an embodiment, a first barrier layer may be further formed on the first work function layer 11, and the material of the first barrier layer is a metal nitride, such as TaN. The first barrier layer forms a middle barrier layer of the PMOS, and the middle barrier layer can prevent metal from diffusing into the P-type work function layer of the PMOS through the middle barrier layer.
S3: as shown in fig. 1c, first TiAl layers 215 'and 225' are deposited using a low temperature PVD process;
the first TiAl layers 215 'and 225' are deposited by a low temperature PVD process as a buffer layer to reduce aluminum diffusion caused by high temperatures. In one embodiment, the temperature of the low temperature PVD process ranges from 0 ℃ to 100 ℃, wherein the temperature of the low temperature PVD process may be fixed or may be gradually changed. In one embodiment, the first TiAl layers 215 'and 225' have a thickness of 1 Angstrom to 10 meters.
S4: carrying out a high-temperature annealing process;
in one embodiment, the temperature of the high temperature annealing process ranges from 100 ℃ to 400 ℃.
S5: as shown in fig. 1d, second TiAl layers 215 and 225 are deposited by a high temperature PVD process, the second TiAl layers 215 and 225 constitute a bulk layer of TiAl, and the first TiAl layers 215 'and 225' and the second TiAl layers 215 and 225 after a high temperature annealing process constitute N-type work function layers 216 and 226 of NMOS and PMOS regions;
the PVD process with higher temperature can enhance the mobility of the deposited TiAl particles on the surface of the substrate, generate a reflow phenomenon, reduce the overlap of PVD and improve the subsequent metal gate filling. In one embodiment, the temperature of the high temperature PVD process is in a range of 200-400 ℃, wherein the temperature of the high temperature PVD process may be fixed or may be gradually changed. In one embodiment, the second TiAl layers 215 and 225 are between 10 angstroms and 100 meters thick.
In one embodiment, the ratio of Ti: the Al atomic ratio is larger than that of Ti in the high-temperature PVD process: the Al atomic ratio, i.e. the aluminum content in the low-temperature PVD process, is slightly lower, preferably 5-10%, and different proportions can be realized by different targets.
S6: as shown in fig. 1e, a top blocking layer 217 is formed on the N-type work function layer 216 of the NMOS in an overlapping manner, and a top blocking layer 227 is formed on the N-type work function layer 226 of the PMOS in an overlapping manner, so as to form a metal layer, wherein the metal layer completely fills the removed regions of the polysilicon gates 310 and 320, and is planarized, thereby forming a metal gate 219 of the NMOS and a metal gate 229 of the PMOS.
In an embodiment of the present invention, the material of the top barrier layers 217 and 227 is TiN. In an embodiment of the present invention, the top barrier layer 227 further comprises Ti layers 218 and 228 overlying TiN.
In an embodiment of the invention, the material of the metal gate is generally Al.
In an embodiment, a method for forming an N-type work function layer of an NMOS device is also provided, and in particular, the NMOS formation region 101 on the left side of the AA line shown in fig. 1b to 1d includes:
s1: referring to fig. 1b, a semiconductor substrate 100 is provided, the semiconductor substrate 100 includes an NMOS formation region 101, a process before a metal gate is completed on the semiconductor substrate by using a process method of a dummy polysilicon gate, and a polysilicon gate structure of the NMOS is formed on the surface of the NMOS formation region 101 of the semiconductor substrate 100, and the polysilicon gate is removed to form a groove 410;
in one embodiment, the polysilicon gate structure includes a gate dielectric layer formed by sequentially stacking an interface layer 211, a high-k layer 212 and a bottom barrier layer 213, and a polysilicon gate formed on the gate dielectric layer;
in one embodiment, a P-well is formed in the NMOS formation region 101, and a polysilicon gate structure of an NMOS device is formed over the P-well of a semiconductor substrate.
In an embodiment of the present invention, the material of the interfacial layer 211 comprises silicon oxide. To increase the adhesion between the high-k layer 212 and the semiconductor substrate 100.
The material of the high dielectric constant layer 212 includes silicon dioxide (SiO2), silicon nitride (Si3N4), aluminum oxide (Al2O3), tantalum pentoxide (Ta2O5), yttrium oxide (Y2O3), hafnium silicate oxide (HfSiO4), hafnium dioxide (HfO2), lanthanum oxide (La2O3), zirconium dioxide (ZrO2), strontium titanate (SrTiO3), zirconium silicate oxide (ZrSiO4), and the like.
In one embodiment of the present invention, the bottom barrier layer 213 comprises a metal nitride such as titanium nitride layer 213a and tantalum nitride layer 213 b. The bottom barrier 213 is used to prevent the high dielectric constant layer 212 and the subsequent work function layer from reacting and affecting the work function value.
As shown in fig. 1b, spacers 240 are further formed on two sides of the polysilicon gate structure.
S2: as shown in fig. 1c, a first layer of TiAl layer 215' is deposited on the bottom and sidewalls of the recess 410 using a low temperature PVD process;
the first TiAl layer 215' is deposited by a low-temperature PVD process and is used as a buffer layer, and aluminum diffusion caused by high temperature can be reduced. In one embodiment, the temperature of the low temperature PVD process ranges from 0 ℃ to 100 ℃, wherein the temperature of the low temperature PVD process may be fixed or may be gradually changed. In one embodiment, the first TiAl layer 215' has a thickness of 1 Angstrom to 10 meters.
S3: carrying out a high-temperature annealing process;
in one embodiment, the temperature of the high temperature annealing process ranges from 100 ℃ to 400 ℃.
S4: as shown in fig. 1d, a second layer of TiAl layer 215 is deposited by a high temperature PVD process, the second layer of TiAl layer 215 forms a bulk layer of TiAl, and the first layer of TiAl layer 215' and the second layer of TiAl layer 215 after a high temperature annealing process form an N-type work function layer 216 in the NMOS and PMOS regions.
The PVD process with higher temperature can enhance the mobility of the deposited TiAl particles on the surface of the substrate, generate a reflow phenomenon, reduce the overlap of PVD and improve the subsequent metal gate filling. In one embodiment, the temperature of the high temperature PVD process ranges from 200 ℃ to 400 ℃, wherein the temperature of the high temperature PVD process may be fixed or may be varied. In one embodiment, the thickness of the second TiAl layer 215 is between 10 angstroms and 100 meters.
In one embodiment, the ratio of Ti: the Al atomic ratio is larger than that of Ti in the high-temperature PVD process: the Al atomic ratio, i.e. the aluminum content in the low-temperature PVD process, is slightly lower, preferably 5-10%, and different proportions can be realized by different targets.
Therefore, aiming at the PVD process of the N-type work function layer of the NMOS, firstly, a groove of the NMOS, which is used for forming the metal grid, is formed, then, a thin TiAl layer is deposited by adopting a low-temperature PVD process and used as a buffer layer to reduce aluminum diffusion caused by high temperature, then, high-temperature annealing is carried out, then, a TiAl main body layer is deposited by adopting a high-temperature PVD process, the mobility of deposited TiAl particles on the surface of a substrate can be enhanced at higher temperature, a backflow phenomenon is generated, the overlap of PVD is reduced, a process window for subsequent metal grid filling is improved, namely, two-step PVD deposition is adopted, the inhibition of low-temperature TiAl on Al diffusion and the buffer capacity and the overlap with smaller high-temperature TiAl are taken into consideration, and the filling effect is improved.
In an embodiment of the present invention, an N-type work function layer of an NMOS device is further provided, please refer to the NMOS formation region 101 on the left side of the AA line shown in fig. 1d, which includes: a first TiAl layer 215 ' formed on the bottom and sidewalls of the groove 410 for forming the metal gate and a second TiAl layer 215 formed on the first TiAl layer 215 ', wherein the temperature of the PVD process for forming the first TiAl layer 215 ' is lower than the temperature of the PVD process for forming the second TiAl layer 215, the thickness of the first TiAl layer 215 ' is less than that of the second TiAl layer 215, and the PVD process for the first TiAl layer 215 ' has Ti: the Al atomic ratio is larger than that of Ti: atomic ratio of Al.
In one embodiment, the thickness of the first TiAl layer 215' is between 1 Angstrom and 10 meters and the thickness of the second TiAl layer 215 is between 10 Angstrom and 100 meters. Wherein, the temperature of the PVD process for forming the first TiAl layer 215' and the PVD process for forming the second TiAl layer 215 may be fixed or graded.
The foregoing detailed description of the embodiments of the present application has been presented to illustrate the principles and implementations of the present application, and the description of the embodiments is only intended to facilitate the understanding of the methods and their core concepts of the present application. Meanwhile, a person skilled in the art should, according to the idea of the present application, change or modify the embodiments and applications of the present application based on the scope of the present application. In view of the above, the description should not be taken as limiting the application.

Claims (6)

1. A method for forming a high dielectric metal gate MOSFET structure, comprising:
s1: providing a semiconductor substrate, wherein the semiconductor substrate comprises an NMOS forming area and a PMOS forming area, the process before metal gate is finished on the semiconductor substrate by adopting a process method of a pseudo polysilicon gate, a polysilicon gate structure of NMOS is formed on the surface of the NMOS forming area of the semiconductor substrate, the polysilicon gate structure of PMOS is formed on the surface of the PMOS forming area of the semiconductor substrate, interlayer dielectric layers are filled among the polysilicon gate structures, each polysilicon gate structure comprises gate dielectric layers formed by an interface layer, a high dielectric constant layer and a bottom barrier layer which are sequentially overlapped, and a polysilicon gate is formed on the gate dielectric layers;
s2: removing polysilicon gates to form a first work function layer, wherein the first work function layer covers the side surfaces and the bottom surfaces of the polysilicon gate removal regions and extends out of the polysilicon gate removal regions, part of the first work function layer is removed, the first work function layer in the polysilicon gate removal regions of the PMOS is reserved, and the first work function layer forms a P-type work function layer of the PMOS;
s3: depositing a first TiAl layer by using a low-temperature PVD (physical vapor deposition) process;
s4: carrying out a high-temperature annealing process;
s5: depositing a second TiAl layer by a high-temperature PVD process, wherein the second TiAl layer forms a TiAl main body layer, and the first TiAl layer and the second TiAl layer which are subjected to a high-temperature annealing process form N-type work function layers of an NMOS region and a PMOS region; and
s6: forming a top blocking layer by overlapping the N-type work function layer of the NMOS, and forming a top blocking layer by overlapping the N-type work function layer of the PMOS to form a metal layer, wherein the polysilicon gate removing area is completely filled and flattened by the metal layer to form a metal gate of the NMOS and a metal gate of the PMOS;
wherein the temperature range of the low-temperature PVD process in S3 is 0-100 ℃; the temperature range of the high-temperature annealing process in S4 is 100-400 ℃; the temperature range of the high-temperature PVD process in S5 is 200-400 ℃.
2. The method of forming a high-k metal gate MOSFET structure as claimed in claim 1, wherein: ti in the low-temperature PVD process: the Al atomic ratio is larger than that of Ti in the high-temperature PVD process: atomic ratio of Al.
3. The method of forming a high-k metal gate MOSFET structure as claimed in claim 1, wherein: the temperature of the low temperature PVD process and the high temperature PVD process is fixed or graded.
4. A method for forming an N-type work function layer of an NMOS device is characterized by comprising the following steps:
s1: providing a semiconductor substrate, wherein the semiconductor substrate comprises an NMOS forming area, the process before metal gate is finished on the semiconductor substrate by adopting a process method of a pseudo polysilicon gate, a polysilicon gate structure of the NMOS is formed on the surface of the NMOS forming area of the semiconductor substrate, and the polysilicon gate is removed to form a groove;
s2: depositing a first TiAl layer on the bottom and the side wall of the groove by using a low-temperature PVD process;
s3: carrying out a high-temperature annealing process; and
s4: depositing a second TiAl layer by a high-temperature PVD process, wherein the second TiAl layer forms a TiAl main body layer, and the first TiAl layer and the second TiAl layer which are subjected to a high-temperature annealing process form N-type work function layers of an NMOS region and a PMOS region;
wherein the temperature range of the low-temperature PVD process in S2 is 0-100 ℃; the temperature range of the high-temperature annealing process in S3 is 100-400 ℃; the temperature range of the high-temperature PVD process in S4 is 200-400 ℃.
5. The N-type work function layer forming method of the NMOS device as claimed in claim 4, wherein: ti in the low-temperature PVD process: the Al atomic ratio is larger than that of Ti in the high-temperature PVD process: atomic ratio of Al.
6. An N-type work function layer for an NMOS device, comprising: the PVD device comprises a first TiAl layer and a second TiAl layer, wherein the first TiAl layer is formed at the bottom and the side wall of a groove for forming a metal gate, the second TiAl layer is formed on the first TiAl layer, the temperature of the PVD process for forming the first TiAl layer is lower than the temperature of the PVD process for forming the second TiAl layer, the temperature range of the PVD process for forming the first TiAl layer is 0-100 ℃, the temperature range of the PVD process for forming the second TiAl layer is 200-400 ℃, the thickness of the first TiAl layer is smaller than that of the second TiAl layer, and Ti: and the Al atomic ratio is larger than that of Ti: atomic ratio of Al.
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TW201301360A (en) * 2011-06-21 2013-01-01 United Microelectronics Corp Transistor having aluminum metal gate and method of making the same
CN106158649A (en) * 2015-04-14 2016-11-23 中芯国际集成电路制造(上海)有限公司 The forming method of semiconductor structure

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