CN106252283A - The preparation method of metal gates - Google Patents
The preparation method of metal gates Download PDFInfo
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- CN106252283A CN106252283A CN201610766204.5A CN201610766204A CN106252283A CN 106252283 A CN106252283 A CN 106252283A CN 201610766204 A CN201610766204 A CN 201610766204A CN 106252283 A CN106252283 A CN 106252283A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
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- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The present invention provides the preparation method of a kind of metal gates, including: providing Semiconductor substrate, semiconductor substrate surface has dummy grid, around the side wall of dummy grid and cover dummy grid and the interlayer dielectric layer of side wall；Cmp interlayer dielectric layer, exposes dummy grid, removes dummy gate pole, forms groove；Sidewall and diapire at described groove form insulating barrier, high-k dielectric layer, cap, cushion, work function regulating course and barrier layer successively；Doped with silicon in the sidewall and diapire deposition the first metal layer, and described the first metal layer of described groove；Fill the second metal level in the trench；Described the first metal layer and the second metal level are made annealing treatment.In the present invention, doped silicon in the first metal layer, annealing makes the silicon in the first metal layer diffuse to downwards in barrier layer, and the stability of device, to the blocking capability of metal in the first metal layer and the second metal level, is improved in the case of not affecting metal filled ability in raising barrier layer.
Description
Technical field
The present invention relates to semiconductor integrated circuit manufacturing technology field, particularly relate to the preparation method of a kind of metal gates.
Background technology
In prepared by CMOS transistor device and circuit, along with development and the crucial chi of CMOS integrated circuit fabrication process
Very little reduces, due to SiO2The reduction of gate oxide dielectric thickness makes grid leakage current increase, simultaneously in order to avoid polysilicon
The depletion effect of grid, HKMG (high k metal gate) technique becomes main flow, especially below 28nm technique node.
The HKMG technique typically now used is all gate last, the forming process one of metal gates (metal gate)
As be: with reference to shown in Fig. 1, form the structures such as dummy grid, source electrode, drain electrode, side wall 11 over the substrate 10, then remove dummy grid,
Form groove 12, then, with reference to shown in Fig. 2, use dielectric layer 13, high-k dielectric layer 14, work function regulating course 15 and metal level 16
Fill the groove produced because removing the part of dummy grid, to form metal gates.
But, in prior art, metal level generally uses aluminum metal layer, and aluminum metal can diffuse to downwards work function regulating course
Affect device stability.At present, use one layer of barrier layer of increase between work function regulating course 15 and metal level 16 to stop more
The diffusion of aluminum, but the barrier layer increased occupies certain space, affects the filling capacity of metal level.
Summary of the invention
It is an object of the invention to provide the preparation method of metal gates, solve metal level of the prior art to work function
The technical problem of regulating course diffusion.
For solving above-mentioned technical problem, the present invention provides the preparation method of a kind of metal gates, including:
Thering is provided Semiconductor substrate, described semiconductor substrate surface has dummy grid, around the side wall of dummy gate pole and cover
Lid dummy gate pole and the interlayer dielectric layer of described side wall；
Interlayer dielectric layer described in cmp, exposes dummy gate pole, removes dummy gate pole, forms a ditch
Groove；
Sidewall and diapire at described groove form insulating barrier, high-k dielectric layer, cap, cushion, work function tune successively
Ganglionic layer and barrier layer；
Doped with silicon in the sidewall and diapire deposition the first metal layer, and described the first metal layer of described groove；
Fill the second metal level in the trench；
Described the first metal layer and the second metal level are made annealing treatment.
Optionally, using chemical vapor deposition method to form described insulating barrier, the material of described insulating barrier is silicon oxide, institute
The thickness stating insulating barrier is
Optionally, atomic vapor deposition technique or chemical vapor deposition method is used to form described high-k dielectric layer, described height
The material of k dielectric layer is hafnium oxide, and thickness is
Optionally, the mixed gas of hafnium tetrachloride and steam is used to form described high-k dielectric layer, and described mixed gas
Flow is 5sccm～20sccm, and the temperature forming described high-k dielectric layer is 300 DEG C～550 DEG C.
Optionally, the material of described cushion is tantalum nitride, and the thickness of described cushion is
Optionally, the material of described work function regulating course is titanium-aluminium alloy, titanium carbon alloy or titanium nitride, and described work function is adjusted
The thickness of ganglionic layer is
Optionally, the material on described barrier layer is tantalum nitride or titanium nitride, and the thickness on described barrier layer is
Optionally, described the first metal layer is the aluminum metal of doped silicon, and the concentration of the silicon in described the first metal layer is
0.1ppm～100ppm.
Optionally, the thickness of described the first metal layer is
Optionally, described second metal level is aluminium copper, and wherein, the content of described copper is less than or equal to 1%, described second
The thickness of metal level is
Optionally, the temperature carrying out annealing employing is 350 DEG C～500 DEG C.
Compared with prior art, in the preparation method of the metal gates that the present invention provides, first form first over the barrier layer
Doped with silicon in metal level, and the first metal layer, then form the second barrier layer on the first metal layer, afterwards, to the first metal
Layer and the second metal level make annealing treatment, and annealing makes the silicon in the first metal layer diffuse to downwards in barrier layer, carries
High barrier is to the blocking capability of metal in the first metal layer and the second metal level, in the case of not affecting metal filled ability
Improve the stability of device.
Accompanying drawing explanation
Fig. 1 is the structural representation forming groove in prior art；
Fig. 2 is the structural representation forming metal gates in prior art
Fig. 3 is the flow chart of the preparation method of metal gates in one embodiment of the invention；
The structural representation of the Fig. 4 Semiconductor substrate for providing in one embodiment of the invention；
Fig. 5 is the structural representation forming groove in one embodiment of the invention；
Fig. 6 is to form insulating barrier, high-k dielectric layer, cushion, work function regulating course and barrier layer in one embodiment of the invention
Structural representation；
Fig. 7 is the structural representation forming the first metal layer in one embodiment of the invention；
Fig. 8 is the structural representation forming the second metal level in one embodiment of the invention.
Detailed description of the invention
Below in conjunction with schematic diagram, the preparation method of the metal gates of the present invention is described in more detail, wherein represents
The preferred embodiments of the present invention, it should be appreciated that those skilled in the art can revise invention described herein, and the most real
The advantageous effects of the existing present invention.Therefore, it is widely known that description below is appreciated that for those skilled in the art, and also
Not as limitation of the present invention.
In order to clear, whole features of practical embodiments are not described.In the following description, it is not described in detail known function
And structure, because they can make to due to the fact that unnecessary details and chaotic.Will be understood that opening in any practical embodiments
In Faing, it is necessary to make a large amount of implementation detail to realize the specific objective of developer, such as according to relevant system or relevant business
Limit, an embodiment change into another embodiment.Additionally, it should think that this development is probably complexity and consuming
Time, but it is only routine work to those skilled in the art.
Referring to the drawings the present invention the most more particularly described below in the following passage.Want according to following explanation and right
Book, advantages and features of the invention is asked to will be apparent from.It should be noted that, accompanying drawing all uses the form simplified very much and all uses non-
Ratio accurately, only in order to facilitate, to aid in illustrating lucidly the purpose of the embodiment of the present invention.
The core concept of the present invention is, it is provided that the preparation method of a kind of metal gates, first forms first over the barrier layer
Doped with silicon in metal level, and the first metal layer, then form the second barrier layer on the first metal layer, afterwards, to the first metal
Layer and the second metal level make annealing treatment, and annealing makes the silicon in the first metal layer diffuse to downwards in barrier layer, carries
High barrier is to the blocking capability of metal in the first metal layer and the second metal level, in the situation of the filling capacity not affecting metal
The stability of lower raising device.
Being described in detail the preparation method of the metal gates of the present invention below in conjunction with accompanying drawing 3～Fig. 8, Fig. 4 is metal
The flow chart of the preparation method of grid, Fig. 4～Fig. 8 is the structural representation that each step is corresponding, the preparation method bag of metal gates
Include following steps:
First, with reference to shown in Fig. 4, perform step S1, it is provided that Semiconductor substrate 100, described Semiconductor substrate 100 can be
The substrat structures known in those skilled in the art such as silicon substrate, germanium silicon substrate, carbon silicon substrate, SOI substrate.At described quasiconductor
Substrate 100 is formed the structures such as fleet plough groove isolation structure, source electrode, drain electrode.Afterwards, formed on described Semiconductor substrate 100 surface
Dummy grid 110, around the side wall 120 around dummy gate pole 100 and cover dummy gate pole 110 and the layer of described side wall 120
Between dielectric layer 130, wherein, dummy gate pole 110 is polysilicon, and described side wall 120 is silicon nitride, described interlayer dielectric layer 130
For silicon oxide, described interlayer dielectric layer 130 protects the structure in Semiconductor substrate 100 in subsequent technique.
Then, with reference to shown in Fig. 5, step S2 is performed, interlayer dielectric layer 130 described in cmp, stop at described
On dummy grid 110, thus expose dummy gate pole 110.Further, then remove dummy gate pole 110, form a groove 140.
In the present embodiment, dry etch process can be used to remove dummy gate pole 110.
Performing step S3, with reference to shown in Fig. 6, sidewall and diapire at described groove 140 form insulating barrier 150, high k successively
Dielectric layer 160, cushion 170, work function regulating course 180 and barrier layer 190.Concrete, first at sidewall and the end of groove 140
Wall forms insulating barrier 150, uses chemical vapor deposition method to form described insulating barrier 150, and insulating barrier is used for will be located in thereon
Isolate between metal gates and Semiconductor substrate 100, and the material of described insulating barrier 150 is silicon oxide, described insulating barrier
The thickness of 150 isForming high-k dielectric layer 160 afterwards on insulating barrier 150, described high-k dielectric layer 160 is for shape
Become gate dielectric layer, use atomic vapor deposition technique or chemical vapor deposition method to form described high-k dielectric layer 160, described
The material of high-k dielectric layer 160 is hafnium oxide, and thickness isSuch as, thickness is Deng, and use
The mixed gas of hafnium tetrachloride and steam forms described high-k dielectric layer 160, described mixed gas flow be 5sccm～
20sccm, the temperature forming described high-k dielectric layer 160 is 300 DEG C～550 DEG C.Then, described high-k dielectric layer forms lid
Cap layers (not shown), described cap is titanium nitride, and thickness isAgain, high-k dielectric layer forms buffering
Layer 170, described cushion 170 is tantalum nitride, and the thickness of described tantalum nitride isAgain, cushion 170 is formed
Work function regulating course 180, work function regulating course is for the threshold voltage of adjusting means, the material of described work function regulating course 180
For titanium-aluminium alloy, titanium carbon alloy, titanium nitride etc., the thickness of described work function regulating course 180 isAfterwards, in work content
Forming barrier layer 190 on number regulating course 180, for the diffusion of barrier metal, the material on described barrier layer 190 is tantalum nitride or nitrogen
Changing titanium, the thickness on described barrier layer 190 isAdditionally, so that the cestode of subsequent metal？Effect is more preferable, in resistance
Can also form a soakage layer (not shown) in barrier 190, the material of described soakage layer is titanium or cobalt, the thickness of soakage layer
For
Afterwards, with reference to shown in Fig. 7, perform step S4, at sidewall and the diapire deposition the first metal layer of described groove 140
210, the first metal layer 210 covers described barrier layer 190, to described first gold medal while depositing described the first metal layer 210
Belong to doped silicon in layer 210 so that described the first metal layer 210 becomes the aluminum metal doped with silicon, described the first metal layer 210
Thickness isAdditionally, according to the design needs of device architecture, the concentration of the silicon in described the first metal layer 210 sets
It is set to 0.1ppm～100ppm.It should be noted that the silicon in the first metal layer can diffuse to barrier layer in subsequent technique
In 190 so that barrier layer 190 can to the blocking capability of metal in the first metal layer and the second metal level, thus not necessarily in
In metal gate structure, the extra barrier layer increasing by one layer of TaN, adds the filling window of metal.
Perform step S5, with reference to shown in Fig. 8, described groove 140 is filled the second metal level 220, described second metal
Layer 220 covers described the first metal layer 210, and the second metal level 220 fills full whole groove.Simultaneously, described second metal level
220 is aluminum metal, and the thickness of described second metal level 220 isSuch as,Certainly, it will be appreciated by persons skilled in the art that described second metal level 220 not
Being limited to aluminum metal, described second metal level 220 can also be aluminium copper, and wherein, the content of described copper is less than or equal to 1%,
Use aluminium copper can increase the electric conductivity of the second metal level 220, the performance of semiconductor device can be improved.
Finally, perform step S6, described the first metal layer 210 and the second metal level 220 are made annealing treatment, annealing treatment
Reason makes the silicon in the first metal layer 210 diffuse in barrier layer 190.In the present embodiment, carry out the temperature that annealing uses
It is 350 DEG C～500 DEG C, such as, 400 DEG C, 450 DEG C, 500 DEG C etc..
In sum, in the preparation method of the metal gates that the present invention provides, first form the first metal layer over the barrier layer,
And doped with silicon in the first metal layer, then form the second barrier layer on the first metal layer, afterwards, to the first metal layer and second
Metal level makes annealing treatment, and annealing makes the silicon in the first metal layer diffuse to downwards in barrier layer, improves barrier layer
To the blocking capability of metal in the first metal layer and the second metal level, in the case of the filling capacity not affecting metal, improve device
The stability of part.
Obviously, those skilled in the art can carry out various change and the modification essence without deviating from the present invention to the present invention
God and scope.So, if these amendments of the present invention and modification belong to the scope of the claims in the present invention and equivalent technologies thereof
Within, then the present invention is also intended to comprise these change and modification.
Claims (11)
1. the preparation method of a metal gates, it is characterised in that including:
There is provided Semiconductor substrate, described semiconductor substrate surface have dummy grid, around dummy gate pole side wall and cover institute
State dummy grid and the interlayer dielectric layer of described side wall；
Interlayer dielectric layer described in cmp, exposes dummy gate pole, removes dummy gate pole, forms a groove；
Sidewall and diapire at described groove form insulating barrier, high-k dielectric layer, cap, cushion, work function regulating course successively
And barrier layer；
Doped with silicon in the sidewall and diapire deposition the first metal layer, and described the first metal layer of described groove；
Fill the second metal level in the trench；
Described the first metal layer and the second metal level are made annealing treatment.
2. the preparation method of metal gates as claimed in claim 1, it is characterised in that use chemical vapor deposition method or oxygen
Metallization processes forms described insulating barrier, and the material of described insulating barrier is silicon oxide, and the thickness of described insulating barrier is
3. the preparation method of metal gates as claimed in claim 1, it is characterised in that use atomic vapor deposition technique or change
Learning gas-phase deposition and form described high-k dielectric layer, the material of described high-k dielectric layer is hafnium oxide, and thickness is
4. the preparation method of metal gates as claimed in claim 3, it is characterised in that use the mixed of hafnium tetrachloride and steam
Close gas and form described high-k dielectric layer, and described mixed gas flow is 5sccm～20sccm, forms described high-k dielectric layer
Temperature is 300 DEG C～550 DEG C.
5. the preparation method of metal gates as claimed in claim 1, it is characterised in that the material of described cushion is nitridation
Tantalum, the thickness of described cushion is
6. the preparation method of metal gates as claimed in claim 1, it is characterised in that the material of described work function regulating course is
Titanium-aluminium alloy, titanium carbon alloy or titanium nitride, the thickness of described work function regulating course is
7. the preparation method of metal gates as claimed in claim 1, it is characterised in that the material on described barrier layer is tantalum nitride
Or titanium nitride, the thickness on described barrier layer
8. the preparation method of metal gates as claimed in claim 1, it is characterised in that described the first metal layer is doped silicon
Aluminum metal, the concentration of the silicon in described the first metal layer is 0.1ppm～100ppm.
9. the preparation method of metal gates as claimed in claim 1, it is characterised in that the thickness of described the first metal layer is
10. the preparation method of metal gates as claimed in claim 1, it is characterised in that described second metal level is aluminum metal
Or aluminium copper, wherein, the content of described copper is less than or equal to 1%, and the thickness of described second metal level is
The preparation method of 11. metal gates as claimed in claim 1, it is characterised in that carry out the temperature that annealing uses
It it is 350 DEG C～500 DEG C.
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| CN201610766204.5A CN106252283B (en) | 2016-08-30 | 2016-08-30 | The preparation method of metal gates |
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| CN201610766204.5A CN106252283B (en) | 2016-08-30 | 2016-08-30 | The preparation method of metal gates |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115424935A (en) * | 2022-08-30 | 2022-12-02 | 中芯越州集成电路制造(绍兴)有限公司 | Method for manufacturing semiconductor device |
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| CN103515318A (en) * | 2012-06-20 | 2014-01-15 | 中芯国际集成电路制造(上海)有限公司 | CMOS fully-silicided metal gate preparation method |
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| CN104752349A (en) * | 2013-12-26 | 2015-07-01 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device manufacturing method |
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2016
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Patent Citations (4)
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| CN103377899A (en) * | 2012-04-25 | 2013-10-30 | 中芯国际集成电路制造(上海)有限公司 | Metal grid electrode manufacturing method and CMOS manufacturing method |
| CN103515318A (en) * | 2012-06-20 | 2014-01-15 | 中芯国际集成电路制造(上海)有限公司 | CMOS fully-silicided metal gate preparation method |
| CN104124169A (en) * | 2013-04-28 | 2014-10-29 | 中芯国际集成电路制造(上海)有限公司 | NMOS transistor and forming method thereof and CMOS transistor and forming method thereof |
| CN104752349A (en) * | 2013-12-26 | 2015-07-01 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device manufacturing method |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115424935A (en) * | 2022-08-30 | 2022-12-02 | 中芯越州集成电路制造(绍兴)有限公司 | Method for manufacturing semiconductor device |
| CN115424935B (en) * | 2022-08-30 | 2024-05-14 | 中芯越州集成电路制造(绍兴)有限公司 | Method for manufacturing semiconductor device |
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