JPS5889865A - Insulated gate type semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To decrease input capacity and to improve breakdown resistance voltage by forming a low resistivity second conductive type region on the source side by a self-aligning method, and forming a gate electrode on the region through an insulating film with the surface of a first conductive type well region as a channel part. CONSTITUTION:A P<+>P<->N<-> type three layer Si substrate is prepared. A thick oxidized SiO2 film 23 is formed on the surface of an N<-> type layer 22. Then, a mask 24, which covers a part of and the drain side of the SiO2 film 23, is formed by photoresist and the like. B is introduced in order to form P type well in the surface of the N<-> layer on the source side. The mask is removed, and e.g. As is deposited and diffused. Thus an N<+> source 25, an N<+> drain 26, and a P well 27 are formed. The insulating film on a source drain contact part is removed. A conductor 30 such as Al is evaporated. The unnecessary part of the Al is removed by photoethcing. Thus a source electrode S, the gate electrode G, and a drain electrode D are formed.

Description

[Detailed Description of the Invention] To this book' [HAHAWA M Ojl IF Ii? (Relating to gold@oxide semiconductor field effect transistor).

A horizontal offset gate structure has been adopted in the MO51PIT for high frequency power. As shown in Figure 1, a high resistivity P-type 81 layer 2 is formed on a low resistivity P1 type S1 base ikl, and an N-type well 3° 4- is formed from a part of the surface of this P layer 2. 1- is formed and C diffusion layers 5 and 6 are provided on the surfaces of the P layer 2 and the Nfi well 3 to serve as a source (8) and a drain (D). By forming a conductor layer 8 that will become a gate (G) through a thin insulating film 7 on the surface of P-fi2 between the source and drain, and introducing an N-type impurity as a mask for the gate 8, M'l )
Connect to 3゜4 ^ Voltage offset gate N single layer 9
In such a horizontal offset gate MO8IFICT, the channel length can be reduced by self-alignment of the offset gate. ', 01gg (incoming capacitance), and '17118 (feedback capacitance) can be destroyed. But the shrimp.

The concentration of P in the 2nd layer due to taxial growth is regulated, and the concentration in the drain IIM well is relatively large in 2008.
8 (output capacity) is large.

As other power MO8FllT, slguneti
There is a structure proposed by cl. As shown in FIG.
From the surface of the M layer of the source thin layer, a P well 13 is formed as a 12 t square oxide film reaching the P layer 10, and the P well 13 and the N layer 11. An M+ layer 14.15t-, which will become a source and drain, is formed on the narrow surface of the M+ layer 14.15t-.

At this time, the N+ layer of sauce evening! 4 uses the P-well type mask. This is a structure in which a gate 17 is provided on a semiconductor layer between a source and a drain via a thin insulation w416. In this structure, the large part of the drain junction is formed by an N-/P-junction that can be controlled to have am wrinkles, so FI? During operation, the depletion layer spreads widely from the junction, making it possible to reduce 0°1111 (output capacitance).

Only MOBI! In RT, (11) the high-resistance p-substrate IO is used, so the output conductance is large and the output loss is large; (2) there is no self-alignment relationship between the channel part and the gate, so O □.

(3) The southern part of the gate is a wide gate oxide film, which causes electric field concentration there and limits the drain breakdown voltage; and (4) the source is connected to the substrate within the chip. Kii! Because it is not 1 in il, source wire [Multi-layer installation d111! There are disadvantages such as the fact that

The present invention has been made to overcome the drawbacks of the above-mentioned American technology, and its purpose is to provide ultra-high frequency power MOaFJItTi.

The present invention will be described in detail below.

Embodiment 91 is shown in FIG. 3 (-) to 3).
The actual production of O8'lWT is shown in terms of each process, which is the king of its manufacturing process.

(a) A P"P N-type three-layer 81 substrate is prepared.

For example, a P+ layer 21 is formed by door-type diffusion on one main surface of a P-type s1 group ζ20, while an N-type epitaxial layer (impurity once N:l□th-"ato) is formed on the other main surface.
ms/aj) 22k growth 1J-17t4(F
). Alternatively, the N-type layer 22t- may be formed by an N''-fi diffusion layer on the other surface of a thickly formed P-type 81 substrate.

A thick StO self-film 23 is formed on the surface of the N-type layer 220 using an oxidation furnace, and photoetching is performed to expose the source/drain regions. Next, a mask 24 made of photoresist or the like is formed to cover a part of the Elloslltg and the drain 11, and a B layer is formed on the YR surface of the N layer on the source side to form a P type layer.
(Boron) is introduced. -(t)) Remove the 613rd mask, deposit ^8 (arsenic), then diffuse C and K to N-type source 25. N+ drain 2
6 (N: 10"atoms/mA, )t- is formed. At this time, B introduced in the previous process is diffused into the N layer with a high diffusion rate, connects to the A & P layer 20, and P which extends in the lateral direction. Sea urchin A (M: 10” atom
s/cd) form 272.

(0)! The saponified II 23t of the photo-etching process is either left as it is or once removed to form a thick AaI film 28, and then photoetched to form an oxidized J11 on the gate and source/drain contact areas. is removed and gate oxidation is performed to form a thin gate insulating film 29f.

(Success) The insulating film on the source drain contact part is removed, a conductor 30 such as aluminum (aluminum) is evaporated, the aluminum part is removed by a photoetching process 11, and the source 8. , ToG, Dray/D each electric I/
ht-form.

Due to the above-mentioned pro 4s, the speed is slowed down and the 9y channel uos
ylTK$Ph has a low resistance P+ layer 211 under the P layer 27 as a substrate, so the output conductance is about 1
reduced to 1/0. That is, the output conductance j
Cgos can be reduced by reducing the drain resistance RDt- from the relationship gos=(ooo,)tRD. The targets are shown according to each step of the manufacturing process.

6L) P" P-N- type 3-layer 81 substrate (same as in the case of maiden row 1) 21-20-221 is prepared. This upper layer N layer 2
After forming a thick VH@ oxide film 31 on 2, the oxide film 31 is removed from the portions that will become the gate and source/drain parts during photoetching, and gate oxidation is performed to form a thin gate insulating film 32.
form. 71131 thick oxidation 71131
One end is the P-well diffusion, which becomes channel AII, and dM+
It is defined by the diffusion mask position, and the other QBs are defined by the gate position.

佽) A polycrystalline 81 layer 33 is formed as shown in t415 on the gate insulating film 32 and the drain 1N layer 22, and a source @ KB (boron) is introduced by ion implantation using the groove as a mask. - Layer 20 & Cl11 continuous and deep P-well region 34 under the gate glazing film
form.

(0) By selectively removing the polycrystalline Bi layer 3 of the drain layer and depositing and diffusing Mu8 (epsilon), a shallow N+ region 35.36 is formed to become the source/drain.
1- form. At this time, 81 polycrystalline layers 33iCN
Impurities are doped to lower the resistance and the original gate voltage is 4ikGt.
obtain.

(e) H semiconductor region surface 3 that becomes source/drain
5.36, selectively attach the source electrode B to the mu 137,
Form a drain electrode.

By the process described above, p#! built y channel mo
In sFIt, as shown in FIG. The input capacitance Ot s
. A large reduction (approx./2)! I] becomes 111@.

Implementation-j3 g5 Figure shows H channel power MO8F revealed in implementation M2
At ICTIC, the first layer of the gate type was formed with a low resistivity polycrystalline 81 layer 37, and the eyelet was formed by overlapping a low resistivity metal film, MQ (Molypude 7) 1113B. This is a case in point.

(The electrode 39 that makes contact with the source and drain is made of MO or mul.) In this way, the gate voltage ll1
With the i2 layer, the resistance of the gate and the wiring connected to the gate can be reduced.

Implementation number 116-) to (0) were implemented in IP12, :(, and the gate insulating film was made into a step-like shape to make the drain thicker. (IL) After forming the gate insulator 1[32, the source -ii tube etching f is removed.

(1)) Perform gate oxidation and create a new thin insulating film 32
, and the initial insulation [132' will be slightly increased in thickness to 1'.

(0) Completed image @f) MOgPITl is shown. In this way, by increasing the thickness of the gate insulating film 321 drain, the electric field is concentrated or relaxed in the ffc portion during MOaF1 operation, and the breakdown voltage is improved. In the power MO8P1 described above, it is provided in the P diffusion layer 401 that reaches the P+ substrate 21 from the surface of the P well layer 34, and is shown as the electrode 41 of the N+ source.

In addition, FIG. 8 shows that instead of forming a P+ diffusion layer, P+
Concave part number 21 with a depth of 10 to 20 μm reaching the substrate
formed on the P substrate, the N source electrode and the tA electrode 43
indicates the columns to be connected. According to these structures, the electric current R passes directly from the north to the P+ substrate 21, making the plurality of source wires pseudo-wires, eliminating the inductance of the wires themselves, and reducing the number of man-hours for wire bonding by 273.
It is a pity that the cost has been reduced, contributing to cost savings.

Power MO used in the present invention at ultra-high spider waves in the bone KGHg band
8νl'l'Kj is effective.

[Brief explanation of the drawing]

Figures 1- and 2 are # side views showing an example of the conventional power M0811T, and Figures 3 (a) to (the slopes are 4Jf of the present invention).
ltExample 1Mo2) Step I#It showing the process of Shimate
h figure, W4 +'#;l' book IAk14 (D actual y @ n
2) Work type 11 showing the process of M Oa y yaT
H side view, Figure 5 MOBF1 of Embodiment 3 of the present invention? 6(a) to (C) are the cross-sectional views of FIGS.
Work type cross-sectional diagram showing a part of O1ilFlte process, No. 7
The figure and FIG. 8 show the implementation of the present invention - 50M08FIi? FIG. 1...P substrate, 2...P single layer (substrate), 3.4.
;・H-well゛, 5, 6...1゛source, drain, 7...gate insulating film, 8...gate, 9...1-
Offset gate, 11...N-epitaxial layer,
12...4 vs oxidative conversion, 13...P well, 14.
．． 15...N+ source, drain, 16...gate insulating film, 17...-gate, 21...P+ substrate, 2
2...P single layer (substrate), 22...N-Evita medium vial layer, 23...thick oxide film, 2 layers, 25.2
-6...1 source, drain, 27...P well,
2゛8... Thick oxide film, 29... Gate oxide film, 3
0...Conductor layer, 31...I thick oxide film, 32...Gate insulating film, 33...Multi-layer 81 layer, 34...P well, 35.36...N source. Drain 37...
-Low resistivity semiconductor layer, 3-8...Low resistivity metal layer, 4
0...P diffusion layer, 41...mu1tji! Maro, 62
...Concave part, 43...AI tsuba. Figure 1 Figure 2. /J Figure 3 Figure 5 Figure 6 Figure 7 Figure 8 Figure 2/

Claims (1)

[Claims] 1. Low resistivity first conductive half-layer substrate - 1 plate growth direction and intermediate layer resistivity 1g1 conductive semiconductor layer and upper layer high resistivity g24
In a three-layer conductor substrate with one semiconductor layer, a layer of 11! A first conductive semiconductor well 1111 is formed next to the first conductive semiconductor well 1111, and a low-ratio paper is applied to a part of the area surface curve and another part of the surface of the 24th electrically conductive semiconductor layer. M is provided in the second conductive semiconductor region 1 to serve as a source and a drain, of which the low resistivity second conductor ff1 is formed in a self-aligned manner through a common diffusion mask with the first conductive type A region. It is made by forming a gate electrode on C through an insulator using the W-type low region surface, which is outside the range of the second conductivity type, as a chapol part. Semiconductor device 2. The insulated gate hazy semiconductor according to claim 1, wherein the isolation gate is shared as a part of a diffusion mask, and the positions of the channel portion and the gate are defined in a self-aligned manner. Device. 3. The insulated gate type semiconductor device according to item 2, wherein the insulated gate is formed by forming a conductor at a shadow on an impurity-doped semiconductor layer. 4.- The insulated gate lid semiconductor device according to claim 2 or IA3, wherein the above-mentioned insulated gate lid semiconductor device is provided on a staircase that gradually increases in distance from the channel portion position to the drain −K. 5. P E' M (My father is M M P
) In the three-layer 81 semi-quad substrate, there is an oxide film on a part of the upper layer N-noodle surface and a wide oxidation tube shape adjacent to this thick oxide film, and the above-mentioned oxide film tma δ Upper layer M-(
P-) JIIK! '(M) Wrinkle impurity and M + (v
+) Child impurities are introduced into the t-M-(P-) layer and the deep P is created by utilizing the difference between the seven amplification and directness ^t- to connect the groan-(N-) layer.
(M) Well stone forms a shallow M (P,) clearing area, and a t-channel corridor on the surface of the i' (M) layer extending laterally, on which the A low resistivity conductor layer structure is used, and a conductor layer is provided to form a gate.
A method for manufacturing an insulating cat semiconductor device using mold.