JPH0212030B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device.
This invention relates to a method for three-dimensionally stacking MOSFETs on a substrate.

[Technical background of the invention]

Recently, polysilicon film has been used, and laser,
A technique that promotes crystal growth by applying annealing treatment using an electron beam, heat, etc., and forming a semiconductor element on a recrystallized polysilicon film is attracting attention. Using this technique, it is possible to three-dimensionally integrate semiconductor elements.

To give a specific example, a complementary MOSFET (CMOSFET) is created in which a p-channel MOSFET is formed on a single-crystal silicon substrate, and an n-channel MOSFET with a common gate is formed on a recrystallized polysilicon layer laminated on top of this by laser annealing. The characteristic values are -2.2V threshold on the p channel side.
Surface mobility 180cm ² /V・S, surface charge 1.6×10 ¹¹ cm
^-2 , threshold 2.1V on the n-channel side, surface mobility
It has been reported that 160 cm ² /V·S was obtained (1980, JFGibbons & KFLee). The practicality of similar vertical CMOS was also reported by GT Goeloe et al. and JP Colinge et al. at the 1980 IEDM.

[Problems with background technology]

When stacking polysilicon layers on a single-crystal silicon substrate or an insulator substrate to form integrated multilayer semiconductor devices, the fundamental process importance is to reduce the number of photoengraving steps and to improve the efficiency of each step. These include making the surface as flat as possible and reducing the level differences in wiring. In this regard, the vertical CMOS that has been reported so far has large steps and does not take element planarization into consideration, leaving major problems in reliability and yield when integrated at high density.

Furthermore, when creating a vertical CMOS, the gate electrode is shared as described above, and the upper MOSFET has a polysilicon layer deposited on the gate electrode with a gate oxide film interposed therebetween. This is because if the upper MOSFET has a structure in which a gate electrode is provided on the surface of the polysilicon layer separately from the gate electrode of the lower MOSFET, the upper
This is because a back gate bias is applied to the MOSFET by the gate electrode of the lower MOSFET. However, if such a stacked structure with a common gate electrode is used, the upper MOSFET has a polysilicon deposition process after the gate oxidation process, so the local level density at the gate oxide film-polysilicon layer interface is 5×
It is often about 10 ¹¹ to 1×10 ¹² cm ^-2 , which is an order of magnitude higher than that of the lower MOSFET.
The reason for this is that impurities present on the wafer surface after manufacturing the lower MOSFET are incorporated into the gate oxide film during the gate oxidation process of the upper MOSFET. This makes it difficult to control the threshold value of the upper MOSFET. Also, in this structure, the top MOSFET
Since the gate electrode is under the semiconductor layer, the bottom
Unlike MOSFETs, the self-alignment technology used in normal silicon gate processes cannot be applied as is.

[Purpose of the invention]

An object of the present invention is to apply self-alignment technology to the upper MOSFET at the same time as surface flattening when creating a three-dimensional MOS integrated circuit by sharing the gate electrode of the MOSFET in the substrate semiconductor layer as the gate electrode of the upper MOSFET. The aim is to improve performance.

[Summary of the invention]

In the present invention, the substrate semiconductor layer includes a first
When forming a MOSFET, unlike a normal silicon gate process, the first polysilicon layer containing impurities, which will become the gate electrode, is deposited and then covered with an oxidation-resistant mask and selectively oxidized without photo-etching. A gate electrode and source and drain contact electrodes are formed separately, and at the same time, source and drain regions are formed by solid phase diffusion from this polysilicon layer. In this way, the first MOSFET is formed by filling the region between the first polysilicon gate electrode and the source and drain contact electrodes with polysilicon oxide, thereby making the surface substantially flat. and the first
A second polysilicon layer is deposited on the substrate on which the MOSFET is formed, and a second MOSFET is formed thereon.

The present invention also provides solid-phase diffusion into the second polysilicon layer from the back surface when forming a second MOSFET by sharing the gate electrode on the first MOSFET formed by flattening the surface as described above. A self-aligned structure is achieved by using That is, the second
Before depositing the polysilicon to make the MOSFET,
A portion of the silicon oxide film between the gate electrode and the source and drain contact electrodes of the first MOSFET is etched, and an impurity-containing layer is selectively buried in the recessed portion. Then, a second polysilicon layer is deposited on the surface of the gate electrode of the first MOSFET via a gate oxide film, and the impurities from the impurity-containing layer are solid-phase diffused to form the source and drain regions of the second MOSFET. Obtain a self-aligned structure.

〔Effect of the invention〕

According to the present invention, there is no photo-etching process for the first polysilicon layer that becomes the gate electrode of the first MOSFET, and selective oxidation of the first polysilicon layer allows the polysilicon layer to directly contact the source and drain as well as the gate electrode. A contact electrode and source and drain regions are simultaneously formed, and the surface of this first MOSFET is flattened. Therefore, on top of this, the second
When forming a MOSFET and arranging metal wiring,
There is no need to form contact holes that reach the substrate semiconductor layer for the source and drain of the first MOSFET, and the steps in the metal wiring are smaller than in the past, reducing the possibility of disconnections in the wiring of 3D MOS integrated circuits. This can be reliably prevented.

Furthermore, according to the present invention, in addition to improving reliability through surface flattening as described above, the second MOSFET is made into a self-aligned structure using solid-phase diffusion from the backside, thereby providing a three-dimensional structure capable of high-speed operation.
A CMOS integrated circuit is obtained.

[Embodiments of the invention]

FIGS. 1a to 1g are cross-sectional views showing the manufacturing process of an embodiment of the present invention. First, a field oxide film 2 is formed on an n-type Si substrate 1 by selective oxidation or the like (a). Next, an oxide film of approximately 1000 Å is formed using a hydrochloric acid oxidation method, and unnecessary portions are removed by etching to form a gate oxide film 3 (b). Next, a first polysilicon layer 4 containing about 5×10 ¹⁹ cm ^-3 of boron is deposited to a thickness of about 0.7 μm over the entire surface (c). Subsequently, an oxide film 5 of about 1500 Å is formed by hydrochloric acid oxidation, and a silicon nitride film 6 is formed thereon by CVD or sputtering (d). Then, this laminated film of nitride film 6 and oxide film 5 is patterned so as to remain in the gate electrode region and source/drain contact electrode region, and selectively oxidized by high pressure oxidation method (9 kg, 600°C) using the remaining laminated film as a mask. Then, the entire polysilicon layer 4 is converted into an oxide film 7 in its thickness direction, and a gate electrode 4 ₁ , a source contact electrode 4 ₂ and a drain contact electrode 4 ₃ are formed separately (e). At this time, the mask pattern consisting of the laminated film of the nitride film 6 and the oxide film 5 is designed to cover the gate electrode sufficiently far into the field region in consideration of the final electrode extraction, as shown by the broken line in FIG. The pattern is such that it extends. In this step, boron contained in the polysilicon layer 4 is diffused into the substrate 1, and a source region 8 and a drain region 9 are simultaneously formed. Note that if the surface of the oxide film 7 buried by this selective oxidation has a large protrusion, it is desirable to planarize the surface by etching the oxide film. In this step, for example, a fluid material film such as a resist having an etching rate similar to that of the oxide film 7 is applied to flatten the surface, and then this fluid material film and the oxide film below it are removed by dry etching. 7
This can be done by uniformly etching until the nitride film 6 is exposed, or more simply by slightly chemically etching the surface of the oxide film 7 using the nitride film 6 as a mask.

In this way, a p-channel MOSFET, which is the first MOSFET, with a substantially flat surface is obtained. Thereafter, the nitride film 6 is removed by etching, and the oxide film 5 is left as it is to be used as the gate oxide film of the second MOSFET, and approximately
Deposit a second polysilicon layer 10 of 0.6 μm
(f). This polysilicon layer 10 contains 1 to 10% boron.
5×10 ¹⁶ cm ^-3 ions are implanted and annealing is performed using a CWAr laser or the like. The conditions for laser annealing are, for example, output power 9~11W, spot size 60~90μ
mφ, feed width 10~40μm, feed speed 5~12.5cm/
sec. Phosphorus ions are selectively implanted into the recrystallized second polysilicon layer 10 to form a source region 11 and a drain region 12, and unnecessary portions of the second polysilicon layer 10 are removed by etching to cover the entire surface. An oxide film containing phosphorus and boron, that is, a BPSG film 13, is deposited to a thickness of 0.5 to 0.8 μm using the CVD method, and after contact holes are formed in this, the surface is smoothed by heat treatment, and electrodes are formed by, for example, vapor deposition or etching of an Al film. Wiring lines 14 ₁ to 14 ₃ are formed to complete the MOSFET (g).

The characteristics of the MOSFET according to this example are as follows. First, the first MOSFET, a p-channel CMOSFET on the substrate side, has a substrate concentration of 1×10 ¹⁵ cm ^-
3. When the gate oxide film thickness is 1000 Å, the ratio of channel width W to channel length L is W/L = 20/8, the threshold value is V _T = -1.6 V, and the local level density is Q _SS 5 × 10. ¹⁰ cm ^-
It is ² . The second MOSFET, an n-channel MOSFET on the second polysilicon side, has a polysilicon concentration of 2×10 ¹⁶ cm ^-3 , a gate oxide film thickness of 1500 Å, and a ratio of channel width W to channel length L of W/L= 16/8
When , the threshold value is V _T =+2.0V, and the local level density is Q _SS 5×10 ¹¹ cm ⁻² . Figure 3 shows the characteristics of this MOSFET. In this manner, according to this embodiment, the localized level density of the second MOSFET on the polysilicon side is also relatively small, making it easy to control the threshold value. This is a process in which the gate oxide film of the second MOSFET becomes the gate electrode of the first MOSFET after depositing the first polysilicon layer 4, which is then immediately oxidized on the entire surface and then covered with a nitride film 6. This is because the gate oxide film is freed from impurity contamination and the quality of the gate oxide film is improved. This also improves the operating speed of the second MOSFET.

According to this embodiment, the first
The MOSFET is formed with a flat surface, and after the second MOSFET is laminated thereon, the electrodes are taken out using the source and drain contact electrodes 4 ₂ , 4 ₃ becomes part of the extraction electrode as it is, so the level difference in the metal wiring is smaller than before.
Therefore, disconnection of the wiring is reliably prevented. As a result, the reliability and yield of the three-dimensional MOS integrated circuit can be improved.

In addition, in the example, a vertical type with a shared gate electrode is used.
Although the case of CMOS has been described, the present invention is not limited to this. For example, the MOSFET formed in the second polysilicon layer is similar to that of the first MOSFET.
As long as the gate electrode is not directly above the gate electrode, the gate electrode may be provided in the usual form on the front surface side. In that case, the conductive channels of the first and second MOSFETs may be either p or n.

Next, in addition to the same surface flattening as in the above example,
An embodiment of the present invention in which the source and drain regions of the second MOSFET are formed in self-alignment with the gate region using solid-phase diffusion from the back side will be described with reference to FIGS. 4a to 4j. do. 1st
Portions corresponding to those in FIGS. a to g are designated by the same reference numerals, and detailed description thereof will be omitted. The steps in FIGS. 4a to 4e are the same as those in FIGS. 1a to 1e. first
The p-channel MOSFET, which is a MOSFET, is
A gate electrode 4 ₁ , a source contact electrode 4 ₂ , and a drain contact electrode 4 ₃ are formed by selective oxidation of the polysilicon layer 4 , and the space between them is filled with an oxide film 7 to form a flat surface. Using 6 as a mask, a portion of the oxide film 7 is etched to form a recess 21 (f). In this recess 21,
A second layer of polysilicon made of second polysilicon is then formed.
An impurity-containing layer that serves as an impurity diffusion source for the source, drain, and other wiring layers of the MOSFET is buried flatly. That is, after oxidizing the exposed side surfaces of the gate electrode 4 ₁ , source contact electrode 4 ₂ , and drain contact electrode 4 ₃ , impurity doping is performed, for example, by doping 1×10 ²⁰ cm ⁻³ with arsenic and phosphorus at an atomic ratio of 1:20. An oxide film 22 is deposited over the entire surface by a high-frequency plasma discharge method to a thickness comparable to the depth of the recess 21, and then a resist film 23, for example, is deposited as a fluid film having an etching rate comparable to that of the oxide film 22. The surface is flattened by spin coating (g).
Then, this resist film 23 and the impurity-doped oxide film 22 thereunder are uniformly etched by a dry etching method until the nitride film 6 is exposed, and then the nitride film 6 is etched.
(h). Thereafter, a second polysilicon layer 10 is deposited over the entire surface as in the previous embodiment (i). This second polysilicon layer 10 is then subjected to recrystallization treatment such as boron ion implantation and laser annealing, and the source region 11 and drain region 1 are formed by solid phase diffusion from the impurity-doped oxide film 22.
2. Form other necessary wiring areas, pattern this second polysilicon layer 10, and finally
The entire surface is covered with a BPSG film 13, contact holes are made, and electrode wirings 14 ₁ to 14 ₃ made of Al film are formed to complete the CMOSFET (j).

According to this embodiment, not only can the same effects as the previous invention be obtained, but also as the second MOSFET,
A self-aligned structure is obtained even though the gate electrode is under the semiconductor layer, and higher speed operation is possible due to the reduction in gate stray capacitance.

[Brief explanation of drawings]

FIGS. 1a to 1g are cross-sectional views showing the manufacturing process of an embodiment of the present invention, FIG. 2 is a diagram showing the nitride film mask pattern of FIG. 1e, and FIG.
4A to 4J are cross-sectional views showing the manufacturing process of another embodiment of the present invention. 1...Si substrate, 2...field oxide film, 3...
...gate oxide film, 4...first polysilicon layer,
4 ₁ ... gate electrode, 4 ₂ ... source contact electrode, 4 ₂ ... drain contact electrode, 5 ... silicon oxide film (gate oxide film), 6 ... silicon nitride film (oxidation-resistant mask), 8 ... ...source area,
9...Drain region, 10...Second polysilicon layer, 11...Source region, 12...Drain region, 13...BPSG film, ₁₄₁ to ₁₄₃ ...Al electrode wiring, 21...Concave portion, 22... Impurity-doped oxide film, 23... Resist film.

Claims (1)

[Claims] 1. Forming a first MOSFET in a substrate semiconductor layer,
In the method of stacking a second MOSFET by depositing a semiconductor layer thereon,
The MOSFET formation process consists of forming a field oxide film on the substrate semiconductor layer, selectively forming a gate oxide film in the element formation region of this substrate semiconductor layer, and then forming a first polysilicon film containing impurities on the entire surface. At the same time, the surface of the first polysilicon layer is thermally oxidized by selectively covering the surface of the first polysilicon layer with an oxidation-resistant mask to separate gate electrodes, source, drain, and contact electrodes. forming source and drain regions by diffusing impurities in the second layer;
The MOSFET formation step includes at least the first
A process of partially etching the oxide film between the gate electrode and the source and drain contact electrodes of the MOSFET to form a recess, and then selectively filling the recess with an impurity-containing layer flatly, and then depositing a second polysilicon layer. a source,
1. A method of manufacturing a semiconductor device, comprising the step of forming a drain region. 2. The oxidation-resistant mask is formed by patterning a laminated film of a silicon oxide film obtained by oxidizing the surface of the first polysilicon layer and a silicon nitride film deposited thereon. A method of manufacturing the semiconductor device described above. 3. The step of selectively burying an impurity-containing layer in the recess formed between the gate electrode and the source and drain contact electrodes includes depositing an impurity-doped oxide film over the entire surface and then planarizing the surface with a fluid material film.
2. The method of manufacturing a semiconductor device according to claim 1, wherein the fluid material film and the impurity-doped oxide film are uniformly dry-etched under conditions of equal etching rate. 4. The method of manufacturing a semiconductor device according to claim 1, wherein the second polysilicon layer is recrystallized by annealing. 5. The first MOSFET and the second MOSFET are complementary MOSFETs sharing a gate electrode,
The gate oxide film of the second MOSFET is
This is obtained by oxidizing the surface of the MOSFET electrode, on which the second polysilicon layer is deposited, and self-aligned with the source and drain regions of the second MOSFET by diffusion of impurities from the impurity-containing layer. Claim 1 formed by
A method for manufacturing a semiconductor device according to section 1.