JPH0697437A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To provide a semiconductor device which has suppressed the occurrence of leak current along the oxide film for separation of the elements of a trench gate type of semiconductor device. CONSTITUTION:This is a semiconductor device where a set of diffusion layers 4 of a second conductivity type are provided in the region of the semiconductor substrate 1 of a first conductivity type surrounded by an insulating film 2 for separation of elements, and a part of the section overlapping the gate electrode 9 of this diffusion layer 4 is arranged a certain interval apart from the end of the insulating film 2 for separation of elements. The gate electrode 9 is provided in the gap of the second conductivity of diffusion layer 5 on the diffusion layer 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a MOSFET (insulated gate type field effect transistor) and a method for manufacturing the same.

[0002]

2. Description of the Related Art A MOSFET, which is a basic element of a silicon LSI (large-scale integrated circuit), has been miniaturized in accordance with the basic concept of the proportional reduction law.
For example, in a 4-megabit DRAM (dynamic random access memory), the gate dimension of a semiconductor device is 0.8 μm, but in a 16-megabit DRAM that has begun to be mass-produced, the gate length is 0.5 μm. In the future, there is no doubt that the dimensions of semiconductor elements will be reduced in order to realize high integration in memories and to improve the performance in logic LSI typified by microprocessors.

FIG. 2 is a schematic cross-sectional view of a semiconductor device having a conventional MOSFET. An oxide film (2) for element isolation is grown on the surface of the semiconductor substrate (1), a pair of diffusion layers (4) is formed on the surface of the semiconductor substrate surrounded by the oxide film (2), and between the diffusion layers (4). The flowing current is controlled by the potential of the gate electrode (9) which is in contact with the substrate through the gate oxide film (8). In FIG. 2, 3 is a channel stopper layer formed under the isolation oxide film, 10 is an interlayer insulating film, 11 is a contact hole, and 1 is a contact hole.
2 is a metal wiring.

In order to miniaturize the semiconductor device having such a simple structure and reduce the size of the gate electrode (9), the impurity concentration of the semiconductor substrate (1) is increased according to the proportional reduction rule described above, and the diffusion layer is formed. (4) must be shallow and the gate oxide film (8) must be thin. Increasing the concentration of the semiconductor substrate (1) shortens the width of the depletion layer formed between the diffusion layer (4) and the substrate, and suppresses the interaction between the diffusion layers. Therefore, the size of the gate electrode (9) can be reduced according to the shortened depletion layer width. Making the diffusion layer (4) shallow also has the effect of suppressing the interaction.

In order to continue miniaturization of semiconductor devices in the future, it is unavoidable to follow this guideline, however, various factors for obstructing miniaturization are becoming remarkable. For example, since the gate oxide film (8) has a thinning limit determined by the tunnel leak current, it is difficult to reduce the thickness to 4 nm or less. Also, the shallow junction limit of the diffusion layer (4) is determined by the energy of ion implantation, so it is difficult to set it to 0.05 μm or less. Further, the increase of the substrate concentration causes not only the increase of the threshold voltage of the semiconductor device but also the deterioration of the characteristics such as the increase of the diffusion layer capacitance and the decrease of the breakdown voltage.

Therefore, a new semiconductor device which can be further miniaturized is desired in place of the semiconductor device having such a structure.

It is the semiconductor device shown in FIG. 3 that may solve the above-mentioned problems associated with the miniaturization of the semiconductor device. In this semiconductor device, a part of the diffusion layer (5) is stacked on the semiconductor substrate, a groove is formed in the gap, and the diffusion layer (4) inside the substrate is formed by the gate electrode (9).
The structure is divided. Therefore, the diffusion layer (4)
The interaction between them is suppressed, and compared with the semiconductor device of FIG.
Enables miniaturization. Further, since the stacked diffusion layer (5) is on the substrate, the contact region between the metal wiring (12) and the diffusion layer (5) can be formed on the stacked diffusion layer (5). As a result, the diffusion layer (4) inside the substrate
The area can be reduced, and the diffusion layer capacitance is reduced. Furthermore, since the gate electrode (9) is processed on the relatively thick insulating film (6) that protects the stacked diffusion layer (5), the gate electrode (9) has selectivity with respect to the oxide film unlike the semiconductor device of FIG. A bad metal such as tungsten can be used as the gate electrode. Reducing the resistance of the gate electrode is effective for improving the performance of the semiconductor device.

A technique related to this is disclosed in Japanese Patent Laid-Open No. 63-2.
11762.

[0009]

The groove gate type semiconductor device shown in FIG. 3 has some excellent characteristics as compared with the conventional type semiconductor device shown in FIG. It is likely to be possible. However, since the structure is different from the conventional semiconductor device, there are some problems caused by it. The first is insulation of the stacked diffusion layer (5) and gate electrode (9). Usually, the stacked diffusion layers (5) are polycrystalline silicon containing impurities, and the stacked diffusion layers (5) are stacked when the gate oxide film (8) is formed.
Since the side wall oxide film (7) thicker than the gate oxide film grows on the side wall of, the insulation is performed using this. However, unlike the oxide film formed on the surface of the single crystal silicon, the sidewall oxide film (7) of polycrystalline silicon has a problem that the withstand voltage is small. Although the thickness of the grown oxide film depends on the impurities contained in the polycrystalline silicon, when the gate oxide film (8) is thinned, the sidewall oxide film (7) is formed.
Does not get too thick. Therefore, there is a problem that the breakdown voltage between the gate electrode (9) and the stacked diffusion layer (5) is low and the capacitance is large.

However, this problem can be solved by depositing the sidewall insulating film (7) not by oxidation but by vapor deposition.

The second problem is a leak current along the element isolation oxide film. Heretofore, in the groove gate type semiconductor device disclosed in patents or the like, Japanese Patent Laid-Open No. 63-21176 has been proposed.
As shown in FIG. 2, only one cross section of the gate electrode is shown. However, in this trench gate type semiconductor device, in order to miniaturize, it is necessary to pay attention to the boundary region between the element isolation oxide film (2) and the substrate surface. This is because, as will be described later, in the trench gate type semiconductor device, the diffusion layer (4) is formed in advance on the semiconductor substrate (1) and the stacked diffusion layer (5) is separated at the same time. If the impurities implanted in the substrate remain along the inter-element isolation oxide film, it causes a leak current. Since this phenomenon becomes more remarkable as the size of the gate electrode becomes smaller, it is necessary to have a structure in which impurities do not remain along the isolation oxide film.

An object of the present invention is to provide a trench gate type semiconductor device in which the generation of a leak current along the oxide film for element isolation is suppressed and a manufacturing method thereof.

[0013]

In order to achieve the above object, the semiconductor device of the present invention has a semiconductor substrate region of the first conductivity type surrounded by an insulating film for element isolation, which has a conductivity of the first conductivity type. A pair of diffusion layers of a second conductivity type having different conductivity types are arranged at desired intervals, and a gate electrode is provided on a semiconductor substrate via a gate insulating film in order to control a current flowing between the diffusion layers. And a part of the portion of the diffusion layer which overlaps the gate electrode is arranged at a desired distance from the insulating film for element isolation.

Further, according to the semiconductor device of the present invention, a set of diffusions of the second conductivity type different from the first conductivity type are diffused in the semiconductor substrate region of the first conductivity type surrounded by the insulating film for element isolation. The semiconductor device includes a field effect transistor in which a layer is arranged at a desired interval and a gate electrode is arranged on a semiconductor substrate through a gate insulating film in order to control a current flowing between the pair of diffusion layers. A diffusion layer is arranged at a desired distance from the insulating film for element isolation in the direction perpendicular to the direction of the current flowing through the element.

In these semiconductor devices, it is preferable that a part of the insulating film for element isolation is thinner in the vicinity of the boundary with the semiconductor substrate region of the first conductivity type than in other parts. In addition, it is preferable that a pair of conductive layers of a second conductivity type that form a diffusion layer be provided on the semiconductor substrate, and a gate electrode be provided in a gap between the conductive layers with an insulating film interposed therebetween. Furthermore, it is preferable that the semiconductor substrate between the pair of diffusion layers has a groove having a depth substantially equal to that of the diffusion layers.

In order to explain the present invention, FIG. 1 shows an example of the semiconductor device of the present invention. 1A is a cross-sectional view taken along a direction perpendicular to the gate electrode, and FIG. 1B is a cross-sectional view taken along the gate electrode (9) (a cross-sectional view taken along line aa 'in FIG. 1A). . As shown in FIG. 1B, the diffusion layer (4) is arranged at a certain interval so as not to come into contact with the element isolation oxide film (2). In FIG. 1, 1 is a semiconductor substrate, 3 is a channel stopper layer formed under an element isolation oxide film, 5 is a stacked diffusion layer, 6 is an oxide film covering the upper part of the stacked diffusion layer, and 7 is a stacked layer. A sidewall insulating film of the diffusion layer, 8 is a gate oxide film, 10 is an interlayer insulating film, 11 is a contact hole, and 12 is a metal wiring.

In order to form such a diffusion layer, at the time of ion implantation, a mask for opening a region smaller than the region surrounded by the oxide film for element isolation (2) is used, or for element isolation. When forming the oxide film (2), a method such as forming an oxide film serving as a mask for preventing ion implantation in a self-aligned manner by utilizing a selective oxidation method can be used.

[0018]

As described above, one of the problems of the trench gate type semiconductor device is the leak current along the edge of the oxide film (2) for element isolation shown in the cross section of FIG. 1 (B). This is because the diffusion layer (4) formed in advance on the substrate is a thin region at the end of the oxide film for element isolation and digs under the region, which is not removed during the subsequent substrate etching. There is. Therefore, if a desired gap is provided between the end of the oxide film for element isolation (2) and the diffusion layer (4) as in the present invention, the fear of leak current is eliminated.

[0019]

[Embodiment 1] A first embodiment of the present invention will be described below with reference to FIGS. In this embodiment, a method using an ion implantation mask will be described. Note that cross-sectional views of the semiconductor device show a direction (A) perpendicular to the gate electrode and a direction (B) parallel to the gate electrode in the same step.

First, as shown in FIG. 4, an element isolation oxide film (2) is grown on a semiconductor substrate (1) by a selective oxidation method. First, the surface of the p-type semiconductor substrate (1) is oxidized to grow an oxide film (not shown) of about 5 nm.
A nitride film (not shown) is deposited thereon by a vapor phase epitaxy method and processed into a desired shape. The film thickness of the nitride film is 200 nm. Using this nitride film as a mask, boron, which is an impurity of the same conductivity type as the semiconductor substrate (1), is ion-implanted.
When this semiconductor substrate (1) is oxidized, oxygen does not pass through the nitride film, so that the oxide film for element isolation (2) grows only in the portion not covered with the nitride film. The thickness of the oxide film is 25
0 nm, and below the oxide film for element isolation (2), the impurities contained in the substrate were made thicker in order to improve the element isolation characteristics, that is, boron was added at 10 ¹⁸ / c.
A channel stopper layer (3) containing about m ³ is provided. As a result, the threshold voltage of the parasitic MOS transistor using the inter-element isolation oxide film (2) as a gate oxide film increases, and the formation of the inversion layer that causes a leak current is suppressed. Next, the nitride film is removed using a phosphoric acid solution heated to 180 ° C. Further, the thin oxide film is removed with a hydrofluoric acid solution to clean the surface of the semiconductor substrate (1).

Next, as shown in FIG. 5, a conductive layer to be a stacked diffusion layer is deposited. In this example, first, an amorphous silicon film (5 ′) was deposited by using the vapor phase growth method.
The film thickness is 50 nm. Amorphous silicon is used here in order to obtain a smooth surface when the stacked diffusion layers are separated later. When polycrystalline silicon is used, the unevenness of the polycrystalline silicon surface is transferred to the substrate surface,
The surface becomes rough. In this groove gate type semiconductor device,
In order to use the processed substrate surface as an active area, surface roughness must be prevented. The deposition of this amorphous silicon can be realized simply by lowering the formation temperature. Specifically, polycrystalline silicon is deposited at 620 ° C., and amorphous silicon is deposited at 520 ° C. Impurity ions are implanted in this amorphous silicon film. In this example, phosphorus ions were implanted at 2 × 10 ¹⁵ / cm ² with an energy of 10 kV. Under this condition, the implanted phosphorus remains in the amorphous silicon film (5 ') and does not reach the substrate. Furthermore, a silicide film (5 ″) for reducing the resistance
Deposit. Specifically, tungsten silicide was deposited to a thickness of 80 nm by using a sputtering method. Deposition temperature is 3
Since the temperature is 50 ° C., the amorphous silicon does not crystallize, and the implanted phosphorus ions do not diffuse into the substrate. Then, an oxide film (6) is further deposited on this. The oxide film is also deposited at a low temperature so that the amorphous silicon (5 ′) and the silicide film (5 ″) are not crystallized. The formation temperature is 450.
℃. As for the film thickness, 150 nm was deposited in consideration of the film loss due to etching.

Next, as shown in FIG. 6, the stacked diffusion layer composed of the amorphous silicon (5 ') and the silicide film (5 ") is separated into a source and a drain by using a lithography method. Specifically, after patterning the organic film and using this to process the oxide film (6),
Using the oxide film (6) as a mask, the underlying silicide film (5 ″) and the amorphous silicon film (5 ′) are processed. Since the amorphous silicon film is the same material as the substrate, when processing the silicon film Then, the semiconductor substrate (1) is scraped off by about 20 nm.When this state is seen in the cross section of Fig. 6 (B), all of the stacked layers are removed, and the oxide film for element isolation (2) is left at the end. A step due to substrate etching is observed.

Next, as shown in FIG. 7, a photoresist pattern (101) is formed as a mask for ion implantation so as not to reach the edges of the element isolation oxide film, and through this, a diffusion layer (4) inside the substrate is formed. ) Is carried out to form a). The ion species is arsenic, the implantation energy is 15 kV, and the implantation amount is 1 × 10 ¹⁵ /
It is about cm ² . After the ion implantation, the photoresist pattern (101) is removed and a heat treatment is performed, so that phosphorus implanted in the amorphous silicon film (5 ′) diffuses into the substrate, which is shown in the cross-sectional view of FIG. 7 (A). Such a diffusion layer is formed.

Next, a nitride film is deposited on the entire substrate, and the entire surface is etched using an anisotropic etching method.
8, the nitride film remains only on the side walls of the stacked diffusion layers (amorphous silicon film 5 ′, silicide film 5 ″) to form the side wall insulating film (7). The stacked diffusion layer is insulated by (7) and the oxide film (6) The thickness of the sidewall insulating film (7) is about 100 nm Further, the silicon substrate exposed in this step is etched to form a substrate. A groove is dug in to separate the diffusion layer (4).
The depth of the dug groove is 50 nm. This process is shown in FIG.
In the cross section of (B), the diffusion layer in the substrate is completely removed, and a step is formed at the end of the element isolation oxide film (2).

Next, as shown in FIG. 9, the sidewall of the groove is cleaned to form a gate oxide film (8) by a known thermal oxidation method. The thickness of the oxide film is 5 nm.

Next, as shown in FIG. 10, a gate electrode (9) is deposited, and this is also processed into a pattern of the gate electrode by using a known lithography method. In this embodiment, polycrystalline silicon containing phosphorus is used for the gate electrode, but it is also possible to use tungsten or silicide in order to reduce the resistance. The film thickness is about 100 nm. When the shape of the gate electrode is observed from the cross section of FIG. 10B, it seems that the gate electrode is swollen on the stacked diffusion layer.

Finally, as shown in FIG. 11, an oxide film (10) of about 500 nm is formed as an interlayer insulating film on the entire surface of the substrate.
Is deposited and a contact hole (11) is opened in this to expose the stacked diffusion layer, the gate electrode and the substrate. Finally, the metal wiring (12) mainly made of aluminum is formed to complete the semiconductor device according to the first embodiment of the present invention.

<Embodiment 2> In the method using the ion implantation mask described above, a semiconductor device having a small channel width,
That is, it cannot be used for a semiconductor device in which the interval between the element isolation oxide films (2) seen in the section (B) of each figure is small. This is because a mask needs a margin for alignment. Therefore, a method applicable to a semiconductor device having such a smaller channel width will be described as a second embodiment. For this purpose, a selective oxidation method is used.

First, as shown in FIG. 12, the surface of the semiconductor substrate (1) is oxidized to grow an oxide film (102) having a thickness of about 5 nm. Then, a nitride film (103) is deposited thereon by vapor phase epitaxy and processed into a desired shape as shown in the figure. The film thickness of the nitride film is 200 nm.

When this semiconductor substrate is oxidized, a nitride film (1
03) is impermeable to oxygen, so that only the portion not covered with the nitride film is covered with the oxide film (104) as shown in FIG.
Grows. The thickness of the oxide film was set to 30 nm so as to serve as a mask for the subsequent arsenic ion implantation.

Next, as shown in FIG. 14, a nitride film is deposited on the entire surface of the substrate and is removed by anisotropic etching as described above. Then, the sidewalls are formed only on the side surfaces of the existing nitride film (103). The nitride film (105) remains, and the underlying oxide film (10
Part of 4) is covered.

In this state, boron was ion-implanted at about 1 × 10 ¹³ / cm ² for the channel stopper. Then, when the substrate is oxidized, as shown in FIG. 15, a nitride film (10
3) and the oxide film (2) for element isolation grows on the surface not covered with the side wall nitride film (105). The thickness of the oxide film is 250 nm, and the channel stopper layer (3) is provided as described in the first embodiment.

Next, as shown in FIG. 16, the nitride film is removed. A phosphoric acid solution heated to 180 ° C. was used to remove the nitride film. Further, the oxide film (102) is also removed to clean the surface. As a result, a shape having a thin oxide film region is formed at the end of the element isolation oxide film (2), and this thin oxide film region serves as an ion implantation mask when the diffusion layer is formed.

Next, as shown in FIG. 17, an amorphous silicon film (5 ') containing phosphorus, which is an impurity having a conductivity type different from that of the semiconductor substrate, is formed as a stacked diffusion layer, and then a silicide film (5 "). ) Is further deposited, and an oxide film (6) is further deposited under the same conditions as in Example 1.

As shown in FIG. 18, the stacked diffusion layer is separated into a source region and a drain region. FIG.
In the (B) cross section, the stacked diffusion layers are removed and cannot be seen. Further, a step due to substrate etching can be seen at the end of the oxide film for isolating the substrate and the element.

Next, as shown in FIG. 19, arsenic ions are implanted to form a diffusion layer. At this time, FIG.
(B) As shown in the cross section, oxide film for element isolation (2)
Since the oxide film at the edge of the becomes a mask for ion implantation,
Prevents arsenic from entering the substrate.

Next, as shown in FIG. 20, a sidewall nitride film (7) is formed on the sidewall of the stacked diffusion layer and a groove is formed in the substrate, but before that, the oxide film is etched to form the device. The thin oxide film at the end of the inter-separation oxide film (2) is removed. As a result, two steps are formed as shown in the cross section of FIG. Then, it is possible to prevent the diffusion layer from being formed under the oxide film (2) for element isolation.

Further, as shown in FIGS. 21 and 22, the gate oxide film (8), the gate electrode (9) and the metal wiring (12) are formed in the same manner as in the first embodiment. The semiconductor device of the second embodiment of the present invention is completed.

Example 3 Although Example 2 is an example in which the selective oxidation method is applied, there is a dimensional limit in element isolation by the selective oxidation method. Therefore, in a third embodiment, a method of forming an ion implantation mask of a diffusion layer in a self-aligned manner by using a trench element isolation method that can be miniaturized instead of the selective oxidation method will be described.

First, as shown in FIG. 23, an oxide film (102) is grown on the surface of a semiconductor substrate, and a nitride film (103) is further formed to form them into a desired shape. The film thickness of the nitride film is 200 nm.

Next, as shown in FIG. 24, when an oxide film is deposited and anisotropic whole surface etching is performed, an oxide film (104) is formed on the side wall of the nitride film (103) as shown in the figure. Remain.

This nitride film (103) and oxide film (104)
With the mask as a mask, the semiconductor substrate (1) is dug down, and FIG.
Shape as shown in. The depth of the dug groove is 0.3 μm
It is a degree.

Next, as shown in FIG. 26, the nitride film (1
03) after removing the oxide film (104) covering the side wall,
When the substrate is dug again, a groove having two steps is formed as shown in the figure. The depth of the second groove is about 5
It is 0 nm. Further, the channel stopper layer (3) is formed by using a known oblique ion implantation method. When the oblique ion implantation method is used, it is possible to introduce ions into a plane perpendicular to the substrate. The ionic species is boron.

Next, a thin oxide film (not shown) is grown on the entire surface, and then an oxide film is deposited on the entire surface, and the oxide film is deposited between the trench type elements as shown in FIG. The oxide film (2) for separation is used.

Furthermore, the nitride film (10
3) is removed, and further the oxide film (102) is removed to obtain the shape shown in FIG.

Next, after the surface of the substrate is made as flat as possible, an amorphous silicon film (5 ') containing phosphorus, which is an impurity having a conductivity type different from that of the semiconductor substrate, is used as a stacked diffusion layer.
Then, a silicide film (5 ″) is deposited as shown in FIG.29. Further, an oxide film (6) is deposited.

Then, as shown in FIG. 30, the stacked diffusion layer is separated into a source and a drain.

Further, as shown in FIG. 31, arsenic is ion-implanted in order to form the diffusion layer (4) inside the substrate. At this time, in the trench element isolation, the step portion serves as a mask for ion implantation so that ions are not implanted near the deep element isolation.

Next, as shown in FIG. 32, a side wall insulating film (7) is formed on the stacked diffusion layer, and as shown in FIG. 33, the oxide film at the step portion of the oxide film for element isolation is formed. Are removed to obtain the shape shown in the cross section of FIG. Then, when the substrate is etched, the diffusion layer (4) is separated, and the diffusion layer is not formed at the end of the trench type element isolation oxide film (2). Hereinafter, FIGS. 34 and 35 are the same as those of the first embodiment, and thus the description thereof will be omitted.

<Fourth Embodiment> The present invention has been described so far by taking one conductive type semiconductor device as an example. However, actually, complementary semiconductor devices in which semiconductor devices having different conductivity types are manufactured on the same substrate are used. Fig. 36
Shows an example. The fabrication method is essentially the same as that described above, but starts with forming regions of different conductivity types in the semiconductor substrate. In this embodiment, an n-type substrate region containing phosphorus is formed in the region (1 ′),
A p-type region containing boron is formed in the region (1 ″). Subsequent device formation is the same as that described so far, except that one diffusion layer (4) and the channel stopper layer (3) are formed. ) And the other diffusion layer (4 ′) and channel stopper layer (3 ′) have different conductivity types, it is necessary to cover the other with a mask when introducing impurities into one element.

FIG. 37 is a pattern plan view of the complementary semiconductor device shown in FIG. Using the pattern shown by 30, an n-type region is formed inside this and a p-type region is formed in the other region. Reference numeral 31 is a pattern for forming an oxide film for element isolation, which is used for processing a nitride film which serves as a mask for the selective oxide film. The same pattern is used for both n-type and p-type. Reference numeral 32 is a pattern for forming a stacked diffusion layer. Ions are selectively implanted into the silicon film of the stacked diffusion layer according to the conductivity type. At this time, only one of the ions is exposed by using the pattern 33. Then 34 and 35
This pattern is used to prevent the diffusion layer from being implanted into the edge of the isolation oxide film. 36 is a gate electrode pattern, 37 is a contact pattern, and 38 is a wiring pattern. This plane pattern shows the case of the first embodiment. When the mask is formed in a self-aligning manner as in the second and third embodiments, the patterns (34) and (35) are used.
Is unnecessary.

In the above embodiments, the silicide film is used as the upper layer of the stacked diffusion layer, but it may be tungsten or molybdenum, and silicide of tungsten or molybdenum is used as the silicide.

[0053]

As described above with reference to some embodiments, according to the semiconductor device of the present invention, the oxidation for element isolation, which has been a problem in the conventional trench gate type semiconductor device. The leakage current between the source and the drain along the film could be suppressed. Therefore, it is possible to maximize the excellent capabilities of the trench gate type semiconductor device, such as punch-through resistance and low parasitic capacitance, and it is possible to realize a high-performance and highly integrated LSI. Specifically, by using this groove gate type semiconductor device, a semiconductor device having a gate dimension of 0.1 μm or less could be realized. This is a size equivalent to that of a 1 gigabit class memory. Further, according to the method for manufacturing a semiconductor device of the present invention, such a semiconductor device could be easily manufactured.

[Brief description of drawings]

FIG. 1 is a sectional view of a trench gate type semiconductor device of the present invention.

FIG. 2 is a sectional view of a conventional semiconductor device.

FIG. 3 is a sectional view of a conventional trench gate type semiconductor device.

FIG. 4 is a cross-sectional view of the trench gate type semiconductor device of the first embodiment of the present invention.

FIG. 5 is a cross-sectional view of the trench gate type semiconductor device according to the first embodiment of the present invention.

FIG. 6 is a sectional view of a trench gate type semiconductor device according to a first embodiment of the present invention.

FIG. 7 is a cross-sectional view of the trench gate type semiconductor device according to the first embodiment of the present invention.

FIG. 8 is a cross-sectional view of the trench gate type semiconductor device according to the first embodiment of the present invention.

FIG. 9 is a sectional view of the trench gate type semiconductor device of the first embodiment of the present invention.

FIG. 10 is a sectional view of the trench gate type semiconductor device of the first embodiment of the present invention.

FIG. 11 is a sectional view of the trench gate type semiconductor device of the first embodiment of the present invention.

FIG. 12 is a sectional view of a trench gate type semiconductor device according to a second embodiment of the present invention.

FIG. 13 is a sectional view of a trench gate type semiconductor device according to a second embodiment of the present invention.

FIG. 14 is a sectional view of a trench gate type semiconductor device according to a second embodiment of the present invention.

FIG. 15 is a sectional view of a trench gate type semiconductor device according to a second embodiment of the present invention.

FIG. 16 is a sectional view of a trench gate type semiconductor device according to a second embodiment of the present invention.

FIG. 17 is a sectional view of a trench gate type semiconductor device according to a second embodiment of the present invention.

FIG. 18 is a sectional view of a trench gate type semiconductor device according to a second embodiment of the present invention.

FIG. 19 is a sectional view of a trench gate type semiconductor device according to a second embodiment of the present invention.

FIG. 20 is a sectional view of a trench gate type semiconductor device according to a second embodiment of the present invention.

FIG. 21 is a sectional view of a trench gate type semiconductor device according to a second embodiment of the present invention.

FIG. 22 is a sectional view of a trench gate type semiconductor device according to a second embodiment of the present invention.

FIG. 23 is a sectional view of a trench gate type semiconductor device according to a third embodiment of the present invention.

FIG. 24 is a sectional view of a trench gate type semiconductor device according to a third embodiment of the present invention.

FIG. 25 is a sectional view of a trench gate type semiconductor device according to a third embodiment of the present invention.

FIG. 26 is a sectional view of a trench gate type semiconductor device according to a third embodiment of the present invention.

FIG. 27 is a sectional view of a trench gate type semiconductor device according to a third embodiment of the present invention.

FIG. 28 is a sectional view of a groove gate type semiconductor device according to a third embodiment of the present invention.

FIG. 29 is a sectional view of a trench gate type semiconductor device according to a third embodiment of the present invention.

FIG. 30 is a sectional view of a trench gate type semiconductor device according to a third embodiment of the present invention.

FIG. 31 is a sectional view of a trench gate type semiconductor device according to a third embodiment of the present invention.

FIG. 32 is a sectional view of a trench gate type semiconductor device according to a third embodiment of the present invention.

FIG. 33 is a sectional view of a trench gate type semiconductor device according to a third embodiment of the present invention.

FIG. 34 is a sectional view of a trench gate type semiconductor device according to a third embodiment of the present invention.

FIG. 35 is a sectional view of a trench gate type semiconductor device according to a third embodiment of the present invention.

FIG. 36 is a sectional view of a complementary semiconductor device using a groove gate type semiconductor element according to the fourth embodiment of the present invention.

FIG. 37 is a plan view of a complementary semiconductor device using the trench gate type semiconductor element according to the fourth embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate 1 ', 1 "... Region 2 ... Oxide film for element isolation 3, 3' ... Channel stopper layer 4, 4 ', 5 ... Diffusion layer 5' ... Amorphous silicon film 5" ... Silicide film 6 , 102, 104 ... Oxide film 7 ... Side wall insulating film 8 ... Gate oxide film 9 ... Gate electrode 10 ... Interlayer insulating film 11 ... Contact hole 12 ... Metal wiring 101 ... Photoresist pattern 103 ... Nitride film 105 ... Sidewall nitride film 30 ... Pattern (For forming n-type region) 31 ... Pattern (for forming oxide film for element isolation) 32 ... Pattern (for forming stacked diffusion layer) 33, 34, 35 ... Pattern (for ion implantation) 36 ... Gate electrode pattern 37 ... Contact Pattern 38 ... Wiring pattern

Claims (16)

[Claims] 1. A set of diffusion layers of a second conductivity type having a conductivity type different from that of the first conductivity type are formed at desired intervals in a semiconductor substrate region of the first conductivity type surrounded by an insulating film for element isolation. For controlling a current flowing between the pair of diffusion layers,
In a semiconductor device having a field-effect transistor in which a gate electrode is disposed on a semiconductor substrate via a gate insulating film, a part of a portion of the diffusion layer that overlaps with the gate electrode is a part of the insulating film for element isolation that is desired. A semiconductor device characterized in that the semiconductor devices are arranged at intervals. 2. A set of diffusion layers of a second conductivity type having a conductivity type different from that of the first conductivity type are formed at desired intervals in a semiconductor substrate region of the first conductivity type surrounded by an insulating film for element isolation. For controlling a current flowing between the pair of diffusion layers,
In a semiconductor device having a field effect transistor in which a gate electrode is disposed on a semiconductor substrate with a gate insulating film interposed therebetween, the diffusion layer has a structure for separating the elements in a direction perpendicular to a direction of a current flowing between the diffusion layers. A semiconductor device, wherein the semiconductor device is arranged at a desired distance from an insulating film. 3. The semiconductor device according to claim 1, wherein a part of the insulating film for element isolation is thinner in the vicinity of the boundary with the semiconductor substrate region of the first conductivity type than in other parts. Semiconductor device. 4. The semiconductor device according to claim 1, wherein a set of conductive layers of a second conductivity type forming a diffusion layer are provided on the semiconductor substrate, A semiconductor device, wherein the gate electrode is provided in a gap via an insulating film. 5. The semiconductor device according to claim 1, wherein the conductive layer is a laminated film of a silicon film and a low resistance material film. 6. The semiconductor device according to claim 1, wherein the low resistance material film is tungsten.
A semiconductor device comprising molybdenum or a silicide of these metals. 7. The semiconductor device according to claim 1, wherein the semiconductor substrate between the pair of diffusion layers has a groove having a depth substantially equal to that of the diffusion layers. Semiconductor device. 8. A semiconductor substrate is provided with a first region of a first conductivity type and a second region of a second conductivity type having a conductivity type different from that of the first conductivity type, and the first and second regions. Are each surrounded by an element isolation insulating film, and a pair of diffusion layers of the second conductivity type are provided in the first region at desired intervals to control the current flowing between the pair of diffusion layers. , A gate electrode is provided on the semiconductor substrate via a gate insulating film to form a first field effect transistor, and a set of diffusion layers of the first conductivity type are provided in the second region at desired intervals. And a gate electrode is provided on the semiconductor substrate through a gate insulating film in order to control a current flowing between the pair of diffusion layers to form a second field effect transistor. One diffusion layer of the field effect transistor and the other diffusion layer are electrically connected, and In the semiconductor device in which the respective gate electrodes are electrically connected, a part of the portion of each of the diffusion layers which overlaps with the gate electrode is arranged at a desired distance from the element isolation insulating film. A semiconductor device characterized by the above. 9. A semiconductor substrate is provided with a first region of a first conductivity type and a second region of a second conductivity type having a conductivity type different from that of the first conductivity type, and the first and second regions. Are each surrounded by an element isolation insulating film, and a pair of diffusion layers of the second conductivity type are provided in the first region at desired intervals to control the current flowing between the pair of diffusion layers. , A gate electrode is provided on the semiconductor substrate via a gate insulating film to form a first field effect transistor, and a set of diffusion layers of the first conductivity type are provided in the second region at desired intervals. And a gate electrode is provided on the semiconductor substrate through a gate insulating film in order to control a current flowing between the pair of diffusion layers to form a second field effect transistor. One diffusion layer of the field effect transistor and the other diffusion layer are electrically connected, and In the semiconductor device in which the respective gate electrodes are electrically connected, the diffusion layers in the first and second regions are isolated from each other in the direction perpendicular to the direction of the current flowing between the diffusion layers by the isolation insulation between elements. A semiconductor device, wherein the semiconductor device is arranged at a desired distance from the film. 10. The semiconductor device according to claim 8 or 9, wherein a pair of conductive layers having the same conductivity type as that of the diffusion layer is provided on the first and second regions, respectively. A semiconductor device, wherein the gate electrode is provided in each of the gaps via an insulating film. 11. A step of forming an element isolation insulating film surrounding a desired region of a surface of a semiconductor substrate of the first conductivity type, and a step of forming a desired direction from the element isolation insulating film in a predetermined direction. A second conductive layer having a conductivity type different from that of the first conductivity type.
3. The method according to claim 1, further comprising a step of forming a conductive type diffusion layer.
A method of manufacturing a semiconductor device, which comprises manufacturing the semiconductor device described above. 12. A first step of growing a first oxide film on a surface of a first conductivity type semiconductor substrate, and a second step of depositing a nitride film on the surface of the first oxide film and processing it into a desired shape. Process of
Using the nitride film as a mask, a third step of implanting impurities of the same conductivity type as the semiconductor substrate, a fourth step of growing a second oxide film on the surface of the semiconductor substrate, and a fifth step of removing the nitride film. A sixth step of removing the first oxide film, and depositing a stacked film of a silicon film containing an impurity having a conductivity type different from that of the semiconductor substrate, a silicide film or a metal film, and an oxide film on the surface of the semiconductor substrate. 7th step, 8th step of separating the laminated film, 9th step of forming an organic film that opens inside the semiconductor substrate region surrounded by the second oxide film, and the semiconductor substrate is of a conductive type. Implanting different impurities of
Tenth step of forming a diffusion layer, eleventh step of removing the organic film, twelfth step of forming a side wall insulating film only on the side wall of the separated laminated film, and forming a groove on the exposed surface of the semiconductor substrate. Then, the method has a thirteenth step of separating the diffusion layer, a fourteenth step of forming an insulating film on the surface of the groove, and a fifteenth step of forming a gate electrode on at least the insulating film. Manufacturing method of semiconductor device. 13. A step of forming an insulating film for element isolation, which surrounds a desired region on the surface of a semiconductor substrate of the first conductivity type and has a vicinity of a boundary with the desired region thinner than other portions. A step of forming a diffusion layer of a second conductivity type having a conductivity type different from the first conductivity type in the region, and removing a thin portion of the insulating film for element isolation arranged in a predetermined direction of the desired region,
3. A method of manufacturing a semiconductor device, comprising the step of forming a gap between an element isolation insulating film and the diffusion layer, wherein the semiconductor device according to claim 1 or 2 is produced. 14. A first step of growing a first oxide film on a surface of a semiconductor substrate of a first conductivity type, depositing a first nitride film on the surface of the first oxide film, and processing it into a desired shape. A second step of performing a third step of growing a second oxide film on the surface of the semiconductor substrate
The step of depositing a second nitride film on the surface of the semiconductor substrate,
Step, the fifth step of leaving the second nitride film only on the side wall of the first nitride film, and using the first and second nitride films as a mask, impurities of the same conductivity type as the semiconductor substrate are used. A sixth step of implanting, a seventh step of growing a third oxide film on the surface of the semiconductor substrate, an eighth step of removing the first and second nitride films, a eighth step of removing the first oxide film 9 steps,
A tenth step of depositing a laminated film of a silicon film containing an impurity having a conductivity type different from that of the semiconductor substrate, a silicide film or a metal film, and an oxide film on the surface of the semiconductor substrate, and an eleventh step of separating the laminated film. A twelfth step of implanting an impurity having a conductivity type different from that of the semiconductor substrate to form a diffusion layer on the surface of the semiconductor substrate exposed by the separation of the laminated film; forming an insulating film only on the side wall of the laminated film; 13th step of removing only the oxide film, a 14th step of forming a groove on the exposed surface of the semiconductor substrate and separating the diffusion layer, a 15th step of forming a gate insulating film on the surface of the groove, and A method of manufacturing a semiconductor device, comprising a sixteenth step of forming a gate electrode. 15. A step of forming a film of a first material having etching resistance on a desired region of a surface of a semiconductor substrate of the first conductivity type, wherein a side wall of the film of the first material has etching resistance. A step of forming a film of the second material, a step of forming a first recess in the semiconductor substrate using the films of the first and second materials as a mask, a step of removing the film of the second material, Using the film of the first material as a mask, the step of forming second recesses of a desired depth in the semiconductor substrate again, the first and second steps described above.
Of the insulating film for element isolation in the concave portion of, the step of forming a diffusion layer of a second conductivity type having a conductivity type different from the first conductivity type at a desired position in the desired region, and A second insulating film for separating the elements, which is arranged in a predetermined direction;
3. The semiconductor device according to claim 1 or 2, further comprising the step of removing only the depth of the recessed portion and forming a gap between the insulating film for element isolation at that portion and the diffusion layer. And a method for manufacturing a semiconductor device. 16. A first step of growing a first oxide film on a surface of a first conductivity type semiconductor substrate, and a second step of depositing a nitride film on the surface of the first oxide film and processing it into a desired shape. Process of
A third step of forming a second oxide film only on the side wall of the nitride film, a fourth step of forming a first recess by digging a semiconductor substrate using the nitride film and the second oxide film as a mask. Step, fifth step of removing only the second oxide film, sixth step of digging the semiconductor substrate again with the nitride film as a mask to form a second recess having a predetermined depth, and first step And a seventh step of forming an impurity layer of the same conductivity type as that of the semiconductor substrate on the side wall and bottom of the second recess, an eighth step of depositing a third oxide film filling the first and second recesses, A ninth step of flattening the third oxide film on the substrate surface by flattening it, a tenth step of removing the nitride film, an eleventh step of removing the first oxide film, and a semiconductor substrate surface. A silicon film containing impurities having a conductivity type different from that of the semiconductor substrate, a silicide film or a metal film, and an oxide film. Twelfth step of depositing a multilayer film,
Thirteenth step of separating the laminated film, fourteenth step of forming a diffusion layer by implanting an impurity having a conductivity type different from that of the semiconductor substrate on the surface of the semiconductor substrate exposed by the separation of the laminated film, the sidewall of the laminated film Forming a sidewall insulating film only on the first oxide film and removing the third oxide film by the depth of the second recess.
5th step, 16th step of forming a groove on the exposed semiconductor substrate surface to separate the diffusion layer, 17th step of forming an insulating film on the surface of the groove and 18th step of forming a gate electrode
A method of manufacturing a semiconductor device, comprising: