JPS6159543B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an insulated gate field effect transistor (hereinafter abbreviated as IGFET), and particularly to a dual gate IGFET.

Dual-gate IGFETs are often used in frequency conversion circuits and modulation circuits that handle intermediate frequency signals in radio receivers, etc., and their structure is shown in FIG. In the figure, for example, an N-type source and drain region 2 is formed on a P-type semiconductor substrate 1.
and 4 are formed, an N-type island region 3 is provided in the middle thereof, and a first gate electrode G ₁ is formed on the channel region between the source region and the island region with a gate insulating film 5 interposed therebetween. has been done. Further, a second gate electrode G ₂ is also formed on the channel region between the drain region and the island region with the gate insulating film 6 interposed therebetween.

In such a structure, the channel length of the first IGFET, which defines the limit of high-frequency operation, is shortened, and the channel length of the second IGFET is lengthened to prevent a drop in breakdown voltage due to punch-through.

However, with such a planar structure, it is difficult to control the channel length, and there is a limit to the short channel.Furthermore, increasing the so-called gm of a transistor requires a large area, resulting in a decrease in yield. bring.

The purpose of the present invention is to develop a dual-gate IGFET that is easy to short channel, has a large gm without requiring a large area, and has a high drain breakdown voltage.
The goal is to provide the following.

The present invention will be explained below with reference to the drawings.

Figures 2 to 7 are cross-sectional views in the order of manufacturing steps of a device according to an embodiment of the present invention, and are shown in the case of an N-channel type IGFET, but the same can be applied to a P-channel type IGFET. That is clear.

First, as shown in FIG. 2, an N-type semiconductor substrate 10 is prepared, and a P-type layer 11,
The N-type layer 12, the P-type layer 13, and the N-type layer 14 are formed in this order by epitaxial growth or the like.
At this time, an N-type impurity such as phosphorus is diffused into the N-type layers 12 and 14 at a high concentration.

Next, as shown in FIG.
Anisotropic etching is performed to form, for example, V-shaped recesses 15 and 16, which extend through the substrate 14 and reach the substrate 10, respectively. Thereafter, an oxide film 17 serving as a diffusion mask is formed on the entire surface, and the oxide film on the surface of one of the recesses 16 is selectively etched away, and boron diffusion is performed, for example, as shown in FIG. The structure connects the P-type epitaxial semiconductor layers 11 and 12, which were separated from each other, to function as a channel stopper. Thereafter, the oxide film 17 serving as a diffusion mask is removed to obtain the structure shown in FIG.

Next, a dual gate structure is created in the other recess 15, but one of the manufacturing steps in this case is
Examples are shown in Figures 6A-E. First, oxide film 1 is applied to the entire surface.
8 is formed, the oxide film only on the surface of the V-shaped recess 15 is selectively removed, and a gate insulating film 19 is formed on the surface of the recess 15. Then, in step A, polysilicon (polycrystalline silicon) 20 is formed in the V-shaped recess, leaving only the portion that will become the first gate and removing the rest.

An oxide film is again provided on the V-shaped recess, an opening is made in the oxide film in the part to be connected to the previously formed polysilicon 20, and then polysilicon is formed again. Since this will be connected to silicon 20, this connecting part of the upper polysilicon layer will be left and the other parts will be removed, and then an oxide film will be formed. Then, in order to form a second gate, the oxide film covering the surface of the N-type layer 13 is removed and a gate insulating film 21 is deposited thereon.

After that, polysilicon 22 is again formed on the entire surface, and an opening for connecting the polysilicon 20 for the first gate is bored in the polysilicon 22,
An oxide film 23 is provided on the entire surface, and a polysilicon 24 is formed, except for the oxide film in the opening, to form a polysilicon 24 that will become an electrode wiring layer for leading out the gate of the polysilicon 20 in the lower layer. This upper polysilicon layer 24 is selectively etched to form first and second gate electrode structures as shown in E.

Then, as shown in FIG. 7, the uppermost N-type layer 1
4 to the source electrode S from polysilicon 20 to the first
The gate electrode G ₁ is taken out from the polysilicon 22, the second gate electrode G ₂ is taken out from the N-type substrate 10, and the drain electrode is taken out from the N-type substrate 10 to form a dual gate type.
It becomes an IGFET.

Note that the recess 16 serves as a channel stopper area.
The channel stopper function can be made more effective by taking out the electrode 25 from the highly-concentrated P-type region on the surface (see FIG. 5) and setting it at the lowest potential of the circuit, for example, zero potential.

FIGS. 8 to 11 are cross-sectional views of the manufacturing process order for obtaining a device according to another embodiment of the present invention, and similarly, the case of an N-channel type IGFET will be explained, but the invention is not limited thereto. Of course.

First, as shown in FIG. 8, an N-type semiconductor substrate 10 is
A P-type epitaxial semiconductor layer 11 is formed on one main surface of the substrate, and an N-type high concentration impurity region 12 is selectively diffused and formed on this one main surface. By growing the P-type epitaxial semiconductor layer 13 again on this main surface, the N-type region 12 is used as a buried layer, and the N-type high concentration impurity region 14 is diffused in one main surface of this epitaxial layer 13. Form.

After that, as shown in FIG.
A V-shaped recess 15 is formed by anisotropic etching, penetrating the P-type epitaxial layers 11, 13 and reaching the substrate 10. And Figure 6 A~
A dual gate structure can be obtained using the method according to E, and finally an IGFET device as shown in FIG. 11 can be obtained.

In each of the above embodiments, the concave portion is V-shaped, but the concave portion is not limited to this and may have various shapes.

As described above, according to the structure of the present invention, the channel length is determined by the width of the epitaxial growth layer and the diffusion depth of the N-type impurity, so it is extremely easy to control it, and A short channel can be realized by reducing the width. In addition, since the channel surface is formed along the concave surface, the chip area can be increased without increasing the chip area.
GM has been achieved, and yield decline can be significantly suppressed.

Furthermore, since it has a vertical structure, the drain current flows through the substrate, which has the advantage that the drain breakdown voltage can be increased.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a conventional dual-gate IGFET, FIGS. 2 to 7 are sectional views of a device according to one embodiment of the present invention in the order of manufacturing steps, and FIGS. 8 to 11 are sectional views of another embodiment of the present invention. FIG. 3 is a cross-sectional view of the example device in the order of manufacturing steps. Explanation of symbols of main parts 10...Semiconductor substrate, 1
1, 13... P-type semiconductor layer, 12, 14... N-type semiconductor layer, 19, 21... gate insulating film, 20, 22...
gate electrode.

Claims (1)

[Claims] 1 a first conductivity type semiconductor substrate; a second conductivity type first semiconductor layer formed on the semiconductor substrate;
a first semiconductor region of the first conductivity type formed on the first semiconductor layer; a second semiconductor layer of the second conductivity type formed on the first semiconductor region; the first semiconductor layer formed on the second semiconductor layer;
a second semiconductor region of a conductive type, a recess penetrating through the first and second semiconductor layers, and further through all of the first and second semiconductor regions and reaching the semiconductor substrate; The first and second semiconductor layers are deposited through a gate insulating film provided to cover the exposed surfaces of the first and second semiconductor layers, respectively.
an insulated gate field effect transistor, wherein the semiconductor substrate and the second semiconductor region serve as a drain and a source region, respectively.