JPS63131584A - Manufacture of cut type insulated-gate electrostatic induction transistor - Google Patents

Abstract

PURPOSE:To improve reproducibility and reliability by leaving a gate electrode only onto the side wall of a U-shaped trench in a self-alignment manner and forming a drain region and a source region in the self-alignment manner, using the gate electrode as a mask material. CONSTITUTION:An epitaxial layer 12 as a channel is grown onto a substrate 11 and a channel impurity is introduced, and a U-shaped trench is shaped. A field oxide film 13 is formed through a selective oxidation method while a window is bored to an element region and a gate oxide film 14 is shaped. A polycrystalline semiconductor 15 as a gate electrode is deposited and the gate electrode is formed only onto the side wall of the U-shaped trench in a self- alignment manner, and a drain region 16 and a source region 17 are shaped, using the gate electrode 15 as a mask. A passivation film 18 is deposited, contact holes are bored and a drain electrode 16' and a source electrode 17' are formed. Accordingly, the gate oxide film and the gate electrode can be shaped only onto the side wall of the U-shaped trench in the self-alignment manner, thus improving reproducibility and reliability.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) This invention relates to a notched insulated gate static induction transistor capable of high-speed switching and a method for manufacturing a notched insulated gate static induction transistor integrated circuit with high speed and low power consumption. Regarding.

(Prior Art) Insulated gate transistors have been used for high frequency amplification and integrated circuits, but they have the drawback of low driving capability. Currently, as a means of overcoming the drawbacks of such insulated gate transistors and increasing their speed, shortening the channel is being actively promoted. Gansho 5
2-1756) and a notched insulated gate static induction transistor (for example, Japanese Patent Application No. 13707/1982) have been proposed.

Insulated gate static induction transistors are designed so that the effect of the drain electric field extends to the source, and because current flows not only at the semiconductor/insulating film interface but also through the substrate, it has unsaturated current-voltage characteristics, making it difficult to drive. It has characteristics such as great ability. In particular, in the notched insulated gate static induction transistor, since the channel is formed in the depth direction of the semiconductor substrate, the channel length and gate length can be easily controlled, and it is suitable for shortening the channel. Therefore, the driving capacity can be increased.

Additionally, because parasitic capacitance can be reduced, it exhibits superior performance as a high-speed transistor or a high-speed, low-power integrated circuit.

An example of a known manufacturing process for this notched insulated gate static induction transistor will be described with reference to No. 4-.

FIG. 4(a) After growing an epitaxial layer 42 to become a channel on a semiconductor substrate 41 used as a drain and introducing channel impurities by thermal diffusion or ion implantation, an anisotropic plasma is applied to a part of the main surface of the semiconductor substrate. A U-shaped groove is formed by etching or the like.

FIG. 4(b) Using ordinary photolithography technology and selective oxidation, a field oxide film 43 is formed, and a window is opened in a part of the main surface of the semiconductor substrate and a part of the side wall of the U-shaped trench. A gate oxide film 44 is formed.

FIG. 4(c) After depositing a polycrystalline semiconductor 45 that will become the gate electrode and etching it so that it remains on the gate oxide film on the sidewalls of the U-shaped trench using normal photolithography, the source region is formed by thermal diffusion or ion implantation. form 46.

FIG. 4(d) A passivation film 47 is deposited and a contact hole is opened to form a drain electrode 41' and a gate electrode 4.
5', and a source electrode 46' are formed.

The impurity density of the drain region 41 and the source region 46 is about 1018 to 10"CM-' respectively.Of course, the conductivity type may be P type or N type, and contrary to the above description, the impurity density is about 1018 to 10"CM-'.
1 may be a source region and 46 may be a drain region. The impurity density of the channel region 42 is 1012 to 10" am-
The conductivity type may be the same as or opposite to the drain region and the source region, and the conductivity type may be the same as that of the drain region and the source region, and the conductivity type may be a multilayer structure.
The depletion layer extending from the drain region must reach the source region, and the impurity density is determined together with the depth of the U-shaped trench to satisfy this requirement.

Further, the thickness of the gate oxide film 44 is set to about 100 to 10,000 mm, and polycrystalline silicon or the like is normally used for the gate electrode, and is set to about 1000 to 1 μm. The conventional notch-type insulated gate static induction transistor shown in this figure is originally formed in the depth direction of the semiconductor substrate, so the dimensions of the transistor can be controlled by the precision of the film formation, and short channel high-speed Very suitable for transistors.

(Problems to be Solved by the Invention) However, in the conventional manufacturing method of a notch type insulated gate static induction transistor, 1. Since normal photolithography technology is used, a margin for mask alignment is required. Gate electrode 4
5 was difficult to form only on the side wall of the U-shaped groove.

For example, FIG. 5 shows an example of the planar structure of a conventional notched insulated gate static induction transistor corresponding to the manufacturing process shown in FIG. , 53 is a gate electrode of a polycrystalline semiconductor, and 5
4 and 55 are a drain contact hole and a gate contact hole, respectively, and 56 and 57 are a drain electrode and a gate electrode, respectively. The BB' cross section in the same figure is the fourth
It is shown in figure (d). lb and lc in the same figure are the fourth
This is the mask alignment margin for photolithography in steps (b) and (C) in the figure, and is usually set to about 0.1 to 2 μm.

Examples of drain current-drain voltage characteristics of transistors with different mask alignment margins lc are shown in FIGS. 6(a) to (C). In this case, the channel length is approximately 0.5 μm, and the channel impurity dose is approximately 1.5×. 10"cm-", gate oxide film thickness is approximately 250cm, and mask alignment margin lc
However, (a) is 0 μm, (b) and (c) are each 1 μm,
It is 2 μm. The case shown in FIG. 3A exhibits unsaturated current-voltage characteristics, has a large driving capability, and exhibits the characteristics of a notched insulated gate static induction transistor well, but has the drawback of poor yield. On the other hand, the same figures (b) and (c
), the portion corresponding to the mask alignment margin operates in the same way as a planar transistor, so the effective channel length becomes longer and the driving capability deteriorates.

An object of the present invention is to eliminate the drawbacks of the above-mentioned method for manufacturing a notched insulated gate static induction transistor, to form a gate oxide film and a gate electrode in a self-aligned manner only on the side walls of a U-shaped trench, and to improve reproducibility and reliability. The present invention aims to provide a method for manufacturing a notched insulated gate static induction transistor with improved properties.

(Means for Solving the Problem) In the notched insulated gate static induction transistor and the method for manufacturing its integrated circuit of the present invention, anisotropic etching is performed to form a U-shaped groove on one main surface of a semiconductor substrate. a step of forming a gate oxide film; and a step of leaving a gate electrode in a self-aligned manner only on the sidewalls of the U-shaped trench;
The method is characterized by comprising a step of forming a drain region and a source region in a self-aligned manner using the gate electrode as a mask material.

As a result, the gate oxide film and the gate electrode, as well as the source region and the drain region, can be formed without being affected by variations in the mask alignment process or the like.

(Example) The present invention will be explained in detail below with reference to Examples.

FIG. 1 shows an example of the manufacturing process of the notched insulated gate electrostatic induction according to the present invention.

FIG. 1(a) After growing an epitaxial layer 12 that will become a channel on a semiconductor substrate 11 and introducing channel impurities by thermal diffusion or ion implantation, a part of the main surface of the semiconductor substrate is etched with U by anisotropic plasma etching or the like. Forms a letter-shaped groove.

(b) Using a selective oxidation method, a field oxide film 13 is formed, and a window is opened in the element region on the main surface of the semiconductor substrate to form a gate oxide film 14.

Figure (Q) After depositing the polycrystalline semiconductor 15 that will become the gate electrode and forming the gate electrode in a self-aligned manner only on the side walls of the U-shaped trench by anisotropic plasma etching, etc., heat is applied using the gate electrode 15 as a mask. A drain region 16 and a source region 17 are formed by diffusion or ion implantation.

(d) A passivation film 18 is deposited, a contact hole is opened, and a drain electrode 16' and a source electrode 17' are formed.

At this time, the drain region 16. The impurity density of the source regions 17 is about 101a to 10"am-", respectively.

Of course, the conductivity type may be P type or N type.

16 may be a source region and 17 may be a drain region.

The impurity density of the channel region 12 is 1012 to 10"am
-', and its conductivity type is the drain region 16
and may be the same as or opposite to the source region 17,
It may have a multilayer structure.

However, at least in a part of the active region, the impurity density is determined together with the depth of the U-shaped trench so that the depletion layer extending from the drain region reaches the source region. Further, the film thickness of the gate oxide film 14 is 100 to 1,0
The thickness of the gate electrode is about 00A, and the thickness of the gate electrode is l.

The thickness is set to about 0.008 to 1 μm. For example, it is very effective to use polycrystalline silicon as the gate electrode, and P
Anisotropic etching can be performed by Cl3 plasma etching.

According to this manufacturing process, the gate oxide film and gate electrode, which have the most influence on the characteristics of the device, can be formed in a self-aligned manner only on the side walls of the U-shaped groove, resulting in high reproducibility.

It is possible to obtain a notched insulated gate static induction transistor with high reliability and device characteristics as shown in FIG. 6(,).

FIG. 2 shows an example of a planar structure of a notched insulated gate static induction transistor corresponding to the manufacturing process shown in FIG. In the figure, 21 is a side wall of a U-shaped trench, 22 is a window formed by selective oxidation that becomes an element region, 23 is a polycrystalline semiconductor gate oxide film, and 2
4. 25 and 26 are drain contact holes, respectively;
They are a source contact hole and a gate contact hole, and 24', 25' and 26' are a drain electrode, a source electrode and a gate electrode, respectively. AA' in the same figure
A cross section is shown in FIG. 1(d). All element areas are U
Since the groove is formed in a self-aligned manner with respect to the sidewall of the groove, a notched insulated gate static induction transistor can be manufactured with good reproducibility.

FIG. 3 shows an example of the cross-sectional structure of one gate when this notched insulated gate static induction transistor is applied to a complementary insulated gate integrated circuit. 30 in the figure is a semiconductor substrate, and a U-shaped groove is provided in a part of its main surface. Further, 31 is an N0 drain region, 32 is a P1 drain region, 33 is an N+ source region, and 34 is a P1 source region, each having an impurity density of about 101a to 1021021a.

35 is a P channel region, and 36 is an N channel region, each having an impurity density of about 1012 to 10"an-',
The impurity density is determined together with the depth of the U-shaped groove so that a depletion layer extending from the drain region reaches the source region in at least a part of the active region. 37 is a gate insulating film such as an oxide film, and 100 to 10
It has a film thickness of about 00A, 37' is a gate electrode, and 38 is a field oxide film. Also, 39 is the P channel and N
This is an N-type buried layer for separating channels. Gate electrode 37' is a logic input, drain electrodes 31' and 32' are logic outputs, and a power supply voltage is applied between source electrodes 33' and 34'.

Such integrated circuits can be manufactured using almost the same manufacturing process as shown in Figure 1, except for the structure on the substrate side, and can be used to create complementary insulated gate integrated circuits that are reproducible, reliable, high speed, and have low power consumption. can be provided. For example, in the complementary insulated gate integrated circuit ring oscillator shown in FIG.
The propagation delay time of ssc was obtained when the power consumption was 6.8 mW.

(Effects of the Invention) As described above, according to the present invention, the drawbacks of the manufacturing process of the conventional notch type insulated gate static induction transistor are improved, and the gate oxide film is formed in a self-aligned manner only on the sidewalls of the U-shaped trench. Therefore, it is possible to form notch-type insulated-gate static induction transistors that can perform high-speed switching and cut-off type insulated-gate static induction transistors that can perform high-speed switching and low IQ power consumption with high reproducibility and reliability. It can be easily produced and its industrial value is extremely large.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of a manufacturing process showing one embodiment of a method for manufacturing a notched insulated gate static induction transistor of the present invention, and FIG. 2 shows a planar structure of the notched insulated gate static induction transistor of the present invention. 3 is a plan view, FIG. 3 is a sectional view showing an embodiment of the notched insulated gate static induction transistor integrated circuit of the present invention, and FIG. 4 is an example of a method for manufacturing a conventional notched insulated gate static induction transistor. 5 is a plan view showing the planar structure of the notched insulated gate static induction transistor, and FIG. 6 is a diagram showing the drain current-drain voltage characteristics of the conventional notched insulated gate static induction transistor. FIG. 3 is a characteristic diagram showing an example. 11.3o, 41: Semiconductor substrate 12.35.36.42: Channel region 13.38.4
3: Field oxide film 14.37.44: Gate insulating film 15.23.45.53: Gate electrode 16.31.32.41 Nidrain region 16', 24
', 41', 56 Nidorain electrode 17.33.3
4.46: Source regions 17', 25', 46': Source electrodes 18.4
7: Passivation film 21. 51: U-shaped groove side wall 22. 52: Element area window 39: Separation layer Applicant's agent Patent attorney Fumio Sato Figure 1 7
II Evening
ll 2:2

II Ri=e, 1 fig.

Claims (1)

[Claims] 1) An anisotropic etching step for forming a U-shaped groove on one main surface of the semiconductor substrate, a step of forming a gate oxide film, and an etching step for forming a U-shaped groove only on the side walls of the U-shaped groove. A method for manufacturing a notch type insulated gate static induction transistor 2) characterized by comprising a step of leaving a gate electrode in an aligned manner, and a step of forming a drain region and a source region in a self-aligned manner using the gate electrode as a mask material. Claims characterized in that the method includes a step of using polycrystalline silicon as the gate electrode material and forming the polycrystalline silicon on the sidewalls of the U-shaped groove in a self-aligned manner by PCl_3 anisotropic plasma etching. 3) A method for manufacturing a notched insulated gate static induction transistor according to claim 1, wherein a large number of notched insulated gate static induction transistors are integrally formed on a semiconductor substrate by the method described above. A method for manufacturing an integrated circuit of a notched insulated gate static induction transistor according to item 1 or 2.