JPH02226772A - Infeed type insulated gate electrostatic induction transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To shorten switching time by forming a low resistance electrode composed of high melting point metal or high melting point metal silicide on the polycrystalline Si side surface of a gate electrode. CONSTITUTION:On a main surface of an Si substrate 10, an U-shaped trench 10' is formed, and a polycrystalline Si gate electrode 12 being a control electrode is formed on the side surface of the trench 10', via a thin gate insulating film 11. Further, on at least a part of the side wall of the electrode 21, a low resistance electrode 13 composed of high melting point metal or high melting point metal silicide is formed. On a main surface and a region 14 in contact with the bottom part of the trench 10', a drain region and a base region are formed, respectively. The gate series resistance of an infeed type electrostatic induction transistor having the electrode 13 can be reduced as mentioned above, so that the switching time can be shortened.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention provides an improved structure of a notched insulated gate static induction transistor that can perform high-speed switching and can be applied to high-speed, low-power consumption integrated circuits, and a method for manufacturing the same. Regarding.

(Prior art) Insulated gate field effect transistors have traditionally been used in high-frequency amplifiers and integrated circuits, but they have the disadvantage of low drive capability because the current path is limited to the vicinity of the semiconductor/insulating film interface. was. As a means of overcoming the drawbacks of such insulated gate field effect transistors and increasing their speed, current efforts are being made to shorten the channels, but this is not sufficient. Therefore, one of the inventors of the present invention proposed an insulated gate electrostatic induction transistor (for example, Japanese Patent Application No. 1756/1983) that exhibits excellent performance as a high-speed switching device or a device for high-speed, low-power consumption integrated circuits. In addition, a notch type insulated gate static induction transistor (for example, Japanese Patent Application No. 13707/1982) has been proposed.

Insulated gate static induction transistors are designed so that the effect of the drain electric field extends to the source, and current flows not only near the semiconductor/insulating film interface but also through the substrate.
It has characteristics such as unsaturated current-voltage characteristics and a driving capacity of 7. In particular, the notched insulated gate static induction transistor has a channel formed in the depth direction of the semiconductor substrate, so the channel length and gate length can be easily controlled, making it suitable for shortening the channel.

The conventional structure of this notched insulated gate static induction transistor will be explained with reference to FIG. A U-shaped groove 40' is formed on one main surface of a high-resistance silicon substrate 40 that will serve as a channel.
A thin gate insulator is provided on the side wall of the groove 40'.
A gate electrode 42 of polycrystalline silicon is formed through the gate electrode 41 . Regions 44 in contact with the top and bottom of the U-shaped groove 40' are, for example, n-type drain and source regions with high impurity density. Of course, the bottom part may be used as a drain or a source. The conductivity type of the channel may be n-type or p-type, but the impurity density is determined so that the space between the drain and the source is completely depleted during at least a part of the operating state. Under such operating conditions, a potential barrier is formed in the channel in front of the source, and the amount of carriers is controlled by the height of this potential barrier, so the drain current varies not only with the gate voltage but also with respect to the drain voltage. However, it changes exponentially.

This potential barrier does not necessarily need to be formed at the interface between the silicon substrate and the gate insulating film, and can be formed inside the silicon substrate, thereby achieving a large driving capability.

(Problem to be Solved by the Invention) However, in the structure of the above-mentioned notched insulated gate static induction transistor, in order to form the gate electrode in a self-aligned manner with respect to the U-shaped groove, the material of the gate electrode is Polycrystalline silicon was used as the material. Therefore, the gate series resistance becomes large, and the switching speed is limited due to the time constant between this resistance and the input capacitance.

SUMMARY OF THE INVENTION An object of the present invention is to provide a notch type insulated gate static induction transistor with a small gate series resistance without sacrificing self-alignment, and a method for manufacturing the same, thereby increasing the speed of the transistor.

(Means and effects for solving the problem) For this purpose, in the present invention, a low resistance electrode made of a high melting point metal or a high melting point metal silicide is formed in a self-aligned manner on at least a part of the side surface of the polycrystalline silicon of the gate electrode. This improves gate series resistance and reduces switching time.

(Example) Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 shows a cross-sectional structure of an embodiment of a notched insulated gate static induction transistor of the present invention. A U-shaped groove 10' is formed on one main surface of a high-resistance silicon substrate 10 that will serve as a channel.
A polycrystalline silicon gate electrode 12 serving as a control electrode is formed on the side wall of the trench 10' with a thin gate insulating film 11 such as an oxide film interposed therebetween. Further, a low resistance electrode 13 made of a high melting point metal or a high melting point metal silicide is formed on at least a portion of the side wall of the gate electrode 12 made of polycrystalline silicon. On the main surface and the region 14 in contact with the bottom of the U-shaped groove 10', main electrodes, for example, n-type drain and source regions having high impurity density are provided. Of course, the bottom part may be used as a drain or a source. The conductor 71t type of the channel may be either P type or N type, but its impurity density is determined so as to ensure that the channel is depleted in at least a part of the operating state. Although the presence of the polycrystalline silicon gate electrode 12 does not change the threshold voltage of the transistor, the presence of the low resistance electrode 13 can significantly reduce the gate series resistance in the direction perpendicular to the plane of the paper.

FIG. 2 shows the manufacturing process of one embodiment of the notched insulated gate static induction transistor of the present invention shown in FIG.

FIG. 2(a): First, a U-shaped groove 20' is formed on one main surface of a high-resistance silicon substrate 20 by anisotropic plasma etching, and then a thin gate oxide film 21 is grown.

The silicon substrate 20 is usually 1011c11-8 to 1011
A (100) substrate having an impurity density of about 0.014cI is used. A portion near the substrate surface that will become a channel may be doped with an impurity of about 10 cm to 10 17 cm −3 , and is set so that the channel is depleted in at least a part of the normal operating state. The depth of the U-shaped groove 20' is 0.1-1.mu.1 degrees, and can be formed by anisotropic plasma etching using PCfI3, for example. The thickness of the thin gate oxide film 21 is about 5 ns to 100 ns.

FIG. 2(b) Polycrystalline silicon film 2 is formed by secondary CVD method.
2 is deposited, and then a high melting point metal film 23 is further deposited. The film thickness of polycrystalline silicon is about 0.1 μm to 0.5 μm, and S t H4
/H2CVD method can be deposited,
Simultaneous doping with PH3 or B2H6 is also possible. The high melting point metal film 23 includes molybdenum (Mo) and tungsten (W).
, titanium (Ti), tantalum (Ta), etc. are suitable. [15μ-~0.
Approximately 5μ layer is formed. These materials can be formed not only by the CVD method but also by sputtering, vapor deposition, etc., but considering the coverage of the U-shaped groove, it is most appropriate to use the CVD method. For example, WF6/H2CVD method WF e /5iH4C
This can be done by the VD method or the like.

FIG. 2(C) The high melting point metal film 23 and the polycrystalline silicon film 22 are continuously etched by anisotropic plasma etching, and the high melting point metal film 23 and polycrystalline silicon film 22 are etched only on the side wall of the U-shaped groove 20'. A two-layer film of crystalline silicon film 22 is left. Furthermore, it is also effective to silicide the high melting point metal film 23 by a lamp annealing method or the like. In particular, the resistance of titanium can be lowered by turning it into a silicide.

Figure 2(d): Source and drain 24 are 1018C
It has an impurity density of about a1 to 11021a, and is formed by a diffusion method, an ion implantation method, or the like.

By performing anisotropic etching of the polycrystalline silicon film and the refractory metal film in this way, a low-resistance gate electrode can be formed in a self-aligned manner with respect to the U-shaped groove.

Further, FIGS. 2(b') and 2(c') show the manufacturing process of another embodiment of the notch type insulated gate static induction transistor of the present invention. Figures 2(a) and 2(d) take the same steps.

FIG. 2(b'): A polycrystalline silicon film 22 is deposited and left only on the side walls of the U-shaped trench by anisotropic plasma etching.

FIG. 2(c') A high melting point metal film 23 is selectively deposited only on polycrystalline silicon by selective CVD. Such selective growth can be performed using the WFe/SiH4CVD method or the like. Of course, it is also effective to silicide the high melting point metal 23 as in the case of FIG. 2(C).

Moreover, the high melting point metal film 23 is grown on the entire surface. polycrystalline silicon by heat treatment. Selective screening of only the high melting point metal on 22 Select the remaining high melting point metal after reciding. selectively etched to remove A similar shape can also be obtained.

In this manner, a low-resistance electrode made of a high-melting point metal or a high-melting point metal silicide can be formed only on the polycrystalline silicon by first performing anisotropic etching of the polycrystalline silicon film and then using the selective CVD method or the selective oxidation method.

Table 1 shows measurement examples of sheet resistance when the conventional polycrystalline silicon gate and the low resistance gate electrode of the present invention are formed of titanium silicide. The sheet resistance is about 1730 of n polycrystalline silicon, and about 1/100 of p polycrystalline silicon.
It can be seen that this has been improved.

Table 1 So far, we have discussed n-channel notched insulated gate static induction transistors, but the same applies to p-channel notched insulated gate static induction transistors with p-type conductivity in the drain and source regions. It is.

Figure 3 shows the propagation of a complementary integrated circuit using a conventional polycrystalline silicon gate notched insulated gate static induction transistor and a complementary integrated circuit using a notched insulated gate static induction transistor using a low resistance gate electrode according to the present invention. The results of evaluating the relationship between delay time and power consumption using a 31-stage ring oscillator are shown. A propagation delay time of 49 psec was obtained when the power consumption was 7 mV, and the switching time was reduced by about half compared to the conventional one.

(Effect of the invention) As described above, the notched static M having the low resistance electrode of the present invention
Since the S-induced transistor can improve the gate series resistance, the switching time can be reduced, and a high-speed logic circuit can be provided. Therefore, the industrial value is large.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing an embodiment of a notched insulated gate static induction transistor having a low resistance electrode of the present invention, and FIG. 2 is a cross sectional view of a notched insulated gate static induction transistor having a low resistance electrode of the present invention. FIG. 3, which is a sectional view of each process showing an example of the manufacturing method, compares an example of the relationship between the switching time and power consumption of the complementary integrated circuit of the notched insulated gate static induction transistor according to the present invention and the conventional one. FIG. 4 is a cross-sectional view of a conventional notched insulated gate static induction transistor. 10...Silicon substrate, 10'...0-shaped groove, 11
... Gate insulating film, 12 ... Polycrystalline silicon gate electrode, 13 ... Low resistance electrode, 14 ... High impurity density region. Applicant's representative Patent attorney Takehiko Suzue 10: Silicon Toad 1 and 10': 0-shaped groove]
1; Kate Shutsuwado 12: Robbery 6 #1! Silicone electrode 13; other electrodes 14 two high hair-free cows armpit area

Claims (2)

[Claims] (1) A silicon substrate has a U-shaped groove on one main surface, main electrodes are provided on the main surface and the bottom of the U-shaped groove, and a thin insulating film is formed on the side walls of the U-shaped groove. Furthermore, a cut-type insulated gate static induction transistor having a polycrystalline silicon control electrode is characterized in that a high melting point metal or a high melting point metal silicide is formed on at least a part of the side wall of the polycrystalline silicon control electrode. Notched insulated gate static induction transistor. (2) Forming a U-shaped groove on one main surface of the silicon substrate, forming a thin insulating film on the sidewalls of the U-shaped groove, depositing polycrystalline silicon, and performing anisotropic plasma etching. leaving only on the side wall of the U-shaped groove by
A method for manufacturing a notched insulated gate static induction transistor, comprising the step of depositing a high melting point metal film and leaving it only on the polycrystalline silicon.