JPS58147151A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To improve the reliability of the insulation between a gate electrode and a source, a drain by removing a film formed on a gate before the step of forming a metal semiconductor compound on the gate electrode, source and drain regions, thereby selectively growing the metal or metal semiconductor on the gate electrode and the source, drain regions. CONSTITUTION:A field oxidized film 102, a gate oxidized film 103, a phosphorus- doped polycrystalline silicon film 104 and an Al film 105 are formed on a P type silicon substrate 101. Then, an Al film 106, the film 105 and the film 104 are selectively etched, and a source and drain region 107 and a wiring region 107' are formed by As ion implantation. Then, when a silicon oxidized film 108 is formed and is etched and removed, a silicon oxidized film 108' remains. Subsequently, the film 106 is removed, tungsten (W) 109 is then deposited in vacuum and annealed, and a tungsten silicide (WSi2) is then grown. Thereafter, an MOS transistor is completed in accordance with the ordinary manufacturing steps.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device for use in a retractor circuit having a l1Ii speed and an a & i torpedo strength.

[Prior art and its problems]

In recent years, the integration density of integrated circuits has increased, and the so-called MLII
Research on I-engineering is underway. By the way, as the degree of integration increases (t'm), the dimensions of the elements that make up the circuit (Jk*T) must be reduced. However, for MOS transistors, the dimensions of the transistors become smaller, and in particular, the transistors that also serve as channels become shorter. As time goes on,
It is known that a so-called short channel effect occurs, and the voltage of the transistor is gradually reduced. This is mainly due to the fact that nitrogen-depleted pigeons due to the drain voltage invade the channel region 12, and 11L# of the channel region has a large influence not only on the gate voltage but also on the drain voltage (=I
This is because it has been done. As a means to prevent this short channel gJ red, there is a method of increasing the substrate temperature in this part by implanting ions into the defective fIjA region, and suppressing the invasion of the poor noodle to 1 by reducing the gate oxide layer thickness. There are methods such as increasing the influence of the electric field of the electrode ◇Also, if the diffusion layer of the source and drain 1) leaks, the invasion of the nitrogen depletion layer into the channel region will be suppressed. /A can be prevented, but when xj is cut, the wiring area is narrowed due to the wiring area being formed by the expanded lik layer at the same time as the source and drain in the normal process, or due to the small proportion.
There is a problem in that the resistance of the wiring area due to the rays ν and the enlarged rays is reduced, and the operating speed of the circuit is significantly reduced. Also, such a shallow 1? When an M9 coupling is created to suppress the extension of the 9 Oboro toward the Dunnell direction, the reverse withstand voltage of the Pli@ coupling decreases due to so-called nerf escape down, and the power supply and voltage 't'ai< are not possible. On the other hand, mv also occurs for the gate electrode during the same period. In other words, the resistance of the wiring made of the gate electrode material limits the circuit operation.
Two. For this reason, the conventional example is International Device Meeting CI IDM) 1981+ 28.
2 rhxoyprxwhLLx DISIGIJIC
DP only00IC88FOIL 8tTBMIO1
As shown in 011MO8F1-8, at least the gate electrode material is covered with an insulator, and then the entire surface is coated with metal.
IK is deposited, and metal silicide is formed by the reaction between the metal and silicon in a form that is self-coated with the gate without mask alignment on the source drain, the wiring area connected to the side of the source drain, and the gate electrode surface. By forming and then removing the unreflected IEh metallized V in the fi part, the ratio fl1m can be reduced without impairing the integrated density.
Suppress the effect V of the short time, 1jIi at a time
A method has been proposed to enable vortex action and reverse voltage resistance. Also, in the same process 1cDM19813.2, a method for selectively forming bimetallic tungsten (Wl) on a substrate 81 or on linear crystalline silicon is shown. When selectively growing (:), the growth layer between the gate electrode A, source, and drain is extremely slow, and in a state close to that II (2), this insulation defect may cause leakage, leakage, or breakdown voltage failure. etc. were a problem.

[Purpose of the invention]

An object of the present invention is to overcome the drawbacks mentioned above. When forming metal or metal silinide on the surface of the gate electrode and source/drain region in cell 7 alignment, The aim is to improve the reliability of the insulation between the two.

[Summary of the invention]

In the present invention, the am'Ik%
The metal or metal half body compound is removed at the R stage before the process of forming the V gate electrode and source/drain region. Then, the metal or metal semiconductor vj! is applied to the W pole and the source and drain regions. The present invention provides a method for manufacturing an 8-speed transistor that can be selectively formed into ik3.

〔Effect of the invention〕

By using the method of the present invention, it becomes possible to separate the metal or metal semi-metal compound formed in the source and drain regions, and the reliability of the insulation between the two is significantly increased. Therefore, it becomes possible to achieve low resistance with good reliability.

[Embodiments of the invention]

Embodiment 11 of the present invention will be described in detail below with reference to the 11th page. IIl prisoner (&1, e.g. 5 by normal process
Field formation 1 on the P-sprayed Shitacon board 101 with 0Ω scratches
11102r'-) Oxide film 103 (ill thickness 2007
1) Next, tan-doped polycrystalline silicon t04YII is formed, and then layer 105 is formed on polycrystalline V9 conductor 104JllII via a thin silicon oxide all (replacement thickness 2◎0mm) 105 for etching stopper.
Forms 4 voices. Next, using light exposure technology, F) rkil
Resist pattern t/formed 1 This resist pattern! 106% silicone as a mask 105
, multi-M insect silicon training 104, v selection etching. Next, the example is Muio: /l'40, V in lx,, 14a
By implanting 1-1 ions, one source and drain region 107 is formed in a second 1iI1 region 107''1. Next, by the well-known low-temperature vapor phase Ifck method, silicon is coated with a 108 k concentration on the entire surface of the silicon substrate.
Form to a uniform thickness of 3 pm (ill! W (see cl) o
8. In addition, 1. Reactive ion etching method or Subatu etching method, etc. C
From 2, this silicon oxide-108t' etching removal removes 1 gate electrode 104.105.106^[
Silicon oxidation a 108 so that only the side wall of 42 is behind
' remains (Kin 1a (a + Japanese wax).

Then, after surface cleaning with 0.7 lasma particles, polycrystalline V5
The layer 166 formed on the container 104 is removed.

Next, after washing the surface with TkJv+wi salt,
After performing Shimako 1I7AV for the activation of ions, 1 silicon, polycrystalline v9 con*i & lt 2 formed thin insulating metal '1: removed and whole blood C2 gold^rin2 e.g. tungsten tank 1109 t'# 4QOA True! ! , I! Watch (first cause tel sanwa). The next example is 800℃
When the 41# is annealed in its own air for about 1 hour, a silicide formation reaction occurs selectively only in the areas where the tungsten 109 and silicon are in contact, and the source and drain regions 107
Surface and wiring area t#1! 107 surface and polycrystalline silicon gate) 104 Tungsten silinide 1xO in table
cvr8i rika grows.

Here, unreacted tungsten is removed by acid treatment (see # in FIG. 2(f)). The following is a normal MOS)
According to the manufacturing process of transistors, PsG conversion, contact holes, blunt holes, and tying lines are formed. Finally, as a maintenance exhibition, the F8GI was installed, holes for bonding were made, and the M, 08) transistor was completed.

! IN2 Figure C2 shows a top view. In the figure, the Moum' cross section corresponds to the s2 factor. This transistor is used, for example, as a switching Tr, and when a voltage of, for example, 5V is applied to the gate and a voltage of, for example, 5V is input to the source from an inverter (not shown), the drain is applied with 5V-Vt.
h (t, large cage) is output, misses the diffusion wiring, and is input to the gate of another transistor.

The above M08 transistor protrudes from the remaining shape 108' of the silicon oxide layer formed in the polysilicon gate-diffusion barrier or from the upper edge of the mask 106 used as a target. For this reason, the surface of the silicon oxide layer on the surface between the polysilicon gate and the diffusion layer becomes thicker, which reduces leakage, short circuits, and stylus pressure defects due to silicide growth between the polysilicon gate and the diffusion layer. , reliability has been improved.

In this example, only the case of selective formation of tungsten silicide was explained, or the technique of selective formation of metal on silicon (for example, the 159th 11th
@m1oal 8ociety Meeting 19
81 no 1cxt@na@a Abstracts va
81-1 Mu b*traots No. 285 or IiDM81 3.2 Low R55isfan
cs 8elfmuxignexposure<L 8ourc@5
Drain ana Gaps Drain ansis
tors im shown. )l, μ on 8i
A meal^ is formed, but 810. Since 4 is not formed on the top, the same 94-
Bon Island! It is possible to apply the present method to the source, drain, and 6-nivori silicon. The metals selectively formed at this time include tungsten and molybdenum.

In the above embodiment, approximately 11
Since the tungsten silicide of 0.00 μm is formed, an extremely low resistance of approximately 7 Ω for the source and drain portions and approximately 5 Ω for the gate portions can be obtained, and it was made using a conventional method that does not use silicide. Diffusion layer (-1=sOQ1
The delay in the diffusion layer wiring extending from the drain (or source) can be significantly reduced. The resistance of the drain (or source) and diffusion layer wiring is generally longer than the length of the wiring area or the dimension of the source or drain connected to it, so the resistance is higher than that of the source or drain. Therefore, the effect of forming metal silicide on the surface of the wiring area is great.

On the other hand, the wiring region may be provided on both the drain and the source.In this method, the dose of ion implantation for forming the source and drain can be determined regardless of the diffusion and the resistor tube. "a-t conventional method (D l
It becomes possible to use a FZ of 1/10 to the C ratio, and it is possible to lower the summer at the edge of the gate. For this reason, the drain drain extends not only to the substrate side but also to the mu ion-implanted layer side (N@ region), that is, inside the PM junction.

As a result, the nitrogen depletion layer near the drain expands, resulting in a surface breakdown voltage of approximately 4 to 5 V compared to the conventional method.
I was able to raise it. In addition, the 9 depletion field capacity of the source and drain can also be reduced by about 40 times, resulting in a +a operation speed of about 101i-30 times! We were able to. In this case, including the silicide layer 1 formed, P
The M-conjugated blood is approximately 0.2^- from the soil surface of the silicon substrate.
(Conventionally, the depth was about 0.4 .mu.m), making it possible to extremely effectively prevent the short beam effect.

On the other hand, the well-known analogy is C: Dynamic R.
In ms circuits such as AM, Bo! l! /J connection wiring t bit is used for low or special word order. For example, 0.3μ
The β- of polysilicon of m is approximately 15 Ω/port even when heavily doped. When approximately 400 μm of tungsten silicide is formed on polysilicon, the resistance of ρ is approximately 5Ω/hole, which is 1/3 compared to polysilicon wiring made by the conventional method that does not use silicide. can be reduced.

Honestly @ - Game) Cover f on polycrystalline silicon 104! I
As for the i-exhibition, only the case of agriculture 106 was shown, or I[
It is clear that the material of the material is not limited to AL, but may be made of a metal such as a Mo film or an insulating material.

In the method described above, only the case of island annealing (2) is described as the side formation reaction, but this may be performed by, for example, irradiating the metal field with a laser. When the 0f-Ar laser is turned on, a similar result can be obtained by performing a laser scan with an output of about 10 W.
- It is convenient because the tin salt temperature w'la is not required. It is also possible to selectively irradiate only predetermined locations with the laser and -^.

The same thing can be done by irradiation with a CWIIL child beam. Silinide can be formed by, for example, implanting ions of 5iyv and 6 ions at the silicon interface after evaporation of 400m of tungsten. etc.

In the above embodiments, only the case of P-wrinkle silicon was described as the semiconductor substrate, but this is not limited to P-wrinkle silicon, but it is also applicable to y temperature or 0M0.
Both N and P like 8! It may be possible to have two substrates on one substrate, or it may be polysilicon crystallized on an amorphous material, single silicon, or SOS. Also, as for Kafuede noodles, I mentioned the case of W, and others Pt, Pa,
Needless to say, anything that achieves alloying, such as Mo, Mb, Ta, etc., may be used. Also, the source, drain, and wiring area table for making the P1 junction, which is the second factor, can be used. It is also possible to form a metal silicide, and then perform ion implantation from 62° C. to 62° C. In addition, the impurities for forming the source and drain V may also be B,
You can use anything as long as it is a substrate and impurities such as 4P. Also, control the gate electrode @'X108'
Although only the case of 810 is shown, any insulating material such as 1-alumina may be used. Also, as a gate electrode,
Using polycrystalline silicon l, there is a thin layer 51 between the ridges LII.
However, these 81o and Ic are not necessarily necessary.Also, in the embodiment of the present invention, Mu ion implantation into the diffusion field was performed only after patterning the polycrystalline silicon gate. It is also possible to perform a second Mu-ion implantation Y directly into the metal island 11 [ia]. Also, in that case, the 11th ion implantation must be performed at ilI + one time! For example, IXIQ"-IXIQ" am
Also, in this example, only when metal ν sootide is pasted on all of the source, drain, and gate electrodes. There are cases where it is not always necessary to lower the resistance by gluing. For example, when polycrystalline silicon is used as a resistor, it is used conveniently without lowering the resistance.

In such a case (secondly, if there is no mask alignment, leave at least 411 strokes on the polycrystalline silicon in the field area, and perform one crucifixion of the silicone etc.) Partial silinide 4! Partial C
: It is also possible to prevent the formation.

[Brief explanation of drawings]

Diagram M1 (1 to lfl is a process cross-sectional view showing one embodiment of the present invention, and the second decoy is a plan view thereof. Oxidation 104... Polycrystalline silicon gate 105.108.108'... Insulating metal (810□) 1
06-...MulII&l 07,l 07''・n Diffusion Oboro 109...Metal (9) 11.0...Metal silicide (VSt,) (731
7) Kensuke Yoshio, Patent Attorney Nori Chika (and 1 other person)

Claims (1)

[Claims] A step of forming a half-body film gate of an M/S transistor in which a film is provided on a half-body substrate, a step of forming an insulator on this gate, and a step of forming an insulating material on this gate, It is characterized by comprising the following steps: 1) a step of removing the insulator on the gate sidewall to protrude above the gate sidewall; and a step of selectively growing a metal or metal semiconductor compound from the source and drain regions of the peninsula substrate and the semicircular gate. A method for manufacturing a semiconductor device.