JPS6113393B2 - - Google Patents
Info
- Publication number
- JPS6113393B2 JPS6113393B2 JP12661777A JP12661777A JPS6113393B2 JP S6113393 B2 JPS6113393 B2 JP S6113393B2 JP 12661777 A JP12661777 A JP 12661777A JP 12661777 A JP12661777 A JP 12661777A JP S6113393 B2 JPS6113393 B2 JP S6113393B2
- Authority
- JP
- Japan
- Prior art keywords
- polycrystalline silicon
- layer
- oxide film
- silicon
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 27
- 239000004065 semiconductor Substances 0.000 claims description 10
- 239000004020 conductor Substances 0.000 claims description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 229910052814 silicon oxide Inorganic materials 0.000 description 10
- 229910052751 metal Inorganic materials 0.000 description 9
- 239000002184 metal Substances 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 238000000034 method Methods 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 239000012535 impurity Substances 0.000 description 5
- 230000015654 memory Effects 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 238000001947 vapour-phase growth Methods 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Non-Volatile Memory (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置、特に多結晶シリコンを用
いた半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to a semiconductor device using polycrystalline silicon.
多結晶シリコンを用いた半導体技術でよく知ら
れているのにシリコンゲート技術があり、大容量
メモリーや高速マイクロプロセツサーに使用され
ている。近年の技術進歩によりMOSLSIは高速
化、高密度を達成しているが、高速化に伴い多結
晶シリコンの抵抗が無視できなくなつてきてい
る。それは十分な不純物の添加にもかかわらず、
金属配線に比べて、はるかに抵抗が高いためで、
多結晶シリコン配線は抵抗を気いする高速ICや
電位降下に気になるセンスアンプ回路には使用上
の大きな制約になつている。特に、大容量メモリ
ーではアドレスラインに多結晶シリコンを使用す
ると、アドレス方向への抵抗成分による信号の遅
れが発生し高速化が不可能であるので、アルミニ
ウムのような低抵抗の金属配線で補強するのが普
通であるが、スタテイクRAMの様な多素子型メ
モリーではこの方式ではどうしてもセル面積の増
大につながり、あまり用いられないのが現状であ
る。最近では、多結晶シリコンの代りにモリブデ
ン、タンタルあるいはタングステンなどの耐熱性
金属を用いた方式や多結晶シリコンと耐熱性金属
との二層構造方式が提案されてはいるが、前者の
耐熱性金属が水素を通さないためによるシリコン
とシリコン酸化膜との界面の安定化が難しいこ
と、後者は配線電極形成後に熱処理工程を行うと
二層間に反応が生じて配線層の抵抗増加がおきる
ので熱処理ができなく、シリコンゲート技術のメ
リツトが損われてしまうという欠点があり実用化
に至つていない。 A well-known semiconductor technology using polycrystalline silicon is silicon gate technology, which is used in large-capacity memories and high-speed microprocessors. Recent technological advances have enabled MOSLSI to achieve higher speeds and higher densities, but as speeds increase, the resistance of polycrystalline silicon can no longer be ignored. Despite the addition of sufficient impurities,
This is because the resistance is much higher than that of metal wiring.
Polycrystalline silicon wiring is a major constraint in its use for high-speed ICs that are sensitive to resistance and sense amplifier circuits that are sensitive to potential drops. In particular, when polycrystalline silicon is used for address lines in large-capacity memories, signal delays occur due to the resistance component in the address direction, making it impossible to increase speed. However, in multi-element memories such as static RAM, this method inevitably increases the cell area, so it is not often used. Recently, methods using heat-resistant metals such as molybdenum, tantalum, or tungsten in place of polycrystalline silicon, and systems with a two-layer structure of polycrystalline silicon and heat-resistant metals have been proposed. The latter is difficult to stabilize the interface between silicon and silicon oxide film because it does not allow hydrogen to pass through, and the latter is difficult to stabilize because the heat treatment process after forming the wiring electrode causes a reaction between the two layers and increases the resistance of the wiring layer. However, it has not been put into practical use because the merits of silicon gate technology are lost.
本発明の目的は上記の欠点を除去し、実用性の
ある低抵抗の多結晶シリコン配線構造を有する半
導体装置を提供することにある。 SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks and provide a semiconductor device having a practical low-resistance polycrystalline silicon wiring structure.
本発明は、多結晶シリコン層をゲート電極もし
くは配線電極の一部として用いる半導体装置にお
いて、前記多結晶シリコン層の上に絶縁層を設
け、該絶縁層の上に前記多結晶シリコン層よりも
電気伝導度の大きい導体層を設け、前記多結晶シ
リコン層と絶縁層と導体層が実質的に同じ形状で
構成され、前記絶縁層の一部に設けられた少くと
も一つ好ましくは複数個の電極開口部により前記
多結晶シリコン層と導体層とが電気的に接続され
ていることを特徴とする。 The present invention provides a semiconductor device using a polycrystalline silicon layer as a part of a gate electrode or a wiring electrode, in which an insulating layer is provided on the polycrystalline silicon layer, and an insulating layer is provided on the insulating layer with a higher electrical potential than the polycrystalline silicon layer. A conductive layer with high conductivity is provided, the polycrystalline silicon layer, the insulating layer and the conductive layer have substantially the same shape, and at least one, preferably a plurality of electrodes are provided on a part of the insulating layer. The polycrystalline silicon layer and the conductor layer are electrically connected through the opening.
本発明を実施例により説明する。 The present invention will be explained by examples.
第１図は本発明の半導体装置の１実施例の平面
図、第２図は第１図のＡ−A′断面図、第３図は
第１図のＢ−B′断面図である。 1 is a plan view of one embodiment of the semiconductor device of the present invention, FIG. 2 is a sectional view taken along line AA' in FIG. 1, and FIG. 3 is a sectional view taken along line BB' in FIG.
公知のＮチヤンネルシリコンゲート技術によつ
てＰ型シリコン基板１上にフイールド酸化膜４を
熱酸化で0.5〜1.0μｍの厚さに成長させ、その一
部にゲート酸化膜５を1000〜1500Åの厚さに成長
させ、続いて不純物を添加した多結晶シリコン層
７を600〜800℃で気相成長法により成長させる。
この多結晶シリコン層７へのＮ型不純物添加は成
長後に従来の拡散法によつて行つても良い。 A field oxide film 4 is grown by thermal oxidation on a P-type silicon substrate 1 to a thickness of 0.5 to 1.0 μm using a well-known N-channel silicon gate technique, and a gate oxide film 5 is grown to a thickness of 1000 to 1500 Å on a part of the field oxide film 4. Then, a polycrystalline silicon layer 7 doped with impurities is grown by vapor phase growth at 600 to 800°C.
The N-type impurity may be added to the polycrystalline silicon layer 7 after growth by a conventional diffusion method.
次に、熱酸化を比較的低温で行い厚さ100〜
1000Åの熱酸化膜８を成長させ、所定の場所に第
１コンタクト１１を開口する。そして多結晶シリ
コン層７より電気伝導度の大きい導体金属層９、
例えばモリブデンをスパツタ方式で厚さ0.3〜0.8
μｍに成長させ、その上に気相成長法によりシリ
コン酸化膜６を成長させる。 Next, thermal oxidation is performed at a relatively low temperature to achieve a thickness of 100~
A thermal oxide film 8 of 1000 Å is grown, and a first contact 11 is opened at a predetermined location. and a conductive metal layer 9 having higher electrical conductivity than the polycrystalline silicon layer 7;
For example, molybdenum is sputtered to a thickness of 0.3 to 0.8
A silicon oxide film 6 is grown on the silicon oxide film 6 by vapor phase growth.
次に、写真食刻法を用いて電極パターンを形成
後、シリコン酸化膜６を選択的に除去し、シリコ
ン酸化膜６をマスクとして導体金属層９をプラズ
マ法により除去し、熱酸化膜８をシリコン酸化膜
６を残す様に弗酸系の液によつて除去し、再びプ
ラズマ法により多結晶シリコン７を除去する。こ
の後、イオン注入法もしくは通常の拡散法によつ
てＮ型不純物を拡散し、ソース及びドレイン領域
を形成し、最後に電極間絶縁用のシリコン酸化膜
６′を成長し、第２コンタクト１２を開口後、ア
ルミニウム配線１０を真空蒸着法により成長させ
て本発明の半導体装置を得る。 Next, after forming an electrode pattern using photolithography, the silicon oxide film 6 is selectively removed, the conductive metal layer 9 is removed using a plasma method using the silicon oxide film 6 as a mask, and the thermal oxide film 8 is removed. The silicon oxide film 6 is removed using a hydrofluoric acid solution, and the polycrystalline silicon 7 is removed again using a plasma method. After that, N-type impurities are diffused by ion implantation or normal diffusion to form source and drain regions, and finally, a silicon oxide film 6' for interelectrode insulation is grown, and a second contact 12 is formed. After opening, aluminum wiring 10 is grown by vacuum evaporation to obtain a semiconductor device of the present invention.
本発明を適用した場合次の効果が得られる。 When the present invention is applied, the following effects can be obtained.
(1) 多結晶シリコンと導体金属層とは第１コンタ
クト部を除きシリコン酸化膜により分離されて
いるので通常のシリコンゲートプロセスのメリ
ツト、即ちゲート電極形成後の熱処理を行うこ
とができる。(1) Since the polycrystalline silicon and the conductive metal layer are separated by a silicon oxide film except for the first contact portion, the advantage of the normal silicon gate process, that is, heat treatment after forming the gate electrode can be performed.
(2) 配線抵抗はほとんど導体金属層で決まるので
多素子構成のメモリーセルのアドレスラインな
どの長距離配線を多結晶シリコン配線としてゲ
ート電極をかねることができ高集積度化が行え
る。(2) Since wiring resistance is mostly determined by the conductive metal layer, long-distance wiring such as address lines in multi-element memory cells can be made of polycrystalline silicon wiring, which can also serve as gate electrodes, allowing for higher integration.
(3) 多結晶シリコンを不純物添加後熱酸化できる
ので拡散時や多結晶シリコン成長時のゴミなど
によるピンホールを埋めることができ金属ゲー
トを用いた時のゲートシヨートを防ぐことがで
き高歩留、高信頼性を得られる。(3) Since polycrystalline silicon can be thermally oxidized after adding impurities, pinholes caused by dust during diffusion and polycrystalline silicon growth can be filled, and gate shoots can be prevented when metal gates are used, resulting in high yield. High reliability can be obtained.
上記実施例はＮチヤンネルMOSTについて説
明したが、本発明はＰチヤンネルMOST、バイ
ポーラICにも適用可能であることは勿論であ
る。 Although the above embodiments have been described with respect to an N-channel MOST, it goes without saying that the present invention is also applicable to a P-channel MOST and a bipolar IC.
第１図は本発明の半導体装置の１実施例の平面
図、第２図は第１図のＡ−A′断面図、第３図は
第１図のＢ−B′断面図である。
１……シリコン基板、２，３……ソース及びド
レイン領域、４……フイールド酸化膜、５……ゲ
ート酸化膜、６，６′……シリコン酸化膜、７…
…多結晶シリコン層、８……シリコン酸化膜、９
……導体金属層、１０……アルミニウム配線、１
１……第１コンタクト、１２……第２コンタク
ト。
1 is a plan view of one embodiment of the semiconductor device of the present invention, FIG. 2 is a sectional view taken along line AA' in FIG. 1, and FIG. 3 is a sectional view taken along line BB' in FIG. 1... Silicon substrate, 2, 3... Source and drain regions, 4... Field oxide film, 5... Gate oxide film, 6, 6'... Silicon oxide film, 7...
...Polycrystalline silicon layer, 8...Silicon oxide film, 9
...Conductor metal layer, 10...Aluminum wiring, 1
1...first contact, 12...second contact.
Claims (1)
電極の一部として用いる半導体装置において、前
記多結晶シリコン層の上に絶縁層を設け、該絶縁
層の上に前記多結晶シリコン層よりも電気伝導度
の大きくかつ該多結晶シリコン層と実質的に同じ
平面形状で構成された導体層を設け、前記絶縁層
の一部に設けられた少くとも一つの電極開口部に
より前記多結晶シリコン層と前記導体層とが電気
的に接続されていることを特徴とする半導体装
置。1. In a semiconductor device using a polycrystalline silicon layer as a part of a gate electrode or a wiring electrode, an insulating layer is provided on the polycrystalline silicon layer, and a layer having an electrical conductivity higher than that of the polycrystalline silicon layer is provided on the insulating layer. A conductor layer having a large size and substantially the same planar shape as the polycrystalline silicon layer is provided, and at least one electrode opening provided in a part of the insulating layer allows the polycrystalline silicon layer and the conductor layer to be connected to each other. A semiconductor device characterized in that the two are electrically connected to each other.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12661777A JPS5459875A (en) | 1977-10-20 | 1977-10-20 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12661777A JPS5459875A (en) | 1977-10-20 | 1977-10-20 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5459875A JPS5459875A (en) | 1979-05-14 |
| JPS6113393B2 true JPS6113393B2 (en) | 1986-04-12 |
Family
ID=14939628
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12661777A Granted JPS5459875A (en) | 1977-10-20 | 1977-10-20 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5459875A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020111265A1 (en) | 2018-11-30 | 2020-06-04 | 株式会社 資生堂 | Pigmentation skin model and method for producing same, and method for evaluating factor for treating or preventing pigmentation of skin |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0215293A (en) * | 1989-05-25 | 1990-01-18 | Yamaha Corp | Electronic musical instrument |
-
1977
- 1977-10-20 JP JP12661777A patent/JPS5459875A/en active Granted
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020111265A1 (en) | 2018-11-30 | 2020-06-04 | 株式会社 資生堂 | Pigmentation skin model and method for producing same, and method for evaluating factor for treating or preventing pigmentation of skin |
| KR20210097116A (en) | 2018-11-30 | 2021-08-06 | 가부시키가이샤 시세이도 | Pigmented skin model and method for manufacturing same, and method for evaluating factors for treating or preventing pigmentation of skin |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5459875A (en) | 1979-05-14 |
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