JPS61287172A - Manufacture of high melting-point metallic gate mos semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the generation of peeling between a reaction layer and a residual polysilicon layer resulting from the instability of interface characteristics by forming a barrier layer between a high melting-point metal and polysilicon through knock-on implantation. CONSTITUTION:An oxide film 2 for isolating elements is formed to an Si substrate 1, a gate oxide film 3 through thermal oxidation and a gate polysilicon film 4 through a decompression CVD method are shaped in succession, and the film 4 is given conductivity through P diffusion, etc. and oxidized, thus forming an oxide film 5 on the surface. A partially removed section 6 is shaped, and oxygen atoms in the oxide film 5 on the polysilicon film 4 are knocked on through ion implantation. The oxide film 5 is removed, a high melting-point metal 7 is deposited, a nitride film 8 for a mask to ion implantation for forming source-drain is deposited, and an element is completed through processes of the patterning of a gate electrode, the formation of the source-drain 9, the deposition of an insulating film 10, the boring of contact holes, the formation of Al group wiring layers 11, etc.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a high melting point metal gate MO8 semiconductor which is heated to prevent the reaction between the upper layer high melting point metal and the lower layer polysilicon due to heat treatment in the device manufacturing process. The present invention relates to a method for manufacturing a device.

(Prior Art) Recent advances in integrated circuit technology are moving toward faster speeds and larger capacities. Currently, polycrystalline silicon (hereinafter referred to as polysilicon) is generally used for gate electrodes and wiring of MO8LSIs such as semiconductor memories.

In this case, the sheet resistance is on the order of several tens of ohms/region, so it is particularly important to use dynamic RAM (Random Acceas
In memory devices, word line signal delay is a major problem and is a major factor hindering the speeding up of devices.

Therefore, in recent years, attempts have been made to use various low-resistance materials for gate electrodes and wiring means. For example, Proceedings of the 45th Japan Society of Applied Physics Academic Conference, lecture numbers 13a-D-2 and 13a-D-3.
, page 475, etc.

Here, an example of an attempt to use a conventional low-resistance material for the gate electrode and wiring means will be explained.
Attempts have been made to apply high melting point metals that can be used in applications of 97 or less.

However, when conventionally used polysilicon is simply replaced with a high melting point metal, there are still many unstable factors such as MO8 interface characteristics compared to polysilicon, which is a well-known technology.

For example, when used in MOt gate electrodes, which are one of the high-melting point metals, the interface state density increases and the mobility decreases due to high-temperature heat treatment at about 900° C. or higher.

Therefore, as a measure to improve the instability of these MO8 field W1 characteristics, a gate electrode having a two-layer structure of a high melting point metal and polysilicon is being considered.

(Problems to be Solved by the Invention) However, even with this structure, a silicidation reaction occurs between the high-melting point metal in the upper layer and the polysilicon layer in the lower layer due to high-temperature heat treatment at about 900°C or higher, and the gate oxide film ( Sins
) Problems still remained, such as a decrease in dielectric strength of the polysilicon layer and the occurrence of peeling between the ink layer and the remaining polysilicon layer due to volumetric shrinkage caused by the reaction.

Therefore, there are examples in which a three-layer structure is created in which a high-melting point metal silicide (for example, MO8i) is sandwiched between the two-layer structure electrode to suppress the reaction between the high-melting point metal and polysilicon. Even with this structure, sufficient suppression has not yet been achieved.

This invention solves the problems of the above-mentioned prior art.
High melting point metal (f-) MO8 A high melting point metal (f-) MO8 that has solved the problem of peeling between the reaction layer and the remaining polysilicon layer due to the instability of the interface properties of LSI.
The present invention provides a method for manufacturing a No. 8 semiconductor device.

(Means for Solving the Problems) The present invention introduces a step of forming a barrier layer between a high melting point metal and polysilicon by knock-on implantation in a method of manufacturing a high melting point metal MO8 semiconductor device. It is.

(Function) According to the present invention, the above-described steps are introduced into the method of manufacturing a high-melting point metal (P-) MO8 semiconductor device, so that the high-melting point metal in the upper layer and the polysilicon in the lower layer are removed by heat treatment in the element manufacturing process. The barrier acts to prevent reactions between the layers, thus eliminating the above-mentioned problems.

(Example) Hereinafter, an example of the method for manufacturing a refractory metal r-) MO8 semiconductor device of the present invention will be described with reference to the drawings.

FIG. 1(a) to FIG. 1(d) are process explanatory diagrams of one embodiment thereof, and FIG. 2 is a plan view after forming the r-) electrode of MO8) Lansostar according to the present invention. 1(a) to 1(C) are cross-sectional views along the line X-X' in FIG. 2, and FIG. 1(d) is a cross-sectional view along the Y-Y' line in FIG. .

First, in FIG. 1(a), an oxide film 2 for element isolation is formed on a substrate 81 as a semiconductor substrate by a conventional method, and then a gate oxide film 3 is formed by thermal oxidation and a gate oxide film 3 is formed by low pressure CVD (CVD).
chemical vapor deposition
) A polysilicon film 4 is sequentially formed using the r-) method. P
-) The polysilicon film 4 is made conductive by P diffusion or the like. After that, this polysilicon film 4 is oxidized to create a different surface! Form l15.

This is carried out at 900° C. for 30 minutes in a dry oxygen atmosphere. That is, for reasons to be described later, the appropriate thickness of this oxide film 5 is about 20 to 1100 nm.

Thereafter, as shown in FIG. 1(b)K, a portion of the oxide film 5 on the polysilicon film 4, which will serve as a wiring, is removed from areas other than the P-) portion of the MOS transistor to form a partially removed portion 6. This is done by normal photolithography using a photoresist (not shown) as a mask.

Next, ion implantation is performed. This is done to knock on oxygen particles in the oxide film 5 on the polysilicon film 4. Therefore, 5 Aa commonly used in the semiconductor industry
Although ions, P ions, BF, ions, etc. can be used, heavier ions (larger number) are more suitable.

Further, the energy of the ion implantation is set so that the peak position of the implanted impurity is near the interface between the oxide film 5 of the polysilicon film 4 and the polysilicon film 4 (the oxide film side is better). In this way, one oxygen atom is efficiently knocked on.

For example, when the oxide film 5 is about 25 OA and the ion implantation energy is 40 KeV and about 70 OA, the ion implantation energy is 150 K@
V is appropriate. Additionally, the maximum implantation energy of a practical ion implanter is currently approximately 200 Key (approximately 400 K@VK when the implanted ions are double charged).
Therefore, from a practical standpoint, the appropriate thickness of the oxide film 5 on the polysilicon film 4 is about 20 to 1100 nm, as described above.

Next, the larger the amount of ion implantation, the more atoms are knocked on, so it is preferable. As a result of the experiment, about 5XIO ions/
-The above is better. However, if the implantation amount is large, it will take a long time for ion implantation, so from a practical point of view, approximately 1X
10 ions/- is suitable.

Thereafter, the oxide film 5 on the polysilicon film 14 is removed using an HF solution, and a high melting point metal 7 such as MO is deposited. This is done by sputtering, vapor deposition, CVD, etc.

Thereafter, a rat oxide film (5iaN+) 8 is deposited as a mask for the ion implantation to form the source and drain (FIG. 1(C)). This is done by sputtering, CVD, etc.

However, this does not necessarily have to be a nitride film, as long as it has a masking effect for the source/drain forming ion implantation.
atsGlass) lia etc. can be used.

Although the details will not be described hereafter, 1. Normal gate electrode patterning, source/drain 9 types, and insulating film using PSG.
The device is completed through processes such as deposition of 0, contact hole opening, and formation of Al-based wiring N111 (see Figure 1(d)).
)). Note that 13 is an r-) electrode pattern, and 12 is a 7-cut region.

As explained above, according to the manufacturing method of the present invention, a mixed layer with acid X atoms is formed on the very surface of the polysilicon layer by knock-on implantation, so even if heat treatment is added in the device manufacturing process, This mixed layer acts as a barrier layer and suppresses the reaction between the high melting point metal and the underlying polysilicon film, and is therefore expected to have effects such as improving device manufacturing yield and reliability.

Moreover, according to this invention, %a! ! Since it is possible to localize oxygen atoms at a higher concentration near the surface of the polysilicon film than with single contact ion implantation, properties such as resistance of the polysilicon film are hardly affected. Can be done.

Furthermore, since ions commonly used in the semiconductor industry, such as Th A, ions, can be used, there is no need for a separate oxygen ion implanter, which is useful from a practical standpoint.

In addition, in a structure in which a thermal oxide film or a CVD oxide film of the polysilicon film 4 is sandwiched, K to obtain a film without local defects is required to be at least 5 Q nm, and F-) the overall film thickness of the electrode. The r-) oxide film 3 is thicker and has steeper steps.
When etching the polysilicon film 4, there is a drawback that the oxide 1[5 on the polysilicon film 4 is also etched from the periphery of the pattern at the same time. However, in this invention, there is no increase in the film thickness, and there is no knock-on. Since the oxygen mixed layer is almost insoluble in the HF solution, it does not have the above drawbacks.

In addition, in the method explained in 5 and above, #! Although we tried to knock on the nitrogen atom, the same effect can be expected by knocking on the nitrogen atom.

In this case, instead of the oxide film 5 on the polysilicon film 4 shown in FIG. 1, a nitride film (SisN4) may be deposited by CVD or the like.

In addition, in the partially removed portion 6 (the portion that does not form a nitrogen atom mixture layer) to ensure electrical connection between the upper layer high melting point metal and the lower layer polysilicon, tunnel current flows through this mixed layer. Not necessarily necessary.

(Effects of the Invention) As described above in detail, according to the present invention, a polysilicon film serving as a gate electrode and wiring is formed on a semiconductor substrate, and an I oxide [or nitride film] is formed on the polysilicon film. & Since the atoms in this oxide film or nitride film are introduced into the polysilicon film by knock ion implantation, the reaction between the high melting point metal and the underlying polysilicon film can be suppressed.

Along with this, there is no peeling of the polysilicon film.

Improvements in device manufacturing yield t, b and reliability can be expected,
Characteristics such as resistance are hardly affected.

Moreover, there is no need for a Shunion ion implanter.

The mixed layer formed by knock-on ion implantation has the advantage of being almost insoluble in the HF solution.

[Brief explanation of the drawing]

FIGS. 1(a) to 1(d) are process explanatory diagrams of an embodiment of the method for manufacturing a high melting point metal P-) MO8 semiconductor device of the present invention, I! Figure 2 shows the same high melting point metal jiff-toM.
MOS obtained by O8 semiconductor device manufacturing method
) is a plan view after formation of the gate electrode of the LANDSTER; l...81 substrate, 2... oxide film for element isolation, 3
...Gate oxide film, 4...Polysilicon film, 5...
·Oxide film. 6... Partially removed portion, 7... High melting point metal, 8... Nitride film. 9... Source/drain region, 10... Insulating film, 1
1... Wiring layer, 12... Active region, 13...
・Gate electrode pattern. Patent applicant Oki Electric Industry Co., Ltd. Figure 1! Y' 23: Kate electrode Ha Gushi 2 Nozumu 11111 is Ma barrel? L Moxibustion Month 05 Transrisk Heisei 6 Figure 2

Claims (1)

[Claims] (a) A step of forming a polysilicon film to serve as a gate electrode and wiring on a semiconductor substrate; (b) Forming an oxide film or a nitride film on at least the gate portion of the polysilicon film. (c) a step of introducing atoms in the oxide film or nitride film into the polysilicon surface by knock-on ion implantation; (d) a step of removing the oxide film or nitride film to form a high melting point metal. , A method for manufacturing a high-melting point metal gate MOS semiconductor device, characterized in that the following steps are provided.