JPS627165A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS627165A
JPS627165A JP60144732A JP14473285A JPS627165A JP S627165 A JPS627165 A JP S627165A JP 60144732 A JP60144732 A JP 60144732A JP 14473285 A JP14473285 A JP 14473285A JP S627165 A JPS627165 A JP S627165A
Authority
JP
Japan
Prior art keywords
film
silicon
polycrystalline silicon
region
diffusion layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP60144732A
Other languages
Japanese (ja)
Other versions
JPH0831598B2 (en
Inventor
Naotaka Hashimoto
直孝 橋本
Nobuyoshi Kobayashi
伸好 小林
Yoshio Sakai
芳男 酒井
Kunihiro Yagi
矢木 邦博
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP60144732A priority Critical patent/JPH0831598B2/en
Publication of JPS627165A publication Critical patent/JPS627165A/en
Publication of JPH0831598B2 publication Critical patent/JPH0831598B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843Source or drain regions of field-effect devices
    • H01L29/0847Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45Ohmic electrodes
    • H01L29/456Ohmic electrodes on silicon

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE:To obtain a diffused layer having a low resistance and a shallow junction by selectively coating a diffused layer region with a high melting point metal film, then accumulating arsenic thereon, and implanting silicon to form a metal silicide in a self-aligning manner. CONSTITUTION:A gate oxide film 3 and a gate electrode 4 are formed on an active region partitioned by a field insulating film 2, a silicon dioxide film is accumulated, the entire semiconductor substrate 1 is etched, a silicon dioxide film 5 remains on the side wall on the electrode 4, with the film 5 as a mask an impurity to form a reverse conductive impurity to the substrate 1 is implanted to form a diffused layer region 6. A tungsten film 7 is selectively coated by a CVD method on the region 6, and an amorphous or polycrystalline silicon film 8 is coated thereon. Then, silicon ions are implanted from above to react the film 8 with the film 7, and heat treated at 650 deg.C to form a tungsten silicide film 9. The remaining film 8 is removed to allow the film 9 to remain only on the region 6.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は、半導体装置の製造方法に係り、特に金属硅化
膜の形成方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for forming a metal silicide film.

〔発明の背景〕[Background of the invention]

従来のゲート電極あるいは拡散層電極上へ自己製金的に
金属硅化物を形成する方法は、たとえば特開昭59−9
9774号に記載のように、半導体基板全面に金属膜7
を被着した後(第3図(a))、熱処理等により金属膜
と基板硅素が接する面のみ反応を起こさせ金属硅化膜9
を形成している(第3図(b))が、金属硅化膜形成に
必要な硅素を半導体基板1から得ているため、形成され
た金属硅化膜9は第3図(c)に示すように半導体基板
1側に入り込み、接合深さが浅くかつ低抵抗の拡散層領
域を金属硅化膜下へ形成することは困難である。
A conventional method of forming a metal silicide on a gate electrode or a diffusion layer electrode by self-manufacturing is described, for example, in Japanese Patent Application Laid-Open No. 59-9.
As described in No. 9774, a metal film 7 is formed on the entire surface of the semiconductor substrate.
(FIG. 3(a)), a reaction is caused only on the surface where the metal film and the silicon substrate are in contact by heat treatment etc. to form the metal silicide film 9.
(Fig. 3(b)), but since the silicon necessary for forming the metal silicide film is obtained from the semiconductor substrate 1, the formed metal silicide film 9 is as shown in Fig. 3(c). It is difficult to form a diffusion layer region that penetrates into the semiconductor substrate 1 side and has a shallow junction depth and low resistance under the metal silicide film.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、半導体基板内の拡散層の硅素の侵食が
少なく、その拡散層上へ自己整合的に金属硅化膜を形成
することにより、低抵抗でかつ接合深さの浅い拡散層を
提供することにある。
An object of the present invention is to provide a diffusion layer with low resistance and a shallow junction depth by forming a metal silicide film in a self-aligned manner on the diffusion layer with little silicon corrosion in the diffusion layer in the semiconductor substrate. It's about doing.

〔発明の概要〕[Summary of the invention]

上記目的を達成するために、本発明は半導体基板の侵食
が少なく拡散層領域上へ自己整合的に金属硅化膜を形成
できるよう、まず拡散層領域上へ高隔点金属膜を化学気
相成長法により選択的に被着した後1次いで非晶質ある
いは多結晶硅素をその上へ化学気相成長法等により堆積
させ、これで硅素等をイオン打込みにより注入し高隔点
金属膜と多結晶硅素を反応させ、その後余分な多結晶硅
素を除去することを特徴としている。
In order to achieve the above object, the present invention first forms a high separation point metal film on the diffusion layer region by chemical vapor deposition so that the metal silicide film can be formed on the diffusion layer region in a self-aligned manner with less erosion of the semiconductor substrate. After selectively depositing it by a method, amorphous or polycrystalline silicon is then deposited on top of it by a chemical vapor deposition method, etc., and then silicon, etc. is implanted by ion implantation to form a high separation point metal film and a polycrystalline silicon film. It is characterized by reacting silicon and then removing excess polycrystalline silicon.

〔発明の実施例〕[Embodiments of the invention]

以下、本発明の実施例を第1図及び第2図を用いて説明
する。
Embodiments of the present invention will be described below with reference to FIGS. 1 and 2.

本発明の第1の実施例を第1図に示す、まず、第1図(
a)に示すように、フィールド絶縁膜2で区画された能
動領域にゲート酸化膜3を熱酸化により形成しゲート電
極材料を被着(た後、パターンニングによりゲート電極
4を形成し1次いで化学気相成長(CVD)法により二
酸化硅素膜を堆積させた後1反応性イオンエツチング(
RI E)により半導体基板1上を全面エツチングし、
ゲート電極4の側壁上に二酸化硅素膜5を残存させ、こ
れをマスクとし半導体基板1と逆導電型の不純物を形成
するような不純物を注入し拡散層領域6を作成した。こ
れに、第1図(b)に示すように拡散層領域6上へCV
D法によりタングステン膜7を選択的に厚さ40nm程
度被着し、次いでその上へ非晶質や多結晶硅素膜8を温
度600℃程度でCVD法やスパッタ方法により厚さl
oonm被着する。次いで第1図(C)に示すように、
前記多結晶硅素8の上より硅素を加速電圧を100〜1
50keV、注入量はI X 10”〜I X 10’
″/li程度イオン打込みにより注入し、多結晶硅素膜
8とタングステン膜7を反応させた後、温度650℃程
度で熱処理を行ないタングステン硅化膜9を形成する。
A first embodiment of the present invention is shown in FIG.
As shown in a), a gate oxide film 3 is formed by thermal oxidation in the active region defined by the field insulating film 2, and a gate electrode material is deposited (after that, a gate electrode 4 is formed by patterning, and then chemically After depositing a silicon dioxide film by vapor phase deposition (CVD), reactive ion etching (
Etching the entire surface of the semiconductor substrate 1 using RIE),
A silicon dioxide film 5 was left on the side wall of the gate electrode 4, and using this as a mask, an impurity was implanted to form an impurity of a conductivity type opposite to that of the semiconductor substrate 1, thereby forming a diffusion layer region 6. In addition, as shown in FIG. 1(b), CV is applied onto the diffusion layer region 6.
A tungsten film 7 is selectively deposited to a thickness of about 40 nm using the D method, and then an amorphous or polycrystalline silicon film 8 is deposited thereon to a thickness of l by CVD or sputtering at a temperature of about 600°C.
oonm adheres. Then, as shown in FIG. 1(C),
Accelerating silicon from above the polycrystalline silicon 8 at a voltage of 100 to 1
50 keV, injection dose I x 10" to I x 10'
After the polycrystalline silicon film 8 and the tungsten film 7 are implanted by ion implantation to react with each other, a heat treatment is performed at a temperature of about 650° C. to form a tungsten silicide film 9.

次いで、絶縁膜2,5上に残った多結晶硅素膜8をヒド
ラジン溶液によって除去し、第111(d)のように拡
散層領域6上のみにタングステン硅化膜9を残す。
Next, the polycrystalline silicon film 8 remaining on the insulating films 2 and 5 is removed using a hydrazine solution, leaving the tungsten silicide film 9 only on the diffusion layer region 6 as shown in No. 111(d).

これは、拡散層領域6を形成した後に、タングステン硅
化膜9を形成する実施例であり、次いで第2図を用い、
タングステン硅化膜9を形成した後、拡散層領域6を形
成する第2の実施例を説明する。
This is an example in which a tungsten silicide film 9 is formed after forming a diffusion layer region 6, and then using FIG.
A second embodiment will be described in which the diffusion layer region 6 is formed after the tungsten silicide film 9 is formed.

第2図(a)は、フィールド絶縁膜2で区画された能動
領域にゲート酸化膜3を熱酸化により形成しゲート電極
材料を被着した後、パターンニングによりゲート電極4
を形成し、次いでCVD法により二酸化硅素膜を堆積さ
せた後、RIEにより半導体基板1上を全面エラチンブ
レゲート電極4の側壁だけに二酸化硅素膜5を残存させ
たMOS型半導体装置の断面図である。次いで第2図(
b)に示すように、拡散層を形成すべき半導体基板1の
露出した領域上にのみタングステン膜7をCVD法によ
り厚さ400人程度選択的に被着し、次いでその上へ多
結晶硅素膜8をCVD法により温度600℃程度切雰囲
気で厚さ1000人被着する0次いで第2図(、)に示
すように、前記多結晶硅素8の上より硅素を加速電圧1
00〜150keV、注入量x X 10111〜I 
X I O”/ffl程度イオン打込みにより注入し、
多結晶硅素膜8とタングステン膜7を反応させた後、温
度650℃程度で熱処理を行ないタングステン硅化膜9
を形成する6次いで、絶縁膜2,5上に残った多結晶硅
素fi18をヒドラジン溶液によって除去し、第2図(
d)に示すように拡散層を形成すべき半導体基板1の露
出した領域にのみタングステンシリサイド膜9を残す。
In FIG. 2(a), a gate oxide film 3 is formed by thermal oxidation in an active region defined by a field insulating film 2, a gate electrode material is deposited, and then a gate electrode 4 is formed by patterning.
A cross-sectional view of a MOS type semiconductor device in which a silicon dioxide film is deposited by a CVD method, and a silicon dioxide film 5 is left only on the sidewalls of an eratin bleed gate electrode 4 over the entire surface of the semiconductor substrate 1 by RIE. It is. Next, Figure 2 (
As shown in b), a tungsten film 7 is selectively deposited to a thickness of about 400 mm by CVD only on the exposed region of the semiconductor substrate 1 where a diffusion layer is to be formed, and then a polycrystalline silicon film is deposited on top of it. 8 is deposited to a thickness of 1000 by CVD in a cutting atmosphere at a temperature of about 600°C. Then, as shown in FIG.
00~150keV, injection dose x X 10111~I
Implanted by ion implantation to the extent of X I O”/ffl,
After reacting the polycrystalline silicon film 8 and the tungsten film 7, heat treatment is performed at a temperature of about 650°C to form the tungsten silicide film 9.
6 Next, the polycrystalline silicon fi18 remaining on the insulating films 2 and 5 was removed using a hydrazine solution, and as shown in FIG.
As shown in d), the tungsten silicide film 9 is left only in the exposed region of the semiconductor substrate 1 where the diffusion layer is to be formed.

ここで、第2図(、)において硅素をイオン打込みによ
って注入する代りにnチャンネルMOS型半導体装置の
場合にはAsをpチャンネルMOS型半導体装置の場合
にはB F z をイオシ種として用いることもできる
Here, instead of implanting silicon by ion implantation in FIG. 2(,), As is used as the ion species in the case of an n-channel MOS type semiconductor device, and B F z is used in the case of the p-channel MOS type semiconductor device. You can also do it.

次いで第2図(e)に示すように、イオン打込みによっ
てタングステン硅化膜9中へ半導体基板1と逆導電型と
なるような不純物を注入し、温度950℃程度の熱処理
をほどこすことにより拡散層領域6を作成する。
Next, as shown in FIG. 2(e), an impurity having a conductivity type opposite to that of the semiconductor substrate 1 is implanted into the tungsten silicide film 9 by ion implantation, and a diffusion layer is formed by heat treatment at a temperature of about 950°C. Create area 6.

第4図は、第1の実施例あるいは第2の実施例を用いて
形成した、相補形MOS形半導体装置の断面図である。
FIG. 4 is a sectional view of a complementary MOS type semiconductor device formed using the first embodiment or the second embodiment.

なお、本実施例では、金属をタングステンに限定して記
載したが、タングステンの代りにモリブデン及びチタニ
ウム等の金属を用いることも可能である。
In this embodiment, the metal is limited to tungsten, but it is also possible to use metals such as molybdenum and titanium instead of tungsten.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、拡散層電極のシート抵抗を10Ω/口
程度にすることができ、かつ拡散層の接合深さを、ゲー
ト酸化膜と半導体基板との界面から0.15μm以下に
することができ、浅い拡散層形成が必要な微細なMOS
トランジスタ及びそれを用いた大規模集積回路を実現す
る上で表常に有益である。
According to the present invention, the sheet resistance of the diffusion layer electrode can be made approximately 10Ω/hole, and the junction depth of the diffusion layer can be made 0.15 μm or less from the interface between the gate oxide film and the semiconductor substrate. Fine MOS that requires shallow diffusion layer formation
It is always useful in realizing transistors and large scale integrated circuits using them.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の第1の実施例を示す工程図、第2図は
本発明の第2の実施例を示す工程図、第3図は従来の製
造方法を示す工程図、第4図は本発明によって形成され
た相補形MQS型半導体装置の断面構造の一例を示す図
である。 1・・・半導体基板、2・・・フィールド絶縁膜、3・
・・ゲート酸化膜、4・・・ゲート電極、5・・・二酸
化硅素膜、6・・・N4″型領域、7・・・タングステ
ン膜、8・・・多結晶硅素膜、9・・・タングステン硅
化膜、10・・・P0冨 1  図 冨Z 図
Fig. 1 is a process diagram showing a first embodiment of the present invention, Fig. 2 is a process diagram showing a second embodiment of the invention, Fig. 3 is a process diagram showing a conventional manufacturing method, and Fig. 4 is a process diagram showing a conventional manufacturing method. 1 is a diagram showing an example of a cross-sectional structure of a complementary MQS type semiconductor device formed according to the present invention. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Field insulating film, 3...
... Gate oxide film, 4... Gate electrode, 5... Silicon dioxide film, 6... N4'' type region, 7... Tungsten film, 8... Polycrystalline silicon film, 9... Tungsten silicide film, 10...P0 1 Figure 2Z Figure

Claims (1)

【特許請求の範囲】 1、フィールド絶縁膜によつて区画された能動領域の所
定の位置に、少なくともゲート絶縁膜と側壁の絶縁膜と
が設けられたゲート電極を形成し、該ゲート電極をマス
クとし半導体基板と逆の導電型拡散層を形成する工程と
、該拡散造領域上に選択的に高隔点金属膜を被着し該高
隔点金属膜上に非晶質あるいは多結晶の硅素膜を被着す
る工程と、該非晶質あるいは多結晶の硅素膜へ硅素をイ
オン打込みにより注入し該金属膜と反応させ熱処理によ
り金属硅化膜を形成する工程と、絶縁膜上の非晶質ある
いは多結晶硅素を除去する工程を含むことを特徴とする
半導体装置の製造方法。 2、MOS型半導体装置の製造方法において、フィール
ド絶縁膜によつて区画された能動領域の所定の位置に、
少なくともゲート絶縁膜と側壁の絶縁膜とが設けられた
ゲート電極を形成する工程と、該能動領域の拡散層を形
成する領域にのみ高隔点金属膜を選択的に被着し、次い
で該高隔点金属上へ非晶質または多結晶の硅素を被着し
た後、硅素をイオン打込みにより注入し該高隔点金属と
反応させ熱処理を行ない金属硅化膜を形成する工程と、
絶縁膜上の該非晶質または多結晶硅素膜を除去する工程
と、次いで該金属硅化膜へ半導体基板と逆導電型拡散層
を形成するような不純物を注入し、熱処理により該不純
物を半導体基板側へ拡散させ拡散層を形成することを含
む半導体装置の製造方法。
[Claims] 1. A gate electrode provided with at least a gate insulating film and a sidewall insulating film is formed at a predetermined position of an active region partitioned by a field insulating film, and the gate electrode is masked. A step of forming a diffusion layer of a conductivity type opposite to that of the semiconductor substrate, selectively depositing a high-resolution metal film on the diffusion region, and depositing amorphous or polycrystalline silicon on the high-resolution metal film. a step of depositing silicon on the amorphous or polycrystalline silicon film, a step of implanting silicon into the amorphous or polycrystalline silicon film by ion implantation, reacting with the metal film, and forming a metal silicide film by heat treatment; A method for manufacturing a semiconductor device, comprising a step of removing polycrystalline silicon. 2. In a method for manufacturing a MOS type semiconductor device, at a predetermined position of an active region partitioned by a field insulating film,
A step of forming a gate electrode provided with at least a gate insulating film and a sidewall insulating film, and selectively depositing a high barrier point metal film only in the region where the diffusion layer of the active region is to be formed; A step of depositing amorphous or polycrystalline silicon on the retardation point metal, implanting silicon by ion implantation, reacting with the retardation point metal, and performing heat treatment to form a metal silicide film;
A step of removing the amorphous or polycrystalline silicon film on the insulating film, and then implanting an impurity into the metal silicide film to form a diffusion layer of a conductivity type opposite to that of the semiconductor substrate, and heat treatment to remove the impurity from the semiconductor substrate side. A method of manufacturing a semiconductor device, the method comprising forming a diffusion layer.
JP60144732A 1985-07-03 1985-07-03 Method for manufacturing semiconductor device Expired - Fee Related JPH0831598B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60144732A JPH0831598B2 (en) 1985-07-03 1985-07-03 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60144732A JPH0831598B2 (en) 1985-07-03 1985-07-03 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPS627165A true JPS627165A (en) 1987-01-14
JPH0831598B2 JPH0831598B2 (en) 1996-03-27

Family

ID=15369045

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60144732A Expired - Fee Related JPH0831598B2 (en) 1985-07-03 1985-07-03 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JPH0831598B2 (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63299377A (en) * 1987-05-29 1988-12-06 Matsushita Electric Ind Co Ltd Manufacture of semiconductor device
JPS63307726A (en) * 1987-06-09 1988-12-15 Seiko Epson Corp Manufacture of semiconductor device
JPH01298768A (en) * 1988-05-27 1989-12-01 Sony Corp Manufacture of mis transistor
JPH0661254A (en) * 1992-08-07 1994-03-04 Toshiba Corp Manufacture of semiconductor device
WO1995006329A1 (en) * 1993-08-20 1995-03-02 Tadahiro Ohmi Semiconductor device and its manufacture
JP2002203810A (en) * 2000-12-28 2002-07-19 Tokyo Electron Ltd Method for manufacturing semiconductor device, semiconductor device, and apparatus for manufacturing semiconductor device

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5459077A (en) * 1977-10-20 1979-05-12 Agency Of Ind Science & Technol Manufacture of semiconductor device
JPS58147151A (en) * 1982-02-26 1983-09-01 Toshiba Corp Manufacture of semiconductor device
JPS61230373A (en) * 1985-04-05 1986-10-14 Seiko Epson Corp Manufacture of semiconductor device

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Publication number Priority date Publication date Assignee Title
JPS5459077A (en) * 1977-10-20 1979-05-12 Agency Of Ind Science & Technol Manufacture of semiconductor device
JPS58147151A (en) * 1982-02-26 1983-09-01 Toshiba Corp Manufacture of semiconductor device
JPS61230373A (en) * 1985-04-05 1986-10-14 Seiko Epson Corp Manufacture of semiconductor device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63299377A (en) * 1987-05-29 1988-12-06 Matsushita Electric Ind Co Ltd Manufacture of semiconductor device
JPS63307726A (en) * 1987-06-09 1988-12-15 Seiko Epson Corp Manufacture of semiconductor device
JPH01298768A (en) * 1988-05-27 1989-12-01 Sony Corp Manufacture of mis transistor
JPH0661254A (en) * 1992-08-07 1994-03-04 Toshiba Corp Manufacture of semiconductor device
WO1995006329A1 (en) * 1993-08-20 1995-03-02 Tadahiro Ohmi Semiconductor device and its manufacture
JP2002203810A (en) * 2000-12-28 2002-07-19 Tokyo Electron Ltd Method for manufacturing semiconductor device, semiconductor device, and apparatus for manufacturing semiconductor device

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