JPS63299377A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To make a silicide layer diffused to a uniform depth, by previously coating the top face and the side walls of a gate electrode completely with an insulating film, adhering a highmelting point metal all over a silicon substrate and then forming an amorphous silicon layer. CONSTITUTION:After the top face and the side faces of a gate electrode 4 are previously coated completely with an insulating film 5, a high-melting point metal 12 is adhered on the whole surface of a silicon substrate 1. An amorphrous silicon layer 13 is then locally formed so as to cover the region extending from the top face of the gate electrode, through a source or drain region up to an insulating film 2 for isolating inter-elements. An MOSFET thus provided is allowed to have improved heat resistance principally because of reaction between the amorphrous silicon 13 and the high-melting point metal 12. The MOSFET is further allowed to have a silicide layer 6 and a silicified junction diffused to a uniform depth.

Description

DETAILED DESCRIPTION OF THE INVENTION FIELD OF INDUSTRIAL APPLICATION The present invention relates to a semiconductor device, and particularly to a method for manufacturing a highly integrated and high speed semiconductor integrated circuit.

Conventional technologyAs the density of semiconductor integrated circuits increases, MO, which is a component
Although the SFET is also scaled down, normal FET operation cannot be maintained in such a device unless scaling in the depth direction is also performed. This contradicts the need to construct a MOSFET that is capable of high-speed operation and has low junction leakage current.

In order to solve the above problems, a technology that has recently been attracting attention is the self-alignment formation of a silicide layer of a low-resistance, high-melting-point metal using an alloy reaction (silicide bonding method) rather than a high impurity concentration layer in silicon. ). In particular, in order to form a contact between the aluminum wiring and the source/drain diffusion region on the oxide film for isolation between elements, an insulating material is deposited on the side wall of the polysilicon gate electrode as schematically shown in FIG. A refractory metal is deposited on the entire surface of the silicon substrate with the upper polysilicon of the polysilicon gate electrode and the silicon substrate of the source/drain regions exposed. When forming an amorphous silicon layer locally on this high melting point metal film, it is possible to prevent a short circuit between the high melting point metal silicide formed later on the gate electrode and the non-film drain region. Therefore, for example, the method of setting the edge of amorphous silicon on the gate electrode side to a finite distance # from the gate electrode is
EDM 84 (1984) pp. 118-121 (IEDM 84 (1984) pp1
18-121).

Problems to be Solved by the Invention In the technology of forming a high melting point metal silicide in a self-aligned manner through an alloy reaction of a high melting point metal deposited on a substrate crystalline silicon, as long as this is applied to a large scale integrated circuit,
It is necessary that the uniformity of the film be maintained even after heat treatment (for example, activation of implanted impurities and flow of an interlayer insulating film) performed after the formation of the high melting point metal silicide film. However, up to now, especially the above-mentioned IEDM 84 (1984) pages 11 to 121 (IEDM
84 (1984) pp. 11s-121), when titanium gold is used as a high-melting point metal, even if a film with good uniformity is obtained during the formation of a titanium silicide film, the subsequent heat treatment at a relatively high temperature and long time (9oO There was a problem in that the titanium silicide film agglomerated during the heating process (for more than 30 minutes), causing surface roughness and exposing the silicon substrate at the cracks in the silicide.

Furthermore, when the edge of the shaped amorphous silicon is located in the middle of the source/drain region as in the conventional example shown in FIG. Despite the presence of titanium silicide, the titanium silicide layer is mostly formed on the upper side of the silicon substrate surface by reacting mainly with the upper layer of amorphous silicon. On the other hand, the titanium layer in the region where there is no amorphous silicon layer on the source/drain film reacts with the crystalline silicon of the substrate, and a titanium silicide layer is buried below the silicon substrate surface in the dog region. be done.

Toe 9 A step is created in the titanium silicide layer near the edge of the amorphous silicon layer previously formed on the source/drain region. Due to this, firstly, there is a high possibility that the titanium silicide on the source/drain film will be disconnected at the step portion. 3snm titanium film, 70snm amorphous silicon film
When condensed, a titanium silicide film with a thickness of about 95 nm is formed in the source/drain region below the amorphous silicon film, and a titanium silicide film with a thickness of about 86 nm is formed in the source/drain region where there is no amorphous silicon, but the connection between these two regions is The thickness of the titanium silicide film in this area is about 35 nm. Secondly, regardless of whether impurity implantation into the source/drain region is performed before or after the formation of the titanium silicide film, the depth of the diffusion layer formed within the same diffusion layer is uneven because there is a step in the substrate crystalline silicon. Gender arises.

This becomes a problem in maintaining normal operation of the device when not only the gate length but also the source/drain regions need to be miniaturized, such as in a switching transistor for a DRAM cell.

The present invention has been made in view of these points, and is a MOS FET that has good heat resistance, a uniform titanium silicide layer in a fine source/drain region, and a shallow diffusion depth.
The purpose is to provide semiconductor devices based on

Means for Solving the Problems The present invention solves the above problems by completely covering the upper surface and side walls of the gate electrode with an absolute R film in advance, and then depositing a high melting point metal on the entire surface of the silicon substrate. By locally forming an amorphous silicon layer from the top of the gate electrode through the source or drain region to the element isolation insulating film, it has excellent heat resistance mainly due to the reaction between the amorphous silicon and the high melting point metal. A MOSFET Q is formed having a silicide layer and a silicided junction with uniform diffusion depth in the source or drain region.

Function The present invention can be carried out by the method described above, for example, at 900°C and 30°C.
Titanium silicide bonding has excellent resistance to heat treatment for more than a minute, has uniform silicide quality, film thickness, and impurity diffusion depth in the source or drain diffusion region, and has few defects in the substrate crystalline silicon, which is advantageous for fineness. It is possible to obtain a MOSFET having:

Embodiment FIG. 1 is a sectional view of a MOSFET having a titanium silicided junction in one embodiment of the present invention, and FIG. 2 is a sectional view of the process for forming the same.

In FIG. 2A, 1 is p-type substrate crystalline silicon (10
0) and the specific resistance is 1 to 1.5 Ω·Cm. 2 is an oxide film formed for isolation between elements. The upper part of the polycide gate electrode is made up of polysilicon 8 subjected to n-diffusion and tungsten silicide 7 deposited in a physical or chemical atmosphere through an extremely thin gate oxide film 4 (for example, about 10 nm). In order to electrically insulate the gate electrode, an oxide film 5 covering the gate electrode is formed to a thickness of about 20 nm by chemical atmosphere deposition. Using this gate electrode as a mask, the LD region of the n-channel MOS FET (
Phosphorus ion implantation is performed to form an n-diffusion layer 11). Next, in order to electrically insulate the sidewalls of the gate electrode and to configure the LDD structure n-channel MO5FET, an oxide film sidewall with a thickness of about 20 nm is formed using the usual method. Together with the oxide film, a gate electrode covering oxide film 6 is formed (FIG. 2B).

In order to remove the natural oxide film in the source/drain region of the surface of the crystalline silicon 1 of the substrate and to expose the active surface of the silicon, reverse sputtering was performed using argon ions.

Immediately after this, 35 circles of a metal silicon layer 12 is deposited on the entire surface of the substrate crystalline silicon 1 in the same vacuum chamber by DC magnetron sputtering, and then an amorphous silicon layer 13 is deposited on the entire surface by RF magnetron sputtering by continuous vapor deposition in vacuum. It was deposited to a thickness of 73 nm by sputtering (FIG. 2C).

Thereafter, the amorphous silicon layer 13 is shaped on the metal titanium layer 12 by conventional photoresist patterning and dry etching methods. The dry etching conditions at this time are such that the selectivity of the amorphous silicon 13 to the metal titanium 12 is sufficiently high, and the pattern of the amorphous silicon layer 13 is formed from the top of the gate electrode covering oxide film 5 to its sidewalls, source/ It extends through the drain region to the upper part of the element isolation oxide film 2, and covers the entire surface of one source/drain region (FIG. 2D).

Next, the amorphous silicon layer 13 is heat-treated using a lamp annealer that is less affected by residual gas and can introduce nitrogen gas.
The metal titanium layer 12 below is silicided. In the areas of the metallic titanium layer 12 on the oxide film where the amorphous silicon layer 13 is not located above, titanium nitride is formed or unreacted metallic titanium remains.
Titanium/silicide can be selectively removed using O2+H2° solution. In this way, a titanium silicide layer 6 is formed as shown in FIG. 2E. In this state, arsenic ions are implanted at a high dose to form a shallow n+ junction, and the implantation energy at this time is approximately 80 keV. Make sure it's in order. After forming the υ interlayer insulating film 3 by chemical atmosphere deposition, it is deposited in an electric furnace for 90 minutes to activate the implanted impurities and to densify the glabellar insulating film 3.
0'C.

Heat treatment is performed for 30 minutes. Immediately after opening a contact hole in the upper part of the titanium silicide layer 6 in the region of the oxide film 2 for element isolation, an aluminum thin film is deposited by sputtering and patterned to form an aluminum wiring 9 (second Figure F).

If necessary, by performing heat treatment at approximately 450°C in a nitrogen atmosphere mixed with hydrogen gas, damage caused by dry etching during contact hole opening can be recovered, and a titanium silicide junction MOSFET with good electrical characteristics can be obtained. Also, the titanium silicide 6 formed by the reaction between the amorphous silicon 13 formed by sputter deposition and the metal titanium 12 has better heat resistance than the one formed by the reaction with the substrate crystalline silicon, and is heated at 900° C. for about 30 minutes. Even after the heat treatment, no surface roughness due to agglomeration of titanium silicide occurs.

In this example, titanium was used as the high melting point metal, but other materials such as tungsten, molybdenum, and
It is also possible to use tal, cobalt, chromium, nickel, and zirconium. Furthermore, by wiring the titanium silicide layer 6 on the oxide film 2 for element isolation and on the gate electrode covering oxide film 6, the titanium silicide layer 6 becomes the third
It can also be used as wiring. The sheet resistance of this wiring is about 3 Ω/hole when the thickness of the titanium silicide layer is about 80 mm.

Effects of the Invention As described above, the present invention has been developed to provide high heat resistance on a uniform diffusion layer with a shallow junction depth, such as the source/drain of a MOSFET, and to eliminate steps and non-uniformity. In addition to lining the high-melting-point metal silicide layer that does not have any cracks, this extension can function as an inter-element isolation oxide film and a wiring on the gate electrode coating oxide film. This greatly contributes to the manufacturing of devices.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a sectional view for explaining a manufacturing method thereof, and FIG. 3 is a sectional view of a conventional semiconductor device of this type. 1...P-type substrate crystal silicon, 2...
・Inter-element isolation oxide film, 3...Interlayer insulating film, 4.
...Gate oxide film, 5...Gate electrode covering oxide film, 6...Titanium silicide layer, 7...
...Tungsten silicide layer, 8...n
+ type polycon, 9...aluminum wiring, 10...
...n+diffusion layer, 11...n+diffusion layer, 1
2...Metal titanium layer, 13...Amorphous silicon layer. Name of agent: Patent attorney Toshio Nakao and 1 other person1
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Claims (1)

[Claims] When forming a MOSFET whose source or drain region is lined with high-melting metal silicide on a silicon substrate, the upper surface and side walls of the gate electrode are completely covered with an insulating film in advance, and then the high-melting metal is coated on the silicon substrate. After depositing on the entire surface, an amorphous silicon layer is locally formed from the upper surface of the gate electrode through the source or drain region and on the element isolation insulating film, and then heat treatment is performed to cause a silicidation reaction of the high melting point metal. The source or drain region is removed from the upper surface of the gate electrode by removing the unreacted refractory metal and compounds other than the refractory metal silicide by wet selective etching while leaving the refractory metal silicide. A method of manufacturing a semiconductor device in which a coating of high-melting point metal silicide, which is mainly produced by reaction with amorphous silicon, is uniformly formed locally on the element isolation insulating film through the process.