JPS6157709B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, particularly an insulated gate type semiconductor integrated circuit device, and a method for manufacturing the same.

In semiconductor integrated circuit devices (hereinafter referred to as ICs), various circuit elements are formed within a semiconductor substrate made of silicon, and a resistor having a predetermined resistance value is covered on an insulating film provided on the surface of the substrate. It is required to form a garment.

On the other hand, in insulated gate ICs, a technology has been adopted in which the gate electrode of an insulated gate transistor is formed from a polycrystalline silicon layer in order to improve the integration density. It is also proposed to use In addition, with the diversification of circuit functions incorporated on a single semiconductor substrate and the improvement of integration density, the polycrystalline silicon layer can be used as a resistor or wiring with as low a resistance value as possible, or as a wiring with an extremely high resistance value. It is required to use it as a resistor with a

For example, Figure 1 shows one unit cell circuit of a static random access memory (RAM), which is constructed by arranging a large number of such cells horizontally and vertically on the main surface of a single semiconductor substrate. In order to reduce the occupied area and power consumption of the IC, the loads R1 and R2 of the insulated gate field effect transistors T1 and T2 are constructed of extremely high resistance polycrystalline silicon layers, and the power lines are It is proposed that the wiring layer such as No. 3 be formed of a polycrystalline silicon layer having extremely low resistance. In addition, in this case, the above-mentioned wiring or gate electrode is required to have highly accurate dimensions, and it is necessary to make an ohmic connection with the drain regions of transistors T1 and T2, respectively. Therefore, the manufacturing process for realizing such an IC is difficult. The problem is that it gets complicated.

For example, the first
In producing an IC having a memory cell as shown in the figure, problems that arise especially when forming high-resistance polysilicon wiring and relatively low-resistance polysilicon wiring will be explained. One proposed method for forming polysilicon interconnects including high-resistance interconnects is to form a polysilicon thin film with no impurities added to a thickness of 4000 Å by chemical vapor deposition (CVD), at least after forming a gate oxide film. After forming a polysilicon wiring pattern by photo-etching, the entire surface is coated with a CVD method, for example.
A SiO ₂ film is formed, and at least the SiO ₂ film on polysilicon that requires low resistance is removed by photoetching. After that, high concentration impurity layers such as source and drain are formed by ion implantation or thermal diffusion method, and at the same time, the desired resistance is removed. It has been proposed to add impurities to the polysilicon wiring portion as well. Note that the high-resistance polysilicon portion is protected by an oxide film when impurities are added. This method has the following disadvantages, especially when forming a highly integrated memory. This is because it is not possible to preliminarily add impurities to the polysilicon interconnection area where resistance is desired to be as low as possible, such as the word line polysilicon interconnection area 3 in Figure 1. Therefore, it is difficult to achieve the desired low resistance.
For example, if a device with a relatively deep source/drain junction depth of 1 μm is formed using phosphorus as an impurity, the surface resistance of the polysilicon layer will be about 50 Ω/gate, and a shallow junction of about 0.4 μm will be formed using arsenic ions. When formed using implantation, the layer resistance of polysilicon exceeds 100 Ω/hole. If such a high polysilicon wiring layer is used for a RAM word line, for example, at a 4K bit integration level, there will be a delay time of approximately 10 nsec due to the RC time constant, and the same method will cause a 16K bit static
When designing RAM, there is a delay of about 20 nsec., which is inconvenient for high-speed, highly integrated RAM.

Further, the following method has been proposed as another method for achieving both a high-resistance polysilicon wiring layer and a low-resistance polysilicon wiring layer.

That is, at least after forming the gate oxide film,
A polysilicon layer is formed by doping impurities on the entire surface, and the entire surface of this polysilicon layer is subjected to, for example, CVD.
A SiO ₂ film is formed by the method. Thereafter, at least the portions of the SiO ₂ film that require low resistance are removed by photoetching to expose the polysilicon.
Thereafter, a high concentration of phosphorus, for example, is added to the polysilicon using SiO ₂ as a mask. Thereafter, a high-resistance polysilicon wiring layer and a low-resistance polysilicon wiring are formed by photo-etching, the polysilicon portion is subsequently protected with, for example, a thin thermal oxide film, and a source/drain junction is formed by, for example, ion implantation. . It has been found that forming polysilicon wiring using this method has the following problems. That is, in the photoetching process for forming polysilicon wiring, a polysilicon layer to which phosphorus is doped at a high concentration and a polysilicon layer to which no impurity is added or to which an extremely small amount of impurity is added are simultaneously etched to form a pattern. For this etching, a hydrofluoric acid-nitric acid-glacial acetic acid based etching solution or CF ₄ + O ₂ plasma is used, but regardless of whether an etchant or plasma is used, phosphorus must be added to a high concentration. As the amount of impurities added increases, the etch rate of the polysilicon layer becomes 1.2 to 1.6 times faster than that of a polysilicon layer without or with a small amount of impurities added. As a result, when the low-resistance polysilicon etch is finished, the high-resistance polysilicon etch is not yet complete, and when the high-resistance polysilicon etch is finished, the low-resistance polysilicon is 20 to 60% full.
This means that the image has been over-etched. The polysilicon gate, which requires the highest degree of dimensional control accuracy, is overetched to a large extent, resulting in significant dimensional reduction compared to the resist pattern and lower dimensional accuracy, making it difficult to apply to high-density MOS processes. I understood.

As a result of further research and analysis, the inventors of the present invention were able to provide a new manufacturing method and structure that was further improved in the process of forming such high-resistance and low-resistance polysilicon wiring.

The present invention thus provides an improved semiconductor integrated circuit device (IC) having a polycrystalline silicon layer with high resistance and low resistance. The present invention will be explained in detail below.

FIG. 2 is a plan pattern diagram of a semiconductor integrated circuit device obtained by the present invention, and FIG.
The figure is a diagram for explaining the process of manufacturing the semiconductor device shown in FIG. 2.

The dotted line 8 in FIG. 2 indicates the boundary between the thick field oxide film (SiO ₂ film) 11 and the active region on the surface of the semiconductor substrate, the solid line region 9 indicates the polysilicon wiring section, and the dashed line 14 indicates the aluminum (Al). 24 is the connection hole between the semiconductor layer (impurity diffusion layer) formed in the active region and the aluminum wirings 2 and 5, and 13 □× is the semiconductor layer (impurity diffusion layer) and the polysilicon wiring 6. ,9
Also, the overlaid portion 4 of the two-dot chain line area 26, the solid line area, and 9 is a high-resistance polysilicon wiring portion.
Indicates R ₁ and R ₂ .

Also, an insulated gate transistor T1 whose channel portion is the semiconductor substrate surface directly under the solid line portion (polycon wiring portion) 9 that crosses the area surrounded by the dotted line 8;
T2, T3, and T4 are formed.

According to the present invention, such a semiconductor device can be manufactured as follows.

As shown in FIGS. 3 and 4A, by oxidizing the p-type silicon substrate 10 using a silicon nitride film as a mask (not shown), a layer of 1 to 2 μm is formed on the substrate surface other than the active region. Forming a thick field SiO ₂ film 11,
After removing the silicon nitride film, a thin gate oxide film (SiO ₂ film) 1 of approximately 1000 Å is deposited on the exposed substrate surface.
2 is formed, and a portion of this oxide film 12 is removed to form an opening 13. Next, as shown in FIGS. 4B and 5, a polysilicon film 15 doped with an impurity such as phosphorus at a high concentration, preferably at a concentration higher than the solid solubility of the impurity in silicon, is formed on the entire surface of the substrate to a thickness of, for example, 0.2 μm. Deposit to a certain thickness. A method for adding impurities into polysilicon is, for example, growing polysilicon by chemical vapor deposition (CVD) and simultaneously supplying a gas such as PH ₃ to form a phosphorus-doped polysilicon thin film. Alternatively, after forming a polysilicon thin film to which no impurities are added, for example, forming an impurity-doped polysilicon thin film 15 by a thermal diffusion method,
As shown in the figure and FIG. 7A, the impurity-doped polysilicon thin film 15 at least in the portion 16 where the high-resistance polysilicon resistor is to be formed is removed by photoetching. Specifically, the polysilicon portion removed in this step corresponds to the area inside the two-dot chain line 26 in FIG.

After forming the pattern of the highly doped polysilicon layer, as shown in FIGS. 6, 7, and 8, a high resistance polysilicon layer 17 with no impurities added is coated on the entire surface using the CVD method, for example. Form to a thickness of 0.2 μm. As can be seen from the figure, there is no field in the opening 16 of the first polysilicon layer 15.
High resistance polysilicon layer 17 directly on SiO ₂ film 11
However, on the other substrate surface, a high resistance polysilicon layer 17 is superimposed on the low resistance polysilicon layer 15. Note that if the resistance value of the high-resistance portion 17 of polysilicon is the desired value after this step, it may be left as is, but if necessary, a small amount (less than 2×10 ¹³ cm ^-2 ) of impurities such as phosphorus or arsenic may be added. may be added to adjust the resistance value.

Thereafter, as shown in FIGS. 9 and 10A, both polysilicon layers are simultaneously photo-etched to form a polysilicon pattern indicated by the solid line 9 in FIG. As can be seen from FIGS. 10A and 11, which show the cross-sectional structure of polysilicon that has been completed up to this step, the low-resistance wiring portion consists of a polysilicon layer 15 doped with a high concentration of impurities and a polysilicon layer 15 that is not doped with impurities. While the layer 17 is formed of a two-layer structure, the high resistance portion corresponding to the resistors R ₁ and R ₂ is formed only of the polysilicon layer 17 to which no impurities are added.

After completing this step, as shown in FIGS. 10B and 11, at least the portion containing high-resistance polysilicon wiring is Protected with an insulator mask 18 made of SiO ₂ or the like formed by the CVD method, impurity ions are implanted into the source/drain or diffusion layer wiring portions on the substrate surface, or from the P-type substrate 10 by thermal diffusion. N-type impurity-containing semiconductor regions 19, 20, 21 defined by PN junctions
form. For example, regions 19 and 20 are formed by implanting phosphorus or arsenic ions, and regions 21
The region is formed from the phosphorus-doped polysilicon layer 15 by heat treatment.

After this step, by using the normal silicon gate process, we can manufacture polysilicon semi-dynamic integrated circuit elements with high resistance, such as 4K bits and 16K bits.
A bit static type MOSRAM can be manufactured. That is, FIGS. 12, 13 and 14
As shown in the figure, a phosphorus silicate glass film 22 is deposited on the surface of the substrate obtained in this way by CVD, and apertures 24 are formed in the glass film 22 by ordinary photolithography. The metal films 2 and 5 are formed by vacuum evaporation technology and photolithography.

In this way, a memory cell as shown in the second example is obtained.

By employing the manufacturing process according to the present invention as described above, the various drawbacks mentioned above can be overcome and a high-performance IC can be manufactured for the following reasons. First, the low-resistance polysilicon wiring section is formed in advance from a double layer of a polysilicon layer doped with impurities at a high concentration, preferably supersaturated, and a polysilicon layer to which no impurities are added. Due to the heat treatment after forming the drain junction, impurity diffusion occurs between polysilicon.
Sufficiently low resistance is possible, for example, a low resistance wiring layer of 20Ω/hole can be realized with good reproducibility. In addition, when photo-etching the polysilicon wiring part, the low-resistance polysilicon part is formed with a double layer and is therefore thick, and the high-resistance part is formed with a single layer and is thin. Since the etching of the silicon portion can be completed reliably, the dimensions of the channel portion, which are strictly required with dimensional control precision, can also be precisely controlled. Due to overetching of the high-resistance polysilicon wiring part, the wiring width is reduced by about 0.5 to 1.5 μm compared to the dimension of the low-resistance part, and the control accuracy is slightly reduced.
In the memory cell shown in the figure, the precision of the resistance value of the high-resistance portion is not so necessary and is within a sufficiently permissible range.

Although the above explanation was based on the case where low-resistance polysilicon and high-resistance polysilicon wiring were used, the present invention can also be applied to higher-order MOS type integrated circuit devices as shown below without major changes. I can do it.

As a means to improve the functionality of a MOS type integrated circuit device, a polysilicon layer 15 is used as shown in FIG.
Instead, high melting point metals such as molybdenum and tungsten, or compounds of these high melting point metals and silicon, i.e., silicide, are used as the gate metal and wiring 30 to further lower the resistance of the gate electrode and mask the gate metal. Sauce
Manufacturing technologies for MOS transistors and ICs that form drain junctions in a self-aligned manner have been proposed. However, when conventional normal processes are used, it is difficult to make these metal gate MOS processes compatible with technology that uses high-resistance polysilicon for wiring. For example, in a memory cell as shown in FIG. 1, it is desirable to use a high melting point metal such as molybdenum in order to reduce the resistance of the word line shown in 3 and increase the speed, but this is difficult to achieve with conventional technology.

According to the present invention, at least after forming the gate oxide film, a high-melting point metal such as molybdenum or its silicide is first formed by CVD, sputtering, or vapor deposition, and at least a portion requiring high-resistance polysilicon is removed by photoetching. This can be achieved relatively easily by subsequently forming a high-resistance polysilicon layer thereon so as to bridge the metal layer, and then forming a gate electrode wiring and a high-resistance polysilicon wiring part by photoetching. be able to. Although electrode wiring including high-resistance polysilicon wiring can be formed using this method, it is not always easy to connect the gate electrode wiring and the source/drain junction, but it is possible to form an electrode thin film of a high melting point metal such as molybdenum. A polysilicon layer heavily doped with the same impurity or the same group of impurities as the impurity for forming the junction and semiconductor region is formed in advance, and the structure of the low-resistance electrode wiring part is formed using highly doped polysilicon. This can be realized by forming a three-layer structure consisting of a high melting point electrode layer and a high resistance polysilicon layer.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a MOS type static memory cell using a high resistance load, and FIG. 2 is a planar pattern diagram of a semiconductor integrated circuit device of the memory cell shown in FIG. 1 constructed according to the present invention. Figures 3 and 6
9 and 12 are planar pattern diagrams for each step for explaining the method of manufacturing a semiconductor device according to the present invention, and FIG. 4A and FIG. -Viewed sectional view, Figure 5 is a -view sectional view of Figure 3, Figure 7A and Figure 7
Figure B is in Figure 6 at different manufacturing processes.
8 is a sectional view of FIG. 6, FIGS. 10A and 10B are sectional views of different manufacturing processes, and FIG. 11 is a sectional view of FIG. 9.
A sectional view taken along line XI--XI, FIGS. 13 and 14 are respectively sectional views taken from - and - in FIG. 12, and FIG. 15 is a sectional view of essential parts of a semiconductor device according to an embodiment of the present invention. 1...V _DD power line, 2...Data line, 3...
...Word line, 4...Polysilicon high resistance, 5...
V _SS power supply line, 6...MOS transistor, 7
...MOS transistor, 10...Si substrate, 11
...Field part SiO ₂ layer, 12...Gate part
SiO ₂ film, 15...low resistance wiring layer, 17...high resistance polysilicon wiring layer.

Claims (1)

[Scope of Claims] 1. An insulating layer formed on a semiconductor substrate, a low resistance wiring layer formed on the main surface of the insulating layer other than a portion where a high resistance wiring layer is to be formed, and the above low resistance wiring layer. A semiconductor device comprising a high-resistance polysilicon layer formed on a wiring layer and on the exposed insulating layer corresponding to a portion where the high-resistance wiring layer is to be formed. 2. The semiconductor device according to claim 1, wherein the low resistance wiring layer is made of polysilicon heavily doped with impurities. 3. The semiconductor device according to claim 1, wherein the low resistance wiring layer is made of a high melting point metal such as molybdenum or tungsten or a silicide of such a high melting point metal. 4. The above-mentioned patent claim characterized in that the low-resistance wiring layer is composed of a polysilicon layer to which impurities are added at a high concentration and a high-melting point metal layer such as molybdenum or tungsten deposited on the polysilicon layer. The semiconductor device according to item 1. 5. Forming a low resistance film on an insulating layer on a semiconductor substrate, selectively removing at least a portion of the film where a high resistance wiring layer is to be formed, and then removing the exposed insulating layer and the remaining part of the film. A method for manufacturing a semiconductor device, comprising forming a high resistance polysilicon layer on a low resistance film. 6. The method of manufacturing a semiconductor device according to claim 5, wherein polysilicon to which impurities are added at a high concentration is used as the low resistance film. 7. The method of manufacturing a semiconductor device according to claim 5, wherein a high melting point metal such as molybdenum or tungsten or a silicide of such a high melting point metal is used as the low resistance film. 8. The above-mentioned patent claim is characterized in that the low-resistance film is a two-layer film consisting of a polysilicon layer doped with impurities at a high concentration and a high-melting point metal such as molybdenum or tungsten deposited on the polysilicon layer. A method for manufacturing a semiconductor device according to item 5.