JPS59208855A - Structure of wiring - Google Patents

Abstract

PURPOSE:To increase the current capacitance of a wiring while preventing cracks on a final passivation and the migration of an Ag wiring by forming the Ag wiring (an electrode) only on a high current applying section in the heat- resistant metallic wiring in a double heat sink (DHD) type element. CONSTITUTION:A transistor Q3 with a P type base B and an N<+> type emitter E, an N<+> type channel cut-off region 4 and a P<+> type region 5 for a diode Dd are formed to one part of an N type epitaxial layer 2. A palladium/titanium (Pd/Ti) wiring layer 7 constituting a heat-resistant metallic wiring for a section, etc. connecting the emitter E in the transistor Q3 and the P<+> type region 5 for the diode Dd is formed on an SiO2 layer 6. The layer of a silver (Ag) wiring 8 is shaped on the Pd/Ti wiring layer 7 only in the wiring section corresponding to a high current applying section receiving surge currents from a bump electrode 10, the wiring section extending over the P<+> type region 5 for the diode Dd from the emitter E in the transistor Q3, in the Pd/Ti wiring layer 7.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to wiring technology, and more particularly to a technology that is particularly effective when applied to a wiring structure in which heat-resistant metal wiring is formed on a substrate.

[Background technology] In DHD (double heat sink) type elements that are sealed with cylindrical glass at high temperatures, semiconductor devices such as IC Zener diodes, which are made into ICs by providing a temperature compensation circuit etc. in the Zener diode pellet, are Heat-resistant metal wiring that can withstand high temperatures during sealing is required.

Therefore, palladium/
Titanium (Pd/Ti) wiring can be considered.

However, since this P d / Ti wiring has a small current capacity, there are problems such as weak strength against surge current.

Therefore, in order to increase the current capacity of the wiring, Pd/
It is conceivable to form a silver (Ag) wiring over the entire T 2 wiring.

However, in this case, the thermal expansion coefficient of Ag and the CVD film that is the final passivation on the Ag wiring, such as phosphosilicate glass (PSG) M*, is greatly different, so there is a problem that cracks occur in the CVD film. The inventor of the present invention has also revealed that there is a problem in that Ag migration occurs when Ag wiring is provided on all Pd/Ti wiring.

[Object of the Invention] An object of the present invention is to provide a wiring structure that can increase the current capacity of the wiring while preventing cracks in the final bar and migration of Ag.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the Invention] A brief overview of typical inventions disclosed in this application is as follows.

In other words, the A
By forming the g wiring (electrode), it is possible to increase the current capacity of the wiring while preventing cranking of final passivation and migration of the Ag wiring.

Furthermore, by forming polysilicon wiring over the entire surface of the heat-resistant metal wiring, the above object can be achieved and the current capacity of the wiring can be increased while preventing cracks in the final passivation.

[Example 1] FIG. 1 is a partial sectional view showing Example 1 of the wiring structure according to the present invention, and FIG. 2 is a circuit diagram showing an example of an IC circuit to which the wiring structure can be applied.

In this embodiment 1, an N+ type silicon (Si) substrate 1
An N-type epitaxial layer 2 is formed thereon by vapor phase growth.

A part of this N-type epitaxial layer 2 has a P-type heath B.
Transistor Q3 with XN+ type emick E, N+ type channel cutoff region 4, P+ of diode Dd
A mold region 5 is formed.

Further, on the N-type epitaxial layer 2, a 5i02 layer 6 is formed except for the P+ type region of the base B1 emitter E1 diode Dd of the transistor Q3.

Further, on this 5i02 layer 6 is a transistor Q3.
Palladium/titanium (P
d/Ti) wiring layer 7 is formed.

Of this P d / Ti wiring layer 7, the bump electrode 1
Only the wiring part corresponding to the large current application part that receives the surge current from 0, that is, the emitter E of the transistor Q3
A layer of silver (Ag) wiring 8 is formed on the P d /Ti wiring layer 7 only in the wiring portion extending from the P + type region 5 of the diode D'd.

This Ag wiring (electrode) 8 increases the current capacity only in the large current application part and increases the surge strength. By providing this Ag wiring 8, P d / Ti
This prevents the wiring layer 7 from melting due to heat generation and penetrating the 5i02 layer 6 particularly in the channel cut-off region 4 and causing short-circuit defects.

At the same time, since the Ag wiring is provided only partially, the Ag wiring 8 can reduce cranking of the PSG film 9, which is final passivation, and can prevent Ag migration.

A specific example of a large current application portion where the Ag wiring 8 is provided is shown in FIG. 2.

That is, the circuit shown in FIG. 2 is an example of a temperature-compensated monolithic Zener IC circuit, and includes three Zener diodes ZD, resistors R1, R2, R3, R4, and a transistor Q1.
, Q2, Q3, and a dummy diode Dd.

This diode Dd is connected to a diode Z between terminals 3 and 10.
When applying a voltage that forward biases D and Dd,
It is provided in order to obtain the forward characteristic of a diode when viewed from the terminal 3.10. Note that the terminal 3 is a substrate electrode provided on the back surface of the substrate 1.

In this IC circuit, the large current application part is the transistor Q
This is a wiring section 11 (indicated by a broken line) extending from the emitter of No. 3 to the negative input terminal section 10, and in this wiring section 11, an Ag wiring 8 is provided on the P d / Ti wiring N7.

That is, the maximum current that flows in this circuit when a surge voltage is applied is the current that flows to the emitter of transistor Q3.

This is because this current flows through the three transistors Q1 and Q2.
, Q3 (multiplyed by each hFE), resulting in a very large current.

[Example 2] FIG. 3 is a partial cross-sectional view showing Example 2 of the wiring structure according to the present invention.

In this embodiment, a 5i02 layer 6 is provided at a predetermined portion of an N-type epitaxial layer 2 formed on an N+ type silicon substrate 1, and a Pd/Ti wiring layer as a heat-resistant metal wiring is provided on this 5i02 layer 6. The point where 7 is formed is the first
This embodiment is substantially the same as the embodiment 1 shown in the figure.

In the second embodiment, a polysilicon layer 12 is provided on the entire surface of the Pd layer of the Pd/Ti wiring layer 7.

This polysilicon layer 12 is intended to increase the current capacity of the wiring, to prevent step disconnections in the Pd/Ti wiring layer 7, and to avoid widening the wiring to obtain a fine structure. . In addition, Pd has a relatively low temperature, for example, 600℃.
Although the polysilicon layer 12 is sublimated at a temperature of approximately .degree.

Furthermore, during heat treatment after the polysilicon layer 12 is formed, Pd diffuses into the lower layer of the polysilicon layer 12 to form a Pd diffusion layer 12a, which improves the conductivity of the polysilicon layer 12 and increases the current capacity. Can be increased.

Note that it is more desirable for the polysilicon layer 12 to have a large amount of doping in order to increase the current capacity. For example, if it is an N type, it is better to have a large amount of phosphorus (P), and if it is a P type, it is better to have a large amount of phosphorus (P). The one that contains a lot of B) is good.

Note that this wiring is connected to the wiring section 11, Q in FIG.
The wiring between the base of 3 and the emitter of Q2, the wiring between the base of Q2 and the emitter of Ql, and the wiring between R2, Q
It is suitable to use it as a wiring between the base of 1 and R2 and between ZD.

[Effects] (1) By forming silver wiring only on the large current application part of the heat-resistant metal wiring formed on the substrate, cranking of final passivation and silver migration are prevented, and the current capacity of the wiring is reduced. can be increased and the surge strength can be improved.

(2) By forming polysilicon wiring over the entire surface of the heat-resistant metal wiring formed on the substrate, it is possible to prevent cranking of the final passivation, increase the current capacity of the wiring, and improve surge strength. can.

(3) By forming silver wiring or polysilicon wiring,
Can prevent step breakage.

(41, By forming #I wiring or polysilicon wiring, current capacity can be increased without expanding the wiring, so
Miniaturization is easily possible.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the Examples and can be modified in various ways without departing from the gist thereof. Nor.

For example, as a heat-resistant metal wiring, P d / Ti
In addition to wiring, wiring metals such as aluminum (At) and gold (Au) may be used, and tungsten (W), chromium (Cr), molybdenum (MO), platinum (Pt) and other metals for forming a Schottky barrier may be used. Metals can also be used instead of the P d /Ti layer and overlaid with polysilicon or silver.

[Field of Application] In the above explanation, the invention made by the present inventor was mainly applied to the field of application, which is the background of the invention, which is an IC Zener diode. It can be applied to all IC circuits using heat-resistant metal wiring.

[Brief explanation of the drawing]

FIG. 1 is a partial cross-sectional view showing a first embodiment of a wiring structure according to the present invention, FIG. 2 is a circuit diagram showing an example of an IC circuit to which the same can be applied, and FIG. 3 is a partial cross-sectional view showing a second embodiment of a wiring structure according to the present invention. FIG. l...Silicon substrate, 2...N type epitaxial N
, Qt, Q2, Q3... Transistor, 4... Channel cut-off region, 5... P+ type region of diode, 6... SiO2 layer, 7... Palladium/titanium (Pd/ Ti) Wiring layer (heat-resistant metal wiring)
, 8... Silver (Ag) wiring, 12... Polysilicon layer (polysilicon wiring), 12a... Pd diffusion layer. , f-4 Figure 1 Figure 2 Figure 3

Claims (1)

[Scope of Claims] 1. A wiring structure characterized in that a silver wiring is formed only on a large current application portion of a heat-resistant metal wiring formed on a substrate. 2. The wiring structure according to claim 1, wherein the heat-resistant metal wiring is made of palladium/titanium wiring. 3. A wiring structure characterized in that a polysilicon wiring is formed on the entire surface of a heat-resistant metal wiring formed on a substrate. 4. The wiring structure according to claim 3, wherein the heat-resistant metal wiring is made of palladium/titanium wiring.