JPH0330363A - Semiconductor integrated circuit device with input-output protective circuit - Google Patents

Abstract

PURPOSE:To prevent the heat-generation breakdown of current-limiting resistor resistor itself even when comparatively large feedthrough currents flow by making the resistance value of a second resistor lower than that of a first resistor and forming the second resistor in a high melting-point silicide resistance film as the compound of a high melting-point metal and silicon. CONSTITUTION:When abnormal voltage is applied to input-output terminals, feedthrough currents are made to flow through a voltage-limiting diode D through a first resistor 12 and a second resistor 13 in parallel connection. Since the resistance value of the second resistor is made lower than that of the first resistor 12, the greater part of feedthrough currents are made to flow through the second resistor 13, but the possibility of the breakdown of the second resistor is reduced even when a calorific value by feedthrough currents is large because the second resistor 13 is composed of a high melting-point silicide resistance film as the compound of a high melting-point metal and silicon and has heat resistance. Accordingly, the breakdown of current-limiting resistor itself due to heat generation with feedthrough currents can be prevented without decreasing the speed of response of a circuit.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device equipped with an input/output protection circuit that protects internal circuits from static electricity, surges, etc. Concerning the structure of

[Conventional technology]

2. Description of the Related Art Semiconductor integrated circuits, which are constructed by forming a large number of transistors, diodes, etc. on a silicon substrate and connecting them to each other, have become increasingly complex as device sizes have become smaller. As the device size decreases, for example in the case of MO5FET (insulated gate field effect transistor), the thickness of the gate oxide film becomes thinner due to the scaling law, and the junction depth between the source and drain becomes shallower. In such a case, a reduction in withstand voltage for external input/output becomes a problem. That is, gate oxidation, lI! !
! As the material becomes thinner, the human power withstand voltage decreases due to dielectric breakdown. Further, as the junction depth of the source/drain becomes shallower, the curvature at the junction surface becomes steeper, so that the t1 junction breakdown voltage decreases, and when the source/drain is used as an output terminal, the breakdown voltage decreases. Such a reduction in breakdown voltage poses a problem with respect to static electricity or surges.

Destruction caused by static electricity occurs when a charged human body directly touches a semiconductor element or its input/output terminals, or when static electricity is generated due to friction between objects after packaging, and high voltage is instantaneously applied to the input/output terminals. Occurs due to

Therefore, conventional semiconductor integrated circuit devices are provided with input/output protection circuits that prevent the application of abnormal voltages to the manual stage and the output stage.

Figure 7(a) shows the human power (protection circuit 1 and output protection circuit 2) applied to the MO3FET circuit, and Figure 7(b) shows the pn
Figure 3 shows a human power protection circuit 3 applied to a p-bi, Dora transistor circuit. In both protection circuits 1.23, the input and output of the internal circuit is connected to the voltage limiting diode D1 inserted between the power supply.
~D6, and the current limiting resistors R and -L inserted between its input/output and the input/output terminal lN10UT.
S and D are parasitic diodes. This protection circuit 1
, 2.3, when an abnormal voltage exceeding the human power and output voltage range of the device operation standard is applied to the input/output terminal lN10UT, the excess voltage is transferred to the power supply side (including the ground side) by the voltage limiting diodes D1 to D. In addition, the through-current that flows when bypassing the excessive voltage of the voltage-limiting dimates D1 to D6 is limited by the current-limiting resistors R1 to R1, and the through-current associated with the through-current is This prevents diode junction breakdown due to heat generation. As the current limiting resistors R and -L, it is known that a diffused resistor is used (in this case, a diode can be added parasitically) and a polycrystalline silicon resistor is used.

[Problem to be solved by the invention]

However, in the above input/output (id 81 circuit), if the resistance values of the current limiting resistors R to R0 are increased in order to suppress the through current, the response speed in the circuit will become slower.On the contrary, if the response speed is increased Therefore, if the resistance values of the current limiting resistors R1 to R3 are made small, the through current cannot be reduced, and not only the junctions of diodes D and -D6 are destroyed due to heat generation, but also the current limiting resistors R1 to R1 themselves are destroyed due to heat generation. As a result, internal circuits such as the input/output terminal 1N10UT are separated, causing permanent damage to the circuit.

Therefore, the object of the present invention is, firstly, to prevent the current limiting resistor itself from being destroyed by heat generation even if a relatively large through current flows, and secondly, to reduce the junction breakdown of the voltage limiting diode itself, so that the circuit An object of the present invention is to provide a semiconductor integrated circuit device equipped with an input/output protection circuit that does not reduce response speed (and has improved destruction resistance of the input/output protection circuit itself).

[Means to solve the problem]

In order to solve the above problems, the measures taken by the present invention are as follows: First, the current limiting resistor of the input/output protection circuit is composed of a first resistor and a second resistor in parallel with the first resistor; The resistance value of the resistor is made lower than that of the first resistor, and the second resistor is made of a high melting point silicide resistance film made of a compound of a high melting point metal and silicon. Further, a second means taken by the present invention is that when the first resistor is made into one conductivity type region of the voltage limiting diode as a diffused resistor layer, the high melting point silicide resistor film serving as the second resistor is A meandering pattern is formed on the resistance layer. Furthermore, a third means is that when the first resistor is a polycrystalline silicon resistive film formed in a meandering manner on an insulating film, a high melting point silicide resistive film, which is the second resistor, is formed on the polycrystalline silicon low resistive film. The coating is formed along the In addition, a fourth measure taken by the present invention is to provide a low concentration region of one of the conductivity types between the pn junctions constituting the voltage limiting diode.

[Effect]

According to the first means, when an abnormal voltage is applied to the input/output terminal, a through current flows through the voltage limiting diode via the first resistor and the second resistor connected in parallel. Since the resistance value of the second resistor is lower than that of the first resistor, the through current flows through the second resistor. Since it is a melting point silicide resistive film and has heat resistance, the risk of destruction of the second resistor is reduced even when the amount of heat generated by through current is large.

In the second method, since the second resistor, which is a high melting point silicide resistive film, is formed in a meandering manner on the diffused resistive layer whose first resistor is one conductivity type region of the voltage limiting diode, the high melting point silicide Although it has a low resistivity, it can be relatively freely set to a predetermined resistance value, and the second
The area occupied by the resistor can be reduced.

In the third means, in order to reduce the occupied area,
A polycrystalline silicon resistance film, which is a first resistance film formed in a meandering manner on an insulating film, is coated with a second resistance film, which is a high melting point silicide resistance film, so that the first resistance does not melt or melt. Even if a crank occurs, the first resistor, which covers the first resistor in a fail-safe manner, absorbs the through-current and bypasses it. do not have.

Furthermore, according to the fourth means, since the low concentration region is interposed between the pn junctions of the voltage limiting diode, the electric field strength at the junction surface is relaxed, Ti flow concentration is less likely to occur, and junction breakdown is prevented. In addition, since the low concentration region itself has resistance, the through current can be suppressed.

〔Example〕

Next, embodiments of the present invention will be described based on the accompanying drawings.

FIG. 1(a) is a vertical sectional view showing the semiconductor structure of an input/output protection circuit according to a first embodiment of the present invention.

In the figure, a field oxide film 11 is formed on an n-type semiconductor substrate 10.
A p-type diffusion layer 12, which serves both as an anode region of a voltage limiting diode and a diffusion resistance layer, is formed in the non-forming region. A high melting point silicide resistance film 13 made of a compound of a high melting point metal and silicon is formed on this p type diffusion layer 12. One end of the high melting point silicide resistive film 13 is connected to the input/output terminal lN10UT via an aluminum wiring 18a that is in conductive contact through a contact hole, and the other end is connected to the aluminum wiring 1 that is in conductive contact through a contact hole.
It is connected to the internal circuit via 8b. Note that 14 is an interlayer insulating film, and 15 is a bancivation film.

The equivalent circuit of such an input/output protection circuit is, as shown in FIG. , the cathode region is composed of an n-type semiconductor substrate 1), a p-type diffusion layer 12 as a high resistance inserted between the input/output 16 and the input/output terminal lN10UT, and a low resistance layer in parallel thereto. High melting point silicide resistance film 13
It is equipped with the following.

In this embodiment, the resistance value of the high melting point silicide resistive film 13 is about 1Ω, and the p-type expansion vI1. The resistance value of the layer 12 is 30 to 100Ω. Therefore, the resistance value of the parallel combined resistor as the current limiting resistor is approximately the p-type expansion layer 12
The resistance value is close to that of . Therefore, it is possible to limit the through current with a large resistance value, and since most of the through current flows through the high melting point nolicide resistive film 13, most of the Joule energy is transferred to the high melting point nolicide resistive film 13. consumed. As a result, the high melting point/reside resistive film 13 generates heat, but since it is originally made of a high melting point material, it does not melt or break like silicon-based resistors or junctions, and the abnormal voltage of the current limiting resistor The heat resistance against the application of is improved.

Next, the above input/output protection circuit structure! ! The construction method will be explained with reference to Figure 2. First, after forming a silicon nitride (S13N4) film on the entire surface of the n-type semiconductor substrate 10,
As shown in FIG. 2 (al), a silicon nitride mask 20 is left as a selective oxidation mask only in the region where impurities are to be introduced by vacuuming, and the rest is removed.
Figure 2(b) due to l. or pyrogenic oxidation.
As shown in FIG.
form at a time. At this time, the oxidation reaction is suppressed directly under the silicon nitride mask 20. Thereafter, the silicon nitride mask 20 is removed, and then boron (B) ions are implanted. The dose 1 at this time is determined in consideration of the forward ON voltage and reverse breakdown voltage of the voltage limiting diode D to be formed later, and the resistance value of the n-type diffusion layer 12. Next, heat treatment is performed at 900 to 1000°C in a diffusion furnace (Fig. 2 FC).
As shown in FIG. 2, an n-type diffusion layer 12 is formed as a diffused resistor and an anode region. Next, various processes are performed to form other devices on the same substrate. In this process,
An oxidation process may be performed on the region above the n-type diffusion layer 12, but it needs to be covered with an oxide film or resist to prevent impurity introduction. After forming various devices, an interlayer insulating film is applied to a thickness of 1000 mm or more before the aluminum deposition process.
It will be thin and fully formed for about 2,000 people. Thereafter, the oxide film and the interlayer insulating film only in the region above the p-type diffusion region 12 are etched away by patterning, and the n-type diffusion layer 12 is exposed.

Next, a high melting point metal is formed on the entire surface. In this case, a vapor deposition or sputtering method is used, and the high melting point metal is Ta.
, Ti, W, Ni, lAo, Pt, Pd, etc. are used. In addition, W,! , Io, it is possible to selectively deposit them by converting them into a halogen compound gas and decomposing them by CVD. After the high melting point metal is deposited, heat treatment is performed at 300-8(]0°C.

However, in the case of Mo, the heat treatment is performed at about 1200°C. As a result, only the metal on the back n-type diffusion layer 12 of the high melting point metal film reacts with the underlying silicon to form a high melting point silicide film as a compound. On the other hand, the metal on the interlayer insulating film remains unchanged even by heat treatment under the above-mentioned temperature conditions and remains as a metal. The high melting point silicide thus formed has excellent heat resistance and has a melting point of 1,500 to 2,000° C., which is higher than that of silicon. In addition, the high melting point silicide film has excellent chemical resistance, such as HF+HNO3, H2SO1+H, [1,
It is only etched by mixed acids such as. Therefore, when the above wafer is treated with an acid such as 11C1,
As shown in FIG. 2(d), all of the metal film except on the p-type expansion layer 12 is etched away, and the interlayer insulating film 14a is etched away.
is exposed, and the high melting point silicide resistive film 13 remains only on the n-type diffusion layer 12. The composition of the silicide resistive film 13 changes depending on the heat treatment time. The specific resistance of the silicide resistive film 13 can be changed by changing the composition ratio of high melting point metal and silicon, but when considering the stability, it is preferable that the ratio of high melting point metal to silicon is about 0.5. .

Next, as shown in FIG. 2(e), an interlayer insulating film 14 is again formed over the entire surface of the wafer. Then buttering 2
Contact holes for aluminum wiring are opened by etching. A contact hole is also formed on the high melting point silicide resistance film 13 in order to use it as a resistor. next,
An aluminum or aluminum-silicon alloy film is formed on the entire surface and patterned into a desired pattern as shown in FIG. 2(f).

Aluminum interconnections 18a and 18b are formed by etching, and then a hanonvation film 15 such as a silicon nitride (S13N4) film is formed over the entire surface. Note that the formation of the input/output protection circuit structure described above can be performed simultaneously with the formation process of the internal circuit.

FIG. 3(a) is a longitudinal sectional view showing a semiconductor structure of an input/output protection circuit according to a second embodiment of the present invention, and FIG. 3(b) is a plan view of the same structure. In FIG. 3, the same parts as those shown in FIG. 1 are given the same reference numerals, and their explanations will be omitted. This embodiment shows an input/output protection circuit that protects internal circuits against abnormal positive and negative voltages, and
An n-type diffusion layer 12 and an n-type diffusion layer 22 in the p-well layer 21 are formed on the O layer. The junction between the n-type diffusion layer 12 and the n-type semiconductor substrate 10 constitutes a current limiting diode D in the equivalent circuit shown in FIG. The junction constitutes current limiting diode D2 in FIG. 3(C). Note that the n-type semiconductor substrate 10 is connected to the power supply v1. LD, and the p well layer 21 is connected to the p"contact region 2.
1a and the power supply 3.1 through the aluminum wiring 21b. It is connected to the. The p-type diffusion region 12 and the n-type diffusion region 22 are separated from each other by a field oxide film 11 having a thickness of about 1 μm. The n-type diffusion layer 12 is shown in Figure 3 (
Meandering high melting point silicide resistive film 23 as shown in b)
is formed, and a meandering high melting point silicide resistance film 24 is also formed on the n-type diffusion layer 22. Here, since the silicide film has a sheet resistance of about several to several tens of Ω/hole, the current limiting resistance is 30 Ω to 1000 Ω.
To obtain the value of , a certain length is required for the shape. Therefore, the high melting point silicide resistance films 23 and 24 have a meandering pattern.

One end of the high melting point silicide resistance film 23 on the p-type expansion layer 12 is connected to the input/output pad 25 via the aluminum arrangement 18a on the interlayer insulating film 14, and the other end is connected to the n-type via the aluminum wiring 26. It is connected to one end of the high melting point silicide resistance film 24 on the diffusion layer 22 . The other end of the high melting point silicide film 24 is connected to an internal circuit via an aluminum wiring 27.

An input/output protection circuit with such a structure is shown in Figure 3 (C
). That is, a voltage limiting diode D1. Da is inserted, and between the input/output terminal 16 and the input/output terminal lN10UT, an n-type diffusion layer 12. A parallel resistance consisting of the n-type diffusion layer 22 and high melting point silicide resistance films 23 and 24 is inserted. Here, the p-type expanded ik layer 12 constituting the voltage limiting diodes D and D2 is
．． The n-type diffusion layer 22 has a sheet resistance of several hundred to several thousand ohms/hole, and when the shape of the diode is taken into account, the resistance value is several hundred to several thousand ohms. The parallel resistance as a current limiting resistor that should limit the through current is a high melting point silicide resistor film 23, 24 of 30 to 100 ohms and an n-type diffusion layer 12, 24, which is a diffused resistance of several hundred to several thousand ohms. Since it is composed of an n-type diffusion layer 22, when an abnormal voltage is applied to the input/output pad 25, most of the through current is shunted to the high melting point silicide resistive film 23, 24, resulting in energy consumption accompanied by heat generation. However, since the high melting point silicide resistance films 23 and 24 have high heat resistance,
It will not be destroyed by melting due to heat generation. n-type diffusion layer 12 as a diffusion resistance. The formation of the high melting point silicide resistance films 23 and 24 on the n-type diffusion layer 22 can be realized without adding a photo process, as in the first embodiment, and the formation of the high melting point silicide resistance films 23 and 24 on the n-type diffusion layer 22 can be realized without adding a photo process.
Since it is superimposed on 22, the silicide resistive film 2
The additional formation of 3.24 does not result in an increase in the occupied area,
It is possible to prevent permanent damage to the input/output protection circuit itself due to melting while maintaining the degree of integration.

FIG. 4(a) is a longitudinal sectional view showing a semiconductor structure of an input/output protection circuit according to a third embodiment of the present invention, and FIG. 4(b) is a plan view of the same structure.

In this embodiment, a polycrystalline silicon resistance film 30 is used as one of the parallel-connected resistors serving as the current limiting resistance, and a high melting point silicide resistance film 31 covering the polycrystalline silicon resistance film 30 is used as the other resistance. This is what I used. n
A fourth layer is formed on the field oxide film 33 on the type semiconductor substrate 10.
The meandering polycrystalline silicon resistor 11j shown in Figure (b)! 3
0 is formed. This polycrystalline silicon resistive film 30 is used when forming various devices of the inner circuit, for example, MOSFET.
It is formed simultaneously with the process of forming the gate electrode. Since polycrystalline silicone itself has a sheet resistance of several tens of ohms/hole, the required resistance value as a current limiting resistor is about 30 to 1000 ohms, so a meandering pattern is used to increase the resistance value. Meandering polycrystalline silicon resistive film 30.
A high melting point silicide resistance film 31 is coated on top. The high melting point silicide resistive film 31 can be formed by depositing a high melting point metal on the entire surface including the polycrystalline silicon resistive film 30 by vapor deposition or sputtering, as in the previous embodiment.
Alternatively, a high melting point metal is selectively deposited only on the contact hole and the polycrystalline silicon resistance film 30 by a CVD method,
Then, heat treatment is applied to silicide, and the metal film other than the contact hole and the polycrystalline silicon resistive film 30 is etched away.

Such a current limiting resistor consists of a polycrystalline silicon resistive film 30 and a high melting point silicide resistive film 31, as shown in FIG. 4(C).
It becomes a parallel combined resistance. High melting point silicide resistance film 31
Compared to the polycrystalline silicon resistive film 30, the sheet resistance is the same or about 50% lower. Therefore, the through current flowing through the high melting point silicide resistive film 31 having high heat resistance is equal to or greater than that flowing through the polycrystalline silicon resistive film. Note that since the parallel combined resistance value is smaller than the individual resistance value, the shape of the resistive film may be adjusted so that the combined resistance value becomes the desired value, or a high melting point silicide resistor may be added on the polycrystalline silicon resistive film 30. The film may be formed discontinuously.

In that case, it is preferable to form a high melting point silicide resistance film at the bent portion of the meandering polycrystalline silicon resistance film 30.

In this way, compared to the conventional case where only a polycrystalline silicon film is used as a current limiting resistor, the structure has more margin against blowout due to through current.

Polycrystalline silicon resistive film 30 due to discontinuity of grain boundaries, etc.
In a state in which cracks are likely to occur, the polycrystalline silicon resistive film 30 is likely to be blown out by application of an abnormal voltage. However, in this embodiment, since the high melting point silicide resistive film 31 covers the polycrystalline silicon resistive film 30, the electric field concentration at the polycrystalline silicon defect portion is reduced, and even if the polycrystalline silicon is blown out, it will not be blown out. Since the polycrystalline silicon particles separated from each other remain electrically connected to each other via the high melting point silicide resistance film 31, there is an advantage that permanent destruction does not occur.

FIG. 5 is a longitudinal sectional view showing a semiconductor structure of an input/output protection circuit according to a fourth embodiment of the present invention. This example uses field oxidation Il! ! Polycrystalline Noricon resistance film 30 on 11
high melting point silicide resistance film 31 covering p-type expansion layer 12 and high melting point silicide resistance film 2 on p-type expansion layer 12 and n-type expansion layer 22
3.24. If the resistance of the high melting point silicide resistive film 31 on the polycrystalline silicon resistive film 30 cannot be ensured sufficiently and the 1Xj current flowing through it is excessive, the high melting point silicide resistive film on the diffusion layer 12. 2
By adding 3.24 in series, the 5 current can be suppressed, and permanent damage due to through current can be effectively prevented.

FIG. 6(a) is a longitudinal sectional view of a semiconductor structure of a human power protection circuit according to a fifth embodiment of the present invention.

This embodiment differs from the second embodiment shown in FIG. 3(a) in that a low-concentration p-type expanded layer is formed between the p-n junction between the n-type semiconductor substrate 10 and the p-type expanded layer 12 constituting the voltage limiting diode. layer 4
1, as well as the p-well layer 21 and the n-type expansion layer 22.
A low concentration n-type diffusion layer 42 is inserted between the pn junction and the pn junction. For example, the low concentration p-type diffusion layer 41 is shown in FIG.
As shown in FIG. 6(C), a planar pattern surrounding the p-type diffusion layer 12 may be adopted, or as shown in FIG. A covering planar pattern may also be used. Due to the presence of the low concentration p-type diffusion layer 41 and the low concentration n-type diffusion layer 42, when a through current flows through the voltage limiting diode due to the application of an abnormal voltage, the electric field concentration at the pn junction surface is alleviated, and the current Concentration becomes less likely to occur, and destruction of the voltage limiting diode itself is prevented. Also, a low concentration p-type diffusion layer 12
Since the n-type diffusion layer 22 itself functions as a type of resistance, it has the effect of suppressing the through current itself.

〔Effect of the invention〕

As explained above, the present invention uses a parallel composite resistor consisting of a first resistor and a second resistor as a current limiting resistor inserted between an input/output and an input/output terminal, and the resistance value of the second resistor is Since this resistor is characterized in that it is lower than that of the first resistor and that the second resistor is formed as a high melting point silicide resistive film, the following effects are achieved.

■The through current caused by the application of abnormal voltage can be shunted to the heat-resistant high melting point silicide resistive film.
It is possible to prevent the current limiting resistor itself from being destroyed due to the heat generated by the through current without reducing the circuit response speed.

■If the first resistor is a sales promotion resistor layer that also serves as one conductivity type region of the voltage limiting diode, and the second resistor is formed in a meandering manner on the diffused resistor layer,
The area occupied by the input/output protection circuit can be reduced.

■Also, when the first resistor is a polycrystalline silicon resistive film formed in a meandering manner on an insulating film, and the second resistor, which is a high melting point solicide, covers the polycrystalline silicon resistive film along the polycrystalline silicon resistive film. Even when the polycrystalline silicon resistive film is fused due to a crank, etc., the high melting point metal silicide resistive film provides electrical continuity between the polycrystalline silicon that is separated from the other.
As a fail-safe, permanent damage does not occur, contributing to improved reliability.

■If a low concentration region of either conductivity type is formed between the pn junction of the voltage limiting diode,
The concentration of electric field in the n-junction can be alleviated, the breakdown voltage of the junction can be improved, and since the low concentration region itself has resistance, the effect of suppressing through current can also be exhibited.

[Brief explanation of drawings]

FIG. 1(a) is a vertical sectional view showing the semiconductor structure of an input/output protection circuit according to a first embodiment of the present invention, and FIG. 1(b) is an equivalent circuit diagram of the same input/output protection circuit. FIGS. 2(a) to 2(f) are longitudinal sectional views for explaining the manufacturing process of the semiconductor structure of the input/output protection circuit. FIG. 3(a) is a vertical cross-sectional view showing the semiconductor structure of the input/output protection circuit according to the second embodiment of the present invention, FIG. 3(b) is a plan view of the same structure, and FIG. ) is an equivalent circuit diagram of the input/output protection circuit. FIG. 4(a) is a longitudinal sectional view showing the semiconductor structure of the input/output protection circuit according to the third embodiment of the present invention, FIG. 4(b) is a plan view of the same structure, and FIG. ) is an equivalent circuit diagram of the same input/output protection circuit. FIG. 5 is a longitudinal sectional view showing a semiconductor structure of an input/output protection circuit according to a fourth embodiment of the present invention. FIG. 6(a) is a vertical sectional view showing the semiconductor structure of the input/output protection circuit according to the fifth embodiment of the present invention, and FIG. 6(b), (C
) is a plan view showing a planar Bakun of a low concentration p-type expansion layer in the same structure. Figure 7(a) is a circuit configuration diagram showing a human power protection circuit and an output protection circuit applied to a MOS FET circuit, and Figure 7(b) is a circuit diagram showing a human power protection circuit applied to a PNP transistor circuit. FIG. 10- N-type semiconductor substrate, 11.33 Field oxide film, 12- P-type diffusion layer (expanded resistance layer, anode region), 13, 23.24.31 High melting point silicide resistance film, 141@bl lament, 15 passivation film,
21 p-well layer, 22- n-type expansion layer (diffused resistance layer,
cathode region), 30 polycrystalline silicon resistance film, 41
Low concentration Vo. Figure 1 Section 2 255 input/output rose (C) Figure Section X30 Polycrystalline silicon resistor. Figure No.

Claims (1)

[Claims] 1) An input/output protection circuit including a voltage limiting diode inserted between the input/output of an internal circuit and a power supply, and a current limiting resistor inserted between the input/output and the input/output terminal. In the semiconductor integrated circuit device, the current limiting resistor includes a first resistor and a second resistor in parallel with the first resistor, the second resistor has a resistance value lower than that of the first resistor, and the second resistor has a resistance value lower than that of the first resistor; 1. A semiconductor integrated circuit device equipped with an input/output protection circuit, wherein the resistor is a high melting point silicide resistance film made of a compound of a high melting point metal and silicon. 2) The first resistor is one conductivity type region of the voltage limiting diode as a diffused resistance layer, and the second resistor is formed in a meandering manner on the diffused resistance layer. A semiconductor integrated circuit device comprising the input/output protection circuit according to item 1. 3) A claim characterized in that the first resistor is a polycrystalline silicon resistive film formed in a meandering manner on an insulating film, and the second resistor covers the polycrystalline silicon resistive film along the polycrystalline silicon resistive film. A semiconductor integrated circuit device comprising the input/output protection circuit according to item 1. 4) A semiconductor integrated circuit device equipped with an input/output protection circuit according to claim 1, wherein the voltage limiting diode includes a low concentration region of one of the conductivity types between the pn junctions.