JPS6245161A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To protect resistance element from breakdown caused by curernt concentration and improve reliability of an IC by connecting a plurality of the straight resistance elements with conductive layers composed of different material from the resistance material. CONSTITUTION:A field insulating film 2 is provided on a P<-> type semiconductor substrate 1 and an N-channel type MISFET 4, an N-channel tpe clamping MISFET 5, resistance elements 6 and a bonding pad 7 are formed on it. Conductive layers 8 are connected to them through contact holes 9. The resistance element 6 are composed of polycrystalline silicon layers and arranged linearly and connected in series with conductive layers 8E. Therefore, curved parts are eliminated from individual resistance elements 6 and current concentration can be avoided so that the breakdown of the resistance elements can be avoided and the reliability of the IC can be improved.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a resistive element, and particularly! IL,
The present invention relates to techniques that are effective when applied to resistance elements of conductive integrated circuit devices.

[Background Art] In a MIS type semiconductor integrated circuit device represented by a semiconductor integrated circuit device equipped with a MOSFET, generally an input protection device including a switching element such as a resistive element and a diode on a bonding pad, particularly an input bonding pad. The circuit is connected. Excessive voltage applied to the input terminal? This is to prevent destruction of the semiconductor element due to Yt gas energy.

In order to reduce the area occupied by the resistive element of the input protection circuit and obtain a predetermined resistance value, it is conceivable to form the resistive element in a meandering shape. However, the inventor has discovered that the meandering resistance element is destroyed by excessive electrical energy.
I discovered something.

This is because the current concentrates on the curved portion of the resistance element.

Regarding the technology to prevent the destruction of semiconductor elements due to excessive electrical energy, for example, Japanese Patent Application No. 1529-1980
It is described in No. 98.

[Object of the Invention] An object of the present invention is to provide a technique for improving the reliability of a semiconductor integrated circuit device.

Another object of the present invention is to provide a technique for increasing the resistance value of a resistor element and improving the degree of integration of a semiconductor integrated circuit device.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the Invention] A brief overview of typical inventions disclosed in this application is as follows.

That is, a plurality of linear resistance elements are connected in series through a different conductive layer.

Hereinafter, the configuration of the present invention will be explained along with examples.

[Example 1] Figure 1 is a plan view of the input protection circuit of a conductor integrated circuit device, Figure 2 is a sectional view taken along the line A-A in Figure 1,
The figure is a sectional view taken along the line BB in FIG. 1. Note that insulating films other than the field insulating film are not shown in FIG. 1 in order to make the structure easier to see.

1 to 3, reference numeral 1 denotes a P-type semiconductor substrate, and a field insulating film 2 made of a silicon oxide film is formed on the surface of the substrate.
is the provision. Further, a P-type channel stopper region 3 is provided below the field insulating film 2.

4 is an N-channel type MISFET, 5 is an N-channel type clamp MTSFET, 6 is a resistance element, and 7 is a bonding pad, and a conductive layer 8 made of an aluminum layer connects them.

It is through the connection hole 9. Resistance element 6 and M for clamp
Construct an input protection circuit for semiconductor integrated circuit devices with I5FET5! It's empty. Details will be described later.

The N-channel type MI 5FET4 is of n+ type! conductor region 10. It is composed of a gate insulating film 11 and a gate electrode 12. The n+ type semiconductor region 10 is.

It is formed by introducing n-type impurities such as phosphorus (P) and arsenic (As) into the surface of the semiconductor substrate 1. The gate insulating film 11 is made of silicon oxide formed by oxidizing the surface of the semiconductor substrate 1. The gate electrode 12 is made of a polycrystalline silicon layer containing n-type impurities such as phosphorus and arsenic. However, the gate electrode 12 is not limited to the polycrystalline silicon layer 1j. For example, molybdenum (Mo), tungsten (W), tantalum (T
a) It may be formed of a high melting point metal layer such as titanium (Ti). Alternatively, it may be formed of a silicide layer of the high melting point metal. Furthermore, the refractory metal layer or silicide layer may be provided on the polycrystalline silicon layer. A conductive layer 8A is provided in the n+ type semiconductor region 10 which becomes a drain region.
An electric potential Vcc, for example, 5 [■] is applied through the gate. The n+ type semiconductor region 10 which becomes the source region has a conductive M
It has the same configuration as type MISFET 4 through 8B. but.

Gate electrode 12 and one n+ type semiconductor region 10 are electrically connected through conductive layer 8C.

That is, they are connected in a diode configuration. the other I
The I+ type semiconductor region 10 is connected to the resistance element 6 and the goo 1-ffi pole 12 of the N-channel MI 5FET 4 by a conductive layer 8D. This is to attenuate the excessive electrical energy flowing in from the pump 7 with the resistive element 6, and then release it into the conductive substrate 1 through surface breakdown between the n+ type semiconductor region 10 and the semiconductor substrate 1. .

Resistance element 6 is made of a polycrystalline silicon layer. This polycrystalline silicon layer is doped with rl type impurities such as phosphorus and arsenic. MISFET4 and MISFET5 for clamp
This is because the gate electrode 12 was formed in the same process. Note that when the gate ffi film 12 of the MISFET 4 and the clamping MISFET 5 is formed of a high melting point metal layer or its silicide layer, the resistance element 6 may be formed in a separate process from the gate electrode 12. However, when the gate electrode 12 is formed by providing a high melting point metal layer or a silicide layer on a polycrystalline silicon layer, it can be formed in the same process as the gate electrode 12.

You can do it like this: First, in the same process as the gate electrode 12, a resistive element 6 consisting of a polycrystalline silicon layer and a high melting point metal layer or silicide layer thereon is formed. Thereafter, the high melting point metal layer or silicide layer on the polycrystalline silicon layer in the resistor element 6 may be etched.

Etching may be performed by forming a resist mask with a pattern that exposes the resistive element 6 over the entire surface of the semiconductor substrate [1].

The resistive element 6 is formed in a straight line, as shown in FIG. Further, a plurality of linear resistive elements 7-6 are connected in series through a conductive layer 8E. Therefore, each resistive element 6 has no curved portion. Also, there are no bent corners. Therefore, the current flows uniformly within the resistance element 6.

That is, no current concentration occurs within the resistance element 6. Therefore, excessive electrical energy flowing from the bonding pad 7 also flows uniformly within the resistive element 6.

Therefore, the resistance element 6 is not destroyed by excessive electrical energy. That is, the reliability of the resistive element 6 is improved.

, Furthermore, MISFET due to excessive electrical energy
In order to prevent destruction of MI 4 or clamp MI 5 FET 5, it is preferable to increase the resistance value of resistor element 6. Furthermore, in order to prevent current concentration, it is preferable to use the linear resistance element 6 as described above.

In order to obtain a large resistance value with one resistance element 6, it is necessary to extend the resistance element 6 for a long time. However, the bonding pad and clamp MISFET5 and M
It is necessary to keep a large distance between the ISFET4 and ISFET4.

Therefore, the degree of integration of the semiconductor integrated circuit device decreases.

However, in this embodiment, as shown in FIG.

A plurality of resistance elements 6 are arranged in parallel, and these resistance teeth 6
are connected in series through a conductive layer 8E. For this reason, the bonding pad 7, the clamping MISFET 5 and the MIS
The distance between the FET 4 and the FET 4 can be reduced. That is, the degree of integration of the semiconductor integrated circuit device can be improved.

Furthermore, by connecting a plurality of resistance elements 6 in series,
The total length of the resistance elements 6 becomes longer. Therefore, the total resistance value increases. Therefore, the attenuation of excessive electrical energy by the resistive element 6 increases. That is, the reliability of the input protection circuit can be improved.

Note that the connecting portion between the resistive element 6 and the bonding pad 7 and the connecting portion between the resistive element 6 and the conductive layer 8E are not destroyed by excessive electrical energy. This is because the adhesion area of the resistive cable 6, the bonding pad 7, and the conductive layer 8E is sufficiently large, so that current concentration that would destroy the resistive element 6 does not occur.

Note that in this embodiment, only four resistance elements 6 are provided. However, it is not limited to this, that is, the resistance element 6
Four or more may be provided and these may be connected in series. Alternatively, it may be three, or even two. That is, the resistance element 6
It is good to have multiple copies.

As shown in FIGS. 2 and 3, an insulating film 13 covers the resistance element 6 and the gate electrode 12. As shown in FIGS. The insulating film 13 is made of, for example, a phosphosilicate glass (PSG) film produced by CVD. An insulating film 14 covers the conductive layer 8. Insulating film 1
4 consists of a PSG film formed by, for example, CVD and a silicon nitride film thereon.

[Example ■] Figure 4 is a plan view of an input protection circuit of a semiconductor integrated circuit device;
5 is a sectional view taken along the line AA in FIG. 4, and FIG. 6 is a sectional view taken along the line BB in FIG. 4. In addition,
In FIG. 4, insulating films other than the field insulating film 2 are not shown in order to make the structure easier to see.

Example (2) is a resistance element 15 consisting of a linear semiconductor region.
A plurality of are provided and these are connected in series through a conductive layer 8E.

The resistance element 15 of this embodiment is made of an n+ type semiconductor region. A plurality of these resistance elements 15 are formed.

The resistive element 15, that is, the semiconductor region is a MISFE.
It is formed in the same process as the n+ type semiconductor region 10 of the T4 and clamp MI 5FET5. Further, a gate insulating film 11 is formed on the surface of the resistive element 15. M.I.
This is because the surface of the resistance element 15 is oxidized when forming the gate insulating film 11 of the S, FET 4 and the clamp MIS FET 5.

As shown in FIG. 4, each resistance element 15 has a straight shape. Therefore, excessive electrical energy flowing from the bonding pad 7 is not concentrated in a part of the resistive element 15. Therefore, there is no generation of abnormal heat due to concentration of electrical energy, and therefore thermal destruction of the resistance element 15 can be prevented. That is, the reliability of the resistance element 15 is improved.

On the other hand, a diode is configured between the resistive element 15 and the semiconductor substrate l. Therefore, a portion of the excessive electrical energy is released from the resistance element 15 into the semiconductor substrate 1.

However, when current concentration occurs, the current is emitted from the concentrated area.

For this reason, the current density during discharge increases and abnormal heat is generated. That is, the resistance element 15 and the semiconductor substrate l
Destroy the bond between which. However, according to this embodiment,
Excessive electrical energy is released from substantially the entire surface of the bonding surface between the resistive element 15 and the semiconductor substrate 1. This is because, as described above, since the current does not concentrate within the resistive element 15, breakdown occurs substantially simultaneously over the entire junction surface between the resistive element 15 and the semiconductor substrate 1. That is, the reliability of the diode composed of the resistive element 15 and the semiconductor substrate 1 is improved.

Note that the resistance element 15 may be formed of a P+ type semiconductor region. The resistance element 15 made of this P+ type semiconductor region is
It may be formed on an n-type semiconductor substrate. Alternatively, an n-type well region may be provided on the surface of the P-type semiconductor substrate 1, and the material may be formed in this well region. In addition, when the resistance element 15 is composed of a P+ type semiconductor region, a P channel type MISFE
It may be formed in the same process as the source and drain of T.

That is, the resistance element 15 is not limited to the conductivity type of the semiconductor region.

On the other hand, in this embodiment, the resistive elements 15 are connected by a conductive layer 18E made of an aluminum layer, but they may be connected by a polycrystalline silicon layer. This polycrystalline silicon layer may be formed in the same process as the gate electrode 12 of the MI S FET. therefore.

Connection may be made using a high melting point metal or a silicide of the high melting point metal, or furthermore, a conductive layer formed by providing a high melting point metal or a silicide thereof on a polycrystalline silicon layer may be used for connection. Gate insulating film 1 at the end of resistance element 15
1 may be selectively removed and opened before forming the gate electrodes 12 of the MISFET 4 and the clamping MISFET 5.

[Effects] According to the new technology disclosed in the present application, the following effects can be obtained.

(1) By connecting multiple linear resistance elements in series with a conductive layer different from that of the resistance elements, current concentration within the resistance elements is eliminated, resulting in damage to the resistance elements due to flux. It is possible to prevent this and improve the reliability of the resistance element.

(2) By using a plurality of linear resistance elements as the resistance elements constituting the input protection circuit, and arranging them in parallel and connecting them in series using a conductive layer different from the resistance elements, the bonding pad and the MISFET for clamping Or, since the distance between the M I S FET that constitutes the buffer circuit etc. is reduced,
The degree of integration of a semiconductor integrated circuit device can be improved.

(3) By connecting a plurality of linear resistive element films in series, the attenuation rate of excess electrical energy by the resistive elements is increased, so that the reliability of the input protection circuit can be improved.

(4) By connecting resistance elements made of linear semiconductor regions in series through a conductive layer, breakdown of the diode made of the semiconductor region and the semiconductor substrate occurs over almost the entire junction surface of the semiconductor regions. Therefore, the reliability of the input protection circuit can be improved by preventing destruction due to breakdown of the diode.

Hereinafter, the present invention has been specifically explained using examples. However, it goes without saying that the present invention is not limited to the above-mentioned examples and can be modified in various ways without departing from the gist thereof. do not have.

For example, in the embodiment described above, the semiconductor element connected to the resistance element is an MI S FET, but the semiconductor element connected to the resistance element may be a bipolar transistor. Furthermore, the conductivity type of the semiconductor substrate is not limited, and the clamping M
An IS FET may also be provided. Also, M for clamp
It goes without saying that other suitable switching elements such as a PN junction diode may be used in place of the I S FET.

[Brief explanation of the drawing]

FIG. 1 is a plan view of the input protection circuit of the semiconductor integrated circuit device of Example I. FIG. 2 is a sectional view taken along the line AA in FIG. 1. FIG. 3 is a sectional view taken along the line BB in FIG. 1. FIG. 4 is a plan view of the input protection circuit of the semiconductor integrated circuit device of Example (2). FIG. 5 is a sectional view taken along the line AA in FIG. 4. FIG. 6 is a sectional view taken along the line B--B in FIG. 4. ■...Semiconductor substrate, 2...°field insulating film, 3
... Channels 1 - collar region, 4... MISFET
, 5... MISFET for clamp, 6.15... Resistance element, 7... Bonding pad, 8... Conductive layer, 9... Connection hole, 10... Semiconductor region, 11.13
．． 14...Insulating film. 12...Gate electrode.

Claims (4)

[Claims] 1. A semiconductor integrated circuit device characterized in that a plurality of linear resistance elements are connected in series through a different conductive layer. 2. 2. The semiconductor integrated circuit device according to claim 1, wherein the resistive element is connected to an external terminal of a chip. 3. 2. The semiconductor integrated circuit device according to claim 1, wherein said resistance element is made of a polycrystalline silicon layer. 4. 2. The semiconductor integrated circuit device according to claim 1, wherein the resistive element comprises a semiconductor region on the surface of a semiconductor substrate.