JP2523678B2 - MOSFET with overcurrent protection function - Google Patents

Description

The present invention relates to a vertical power MOSF having an overcurrent protection function.
Regarding ET.

[Prior art]

As a conventional vertical power MOSFET with an overcurrent protection function, for example, the 1985 IEEE Power Electronics Specialists Confere
nce Record, 1985, pp229).

The above device has a vertical MOS (V
DMOS), which is a so-called power IC in which CMOS and bipolar transistors are integrated. This device is overcurrent,
It has a function to protect the device from abnormalities such as over temperature and over voltage.

Of the above-mentioned devices, the circuit configuration of the overcurrent protection part which is the object of the present invention is as shown in FIG. 8, and its structural cross section is as shown in FIG.

In FIG. 8, the main MOSFET 81 is a single cell MOSFET.
Thousands of the same cells as 82 (3000 in this example) are connected in parallel.

In this example, the single cell MOSFET 82 and the main MOSFET 81
Since the ratio of the number of cells to and is 1: 3000, 3000 times the current that has flowed in the single cell MOSFET 82 will flow to the main MOSFET.

The main current flowing through the load 84 is the same as that of the single cell MOSF described above.
The current is monitored by a current mirror circuit including the ET 82 and the galvanometer 83.

In the above circuit, when the current flowing through the galvanic resistor 83 becomes large and the drop voltage across the galvanic resistor 83 becomes large, an overcurrent detection signal is output from either the upper side comparator 85 or the lower side comparator 86. The subsequent gate drive circuit is stopped to cut off the current. Therefore, it is possible to prevent the power IC from being damaged by an overcurrent flowing through the device when the load is short-circuited.

[Problems to be solved by the invention]

However, such a conventional MO with overcurrent protection function
In SFET, the circuit configuration is complicated, the devices used are diverse such as VDMOS, CMOS, and bipolar transistor, the manufacturing process is complicated, and the chip area is increased.Therefore, there is a problem that the manufacturing cost increases. Also, since the above device has a function of protecting the device from various abnormalities such as overcurrent, overtemperature, and overvoltage, it is not cost-effective in an application field that requires only the overcurrent protection function. However, there is a problem that the industrial application range is limited.

The present invention has been made in order to solve the problems of the conventional techniques as described above, and an object of the present invention is to provide a MOSFET having an overcurrent protection function, which has a simple structure and an easy manufacturing process.

[Means for solving problems]

In order to achieve the above object, in the present invention, a first MOSFET for switching a load, a drain thereof are commonly connected to a drain of the first MOSFET, and a gate thereof is connected to an input terminal. The second MOSFET for the current mirror, which has a smaller number of cells than the MOSFET, and the first MOSFET described above.
Current source connected between the source of the first MOSFET and the source of the second MOSFET, the gate of the first MOSFET, and the second resistor of the second MOSFET.
An input resistance connected between the gate of the MOSFET and a collector is connected to a connection point between the gate of the first MOSFET and the input resistance, and a base of the input resistance and the second MOSF.
It is connected to the connection point with the source of ET, and the emitter is the first
And a bipolar transistor connected to the source of the MOSFET.

That is, in the present invention, the current detection of the current mirror is performed by utilizing the threshold characteristic of the base-emitter voltage of the bipolar transistor, and the MOSFET of the main current circuit is
The gate of the current mirror circuit and the gate of the current mirror circuit are separated, and in the event of an abnormality, only the voltage applied to the gate of the main current circuit is stopped to interrupt the current.

With the above-described configuration, the present invention does not require CMOS logic as in the prior art, so the manufacturing process is simple, and since the number of elements is small, the chip area can be reduced even if integrated on the same chip. The increase will be slight. Further, by separating the gate of the MOSFET of the main current circuit and the gate of the MOSFET of the current mirror circuit, the MOSFET of the main current circuit is completely turned off by the positive feedback action in the event of an abnormality, so that it is caused by the overcurrent conduction. It also has the function of preventing damage due to overtemperature.

Example of Invention

FIG. 1 is a circuit diagram of an embodiment of the device of the present invention,
2 to 4 are structural sectional views of an embodiment of the present invention.

First, in FIG. 1, M ₁ is a main MOSFET, M ₂ is a current mirror MOSFET, and as in the case of FIG.
The current mirror MOSFET is a single cell, and the main MOSFET is the same single cell connected in thousands. Note that the number of cells of the current mirror MOSFET is not limited to one, but is significantly smaller than the number of cells of the main MOSFET. R _S is a galvanic resistance, R _i is an input resistance, T ₁ is a main bipolar MOSFET that limits the gate voltage V _G1 of MOSFET M _1.
A transistor, a part composed of the above,
That is, the portion 100 surrounded by the broken line is the MOSFET with overcurrent protection function of the present invention. D is a drain terminal, S is a source terminal, and G is a gate terminal. Note that R _L is a load and V _B is a power supply voltage.

Next, FIG. 2 is a structural diagram of an embodiment of the main MOSFET M ₁ and the current mirror MOSFET M ₂ described above.
(A) is a sectional view and (B) is a plan view of the poly-Si layer 7.
These MOSFETs are so-called vertical MOSFs in which current flows from the back surface of the semiconductor chip to the front surface (bottom to top of the drawing).
It is ET.

In FIG. 2, reference numeral 1 is an n ⁺ substrate that serves as a drain electrode, 2
Is an n substrate serving as a drain region, 3 is a p body region forming an inversion layer by a gate voltage, 4 is an n ⁺ source region, 5
Is a P ⁺ body region, 6 is an interlayer insulating film, 8 is a metal wiring, and 9 is a gate oxide film. Further, 7 is poly-Si provided on the gate oxide film 9, and a part thereof becomes a gate electrode.

The main MOSFET M ₁ and the current mirror MOSFET M ₂ are
As shown in the figure, the cells are connected in parallel.
The ratio of the number of cells is equal to the shunt ratio of the current between M ₁ and M ₂ , that is, the principle of the current mirror is the same as the conventional one.

Next, FIG. 3 shows the input resistance R _i and the galvanic resistance shown in FIG.
FIG. 3 is a structural cross-sectional view of an example of a poly-Si resistor portion used as R _S.

In FIG. 3, 10 is a field oxide film. Further, poly Si7 the main MOSFET · M ₁ in the second view
And the gate electrode of the current mirror MOSFET M ₂
If the same material as Si is used, the number of steps does not increase. The doping of poly-Si may be performed in common with the step of forming the n ⁺ source region 4, p ⁺ body region 5, p body region 3 and the like of M ₁ and M ₂ .

Next, FIG. 4 is a structural sectional view of an embodiment of the portion of the bipolar transistor T ₁ shown in FIG.

In FIG. 4, reference numeral 20 denotes a first base region commonly formed with the p body region 3 of the main MOSFET M ₁ and the current mirror MOSFET M ₂ . In addition, even higher concentration in this
It has a second base region 21 made in common with the p ⁺ body region 5 of M ₁ and M ₂ and an emitter region 22 made in common with the n ⁺ source region 4.

The second base region 21 and the emitter region 22 are formed by the self-alignment diffusion (Diffusion Self Alignment technique) using the same mask in order to reduce the base width of the bipolar transistor T ₁ formed in the lateral direction of the surface. To do. A part of the first base region 20 of the T ₁ forming portion is cut by forming the collector region 23 after forming the first base region 20, whereby a lateral transistor T _{1 is formed.}
Has a sufficiently small base width and a low base impurity concentration to ensure a high h _FE .

The above circuit configuration and device configuration are similar to those of conventional power ICs.
It is easy to manufacture because it can be configured without the CMOS logic and complex bipolar transistors found in.

In addition, since the number of required elements is small, the chip area is small.

[Action]

 Next, the operation will be described.

First, the operation of the circuit shown in FIG. 1, the main MOSFET · M ₁ and the current mirror MOSFET · to the gate terminal G
When a voltage V _G higher than the threshold voltage V _{th of} M ₂ is applied, M ₁ and M ₂
Both turn on, and a current I _L flows through the load R _L. If the bipolar transistor T ₁ is off at this time, V _G = V _G1 = V _G2
And the current I flowing in M ₁ and the current i flowing in M ₂ are n ₁ : n ₂ = I: i, where n ₁ and n ₂ are the number of cells constituting each.
Is.

Further, since I _L = I + i, the load current I _L is Becomes

Accordingly, the voltage across the galvanometric resistor _{R S V S (V S =} R S ×
The load current I _L can be known by detecting the current i from i).

In normal operation, the above voltage V _S is the threshold value V _BE of the base-emitter voltage of the bipolar transistor T _1.
Since it is set to a value smaller than (0.6V), the bipolar transistor T ₁ is turned off, and V _G = V _G1 = V _G2 , as can be easily seen from FIG.
The aforementioned current mirror operation is guaranteed.

On the other hand, if an accident such as a load short circuit occurs, the load current I _L
T but increases, so increases in proportion thereto also the above currents i, increases the voltage V _S of the galvanometric resistor R _S, when the value exceeds the base-emitter voltage V _BE = 0.6V of T _{1 1,} the gate voltage V _G1 of the main MOSFET M ₁ drops as a result.
That is, V _G = V _G2 > V _G1 .

At this time, assuming that the limit value of the load current I _L is I _lim , the value of R _S is If it is selected, the load current I _L can be limited to the limit value I _lim by turning on the transistor T ₁ at the target current value I _lim .

By the way, when V _G2 > V _G1 as described above, V _G2 ≠ V _G1
Therefore, the principle of the current mirror is no longer valid.

That is, in the main MOSFET M ₁ , the gate voltage
When V _G1 decreases, the on-resistance R _{ON of the} M ₁ increases rapidly.
Even if the current I (I _L ) flowing through the M ₁ decreases, the drain-source voltage V _DS , that is, Will increase.

On the other hand, the current mirror MOSFET M ₂ still has V _G2
Since the voltage = V _G remains applied, the current i increases as V _D increases.

That is, the current I flowing through M ₁ decreases, but the current i flowing through M ₂ increases conversely. Therefore, the voltage V _S = R _S × i across the galvanic resistor R _S becomes larger, and the bipolar transistor T ₁ is turned on more strongly, so that the gate voltage V _G1 of M ₁ is positively fed back. Further down, V _G1 <
It becomes V _th and M ₁ is cut off. Therefore, once the overcurrent exceeds the limit value I _lim , almost no current flows through the main MOSFET M ₁ , so that the element is protected from the overcurrent.

Also, if the current value is limited to the limit value I _lim when an overcurrent state occurs due to a load short circuit, the power MOSFET will
It consumes the power of V _DS × I _lim . And for the current I _lim larger than the design current, the V _DS is usually too large, and the above power consumption shown by the product of the excessive V _DS and the current I _lim larger than the normal operating current is usually The power consumption is much higher than the power consumption at that time, and the junction temperature becomes too high, which may eventually lead to thermal runaway damage. However, in the present embodiment, as described above, once the current exceeds the limit value I _lim , almost no current flows in the main MOSFET M ₁ , so that the element is protected from overcurrent at the same time. Also, it is protected from an overtemperature rise due to the overcurrent energization as described above.

Note that, as shown in FIG. 3, the resistors used in the above examples are all made of poly-Si formed on the insulating film, so that M ₁ ,
The electrical insulation from M ₂ is perfect and it is extremely stable against temperature rise.

Also, a bipolar transistor T ₁ formed in the substrate
DS is a horizontal type, but the base width can be made extremely narrow.
Since it is formed using A (Diffusion Self Aligument) technology, it operates stably as an overcurrent detection comparator.

Next, FIG. 5 is a second embodiment of the present invention and shows a sectional view of a structure in which the bipolar transistor T ₁ and the galvanic resistance R _S in the circuit of FIG. ₁ are integrated.

The difference from FIG. 4 is that the pinch region under the collector region 23
25 is used as the galvanic resistance R _S.

In the structure of this embodiment, the pinch region having a large specific resistance is used, and the region immediately below the collector region is effectively used, so that the chip area can be saved.

 Next, FIG. 6 is a diagram of a third embodiment of the present invention.

This embodiment is an example in which the bipolar transistor T ₁ in FIG. ₁ is composed of three layers of npn poly Si transistors.

Since poly-Si has many traps at grain boundaries, the diffusion length of electrons, which are minority carriers, is typically several thousand Å ~
Although it is 1 μm, if the base width can be set to this level, it can be sufficiently used. Further, even if h _FE <1, it cannot be different if the output impedance of T ₁ is sufficiently lower than the input resistance R _i .

In this embodiment, poly-Si is laminated to form a collector region 31, a base region 32, and an emitter region 33 in order from the bottom. The thickness of each of the above regions is the collector region 31.
1μm, base region 325000Å, emitter region 331μ
m.

In this embodiment, in order to prevent the impurity diffusion between the three layers, it is preferable to deposit the vertical MOSFETs M ₁ and M ₂ shown in FIG. ₂ by LPCVD or the like.

According to this configuration, the number of manufacturing steps is slightly increased, but the parasitic bipolar transistor cannot be used at all, so that the performance is the best.

Next, FIG. 7 is a diagram of a fourth embodiment of the present invention.
(A) is a sectional view and (b) is a plan view.

This is a bipolar transistor T ₁ as in FIG.
A poly-Si bipolar transistor used as is shown, but since the structure can be made of more poly-Si,
The manufacturing process is simpler than that of the illustrated embodiment.

In this embodiment, in order to obtain a short base width,
The base region 35 and the emitter region 34 are sequentially diffused by the same diffusion mask made of thick SiO ₂ or the like, and the base width is controlled to be small by the difference in the diffusion. This technique is known as DSA technology. 38 in FIG. 7 (B) is a DSA mask. Further, 40 is a lead region of the base region 35, on which a base electrode (not shown) is provided.

Since the configuration of this embodiment is a lateral device, the size for obtaining the same drive capacity is larger than that of the embodiment of FIG. 6, but the process is simple and no parasitic bipolar transistor is used. It has an excellent effect that it cannot.

〔The invention's effect〕

As described above, according to the present invention, the current detection of the current mirror is performed by utilizing the threshold characteristic of the base-emitter voltage of the bipolar transistor, and the gate of the MOSFET of the main current circuit and the current mirror circuit MOSF
Since the gate is separated from the ET and the current is cut off by stopping only the voltage applied to the gate of the main current circuit in the event of an abnormality, the manufacturing process is simple and the chip area is small. The effect that it can be provided at low cost is obtained. Also, the MOSF of the main current circuit
By separating the gate of ET and the gate of the MOSFET of the current mirror circuit, the MOSFET of the main current circuit is completely turned off by the positive feedback action in the event of an abnormality, so destruction due to overtemperature caused by the conduction of overcurrent is also prevented. You can do it. Further, in the embodiment shown in FIG. 5, the chip area can be further reduced as compared with the case where the circuit shown in FIG. 1 is realized by the devices shown in FIGS. Further, in the embodiment shown in FIGS. 6 and 7, many excellent effects such as high performance without parasitic effect can be obtained because of the SOI structure.

[Brief description of drawings]

1 is a circuit diagram of an embodiment of the present invention, FIGS. 2 to 4 are structural diagrams of an embodiment of the present invention, FIGS. 5 to 7 are structural diagrams of other embodiments of the present invention, and FIG. FIG. 9 is an example of a conventional device. <Description of symbols> M ₁ …… Main MOSFET M ₂ …… Current mirror MOSFET T ₁ …… Bipolar transistor R _i …… Input resistance R _S …… Current detection resistance R _L …… Load V _B …… Supply voltage 100 ...... MOSFET with overcurrent protection function

Claims (1)

(57) [Claims] 1. A first MOSFET for switching a load,
A second MOSFET for a current mirror, the drain of which is connected in common with the drain of the first MOSFET and the gate of which is connected to an input terminal and which has a smaller number of cells than the first MOSFET;
A galvanic resistor connected between the source of the first MOSFET and the source of the second MOSFET, and an input connected between the gate of the first MOSFET and the gate of the second MOSFET. A resistor and a collector are connected to a connection point between the gate of the first MOSFET and the input resistance, a base is connected to a connection point between the galvanic resistance and the source of the second MOSFET, and an emitter is connected to the first point. 1. A MOSFET having an overcurrent protection function, comprising a bipolar transistor connected to the source of MOSFET 1.