JPS5916413B2 - semiconductor equipment - Google Patents
semiconductor equipmentInfo
- Publication number
- JPS5916413B2 JPS5916413B2 JP11771075A JP11771075A JPS5916413B2 JP S5916413 B2 JPS5916413 B2 JP S5916413B2 JP 11771075 A JP11771075 A JP 11771075A JP 11771075 A JP11771075 A JP 11771075A JP S5916413 B2 JPS5916413 B2 JP S5916413B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- type
- semiconductor region
- semiconductor
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 title claims description 58
- 239000002184 metal Substances 0.000 claims description 13
- 230000005684 electric field Effects 0.000 description 9
- 239000000758 substrate Substances 0.000 description 8
- 238000009792 diffusion process Methods 0.000 description 7
- 230000015556 catabolic process Effects 0.000 description 6
- 239000012535 impurity Substances 0.000 description 6
- 238000000034 method Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000002441 reversible effect Effects 0.000 description 4
- 239000004020 conductor Substances 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 230000006378 damage Effects 0.000 description 2
- 230000006698 induction Effects 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/732—Vertical transistors
- H01L29/7322—Vertical transistors having emitter-base and base-collector junctions leaving at the same surface of the body, e.g. planar transistor
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Integrated Circuits (AREA)
- Bipolar Transistors (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】
本発明は、サージ電圧に強いＰＮ接合を有する半導体装
置に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device having a PN junction that is resistant to surge voltages.
従来のトランジスタ、或いはトランジスタおよび抵抗素
子などの複数の回路素子を集積化した半’ｏ 導体集積
回路などのＰＮ接合を有する半導体装置は、これに印加
される予期せぬサージ電圧によつてしばしぱ破壊される
場合がある。Semiconductor devices with PN junctions, such as conventional transistors or semi-conductor integrated circuits that integrate multiple circuit elements such as transistors and resistive elements, often fail due to unexpected surge voltages applied to them. It may be destroyed.
この予期せぬサージ電圧は例えば半導体装置の運搬時の
人体からの静電気の誘導、或いはそれらの半導体装置を
ｊ５テレビセットなどの電子機器に応用した場合にその
応用回路機器の周辺回路からの好ましくないサージ電圧
の誘導に起因し、好ましくないこのサージ電圧は、半導
体装置に設けられた信号の入出力端子、或いは接地端子
などの外部接続用端子から、ｊ０半導体装置のＰＮ接合
部に印加され、該ＰＮ接合を破壊するのである。従つて
、本発明の主たる目的は、サージ電圧によりＰＮ接合が
破壊されるのを防止することにある。This unexpected surge voltage may be caused, for example, by the induction of static electricity from the human body during the transportation of semiconductor devices, or if these semiconductor devices are applied to electronic equipment such as a J5 television set, undesirable surge voltage may be generated from the peripheral circuits of the applied circuit equipment. This undesirable surge voltage, which is caused by the induction of surge voltage, is applied to the PN junction of the j0 semiconductor device from a signal input/output terminal provided on the semiconductor device or an external connection terminal such as a ground terminal. This destroys the PN junction. Therefore, the main object of the present invention is to prevent the PN junction from being destroyed by surge voltage.
■５ 本発明の他の目的は、半導体装置本来の特性を損
傷することなく、サージ電圧に対し破壊強度の強い半導
体装置を提供することにある。(5) Another object of the present invention is to provide a semiconductor device that has strong breakdown strength against surge voltage without damaging the original characteristics of the semiconductor device.
：Ｐ！−
本発明のさらに他の目的は、半導体素子を形成するため
の半導体チツプ内の占有面積を極力小さくせしめたサー
ジ電圧に対する破壊強度の強い半導体装置を提供するこ
とにある。:P! - Still another object of the present invention is to provide a semiconductor device which has a strong breakdown strength against surge voltage and which minimizes the area occupied within a semiconductor chip for forming a semiconductor element.
本発明の要旨は、少なくとも、第１導電型の第１領域中
に、第２導電型の第２領域が存在し、該第１領域と第２
領域との間にＰＮ接合を有する半導体装置において、該
第２導電型の第２須域に、金属層によるコンタクト部を
形成し、該コンタクト部直下に、前記第２領域を囲むよ
うに、第３領域を形成し、該第３頭域は、前記第２須域
よりも濃度が低い第２導電型の領域若しくは前記第１領
域よりも濃度が低い第１導電型の須域又は、真性半導体
の碩域のいずれかよりなることを特徴とする半導体装置
にある。The gist of the present invention is that at least a second region of the second conductivity type exists in the first region of the first conductivity type, and the first region and the second region
In a semiconductor device having a PN junction between the second region and the second region, a contact portion made of a metal layer is formed in the second region of the second conductivity type, and a contact portion is formed immediately below the contact portion so as to surround the second region. The third region is a region of a second conductivity type that has a lower concentration than the second region, a region of a first conductivity type that has a lower concentration than the first region, or an intrinsic semiconductor. A semiconductor device comprising any one of the following sub-regions.
以下、本発明を図面を参照にして説明する。Hereinafter, the present invention will be explained with reference to the drawings.
第１図ｂは本発明の一実施例に係る半導体装置（集積回
路）の断面図を示し、第１図ｄはその平面図を示す。第
１図ａはその等価回路図を示し、第１図ｃはその半導体
装置に印加される電界強度を示す。第１図ｂにて、１は
Ｐ型の半導体基板、２は、Ｎ型島領域で、この島領域は
ｐ＋型のアイソレーシヨン須域５にて他のＮ型島領域（
図示せず）から電気的絶縁されている。３は、Ｎ型島領
域の中に形成されたＰ型のベース領域、４はＰ型ベース
領域中に形成されたＮ型のエミツタ領域、１０１は、コ
ンタクト部８によつてベース領域３にオーミツク接続さ
れている金属配線層で、これは入力端子７に接続される
。FIG. 1b shows a sectional view of a semiconductor device (integrated circuit) according to an embodiment of the present invention, and FIG. 1d shows a plan view thereof. FIG. 1a shows its equivalent circuit diagram, and FIG. 1c shows the electric field strength applied to the semiconductor device. In FIG. 1b, 1 is a P-type semiconductor substrate, 2 is an N-type island region, and this island region is connected to another N-type island region (
(not shown). 3 is a P-type base region formed in the N-type island region, 4 is an N-type emitter region formed in the P-type base region, and 101 is an ohmic contact to the base region 3 through the contact portion 8. A connected metal wiring layer is connected to the input terminal 7.
１０２はエミツタ領域４にオーミツク接続された金属配
線層で、この金属配線層は導線１４によつて接地される
。Reference numeral 102 denotes a metal wiring layer ohmicly connected to the emitter region 4, and this metal wiring layer is grounded by a conductive wire 14.
１０３は、コレクタ領域として作用するＮ型島領域２に
オーミツク接続された金属配線層で、この配線層はさら
に、出力導体１１および負荷抵抗１３を通して電源Ｖｃ
ｃに接続される。Reference numeral 103 denotes a metal wiring layer that is ohmicly connected to the N-type island region 2 that acts as a collector region, and this wiring layer is further connected to the power supply Vc through the output conductor 11 and the load resistor 13.
connected to c.
１０は、低濃度なＰ一型碩域で、その不純物濃度は約１
０１５〜１６ａｔ０ｍｓ／Ｃｄである。10 is a low-concentration P-type region, and its impurity concentration is approximately 1
015-16at0ms/Cd.
この不純物濃度は、Ｐ型ベース碩域３の不純物濃度（例
えば１０１８ａｔ０ｍｓ′）より低い濃度に規定される
。このＰ一型領域１０は第１図ｄの平面図からも明らか
なように、入力信号の供給用の金属配線層１０１がベー
ス領域３にオーミツクコンタクトするコンタクト部８の
直下のＰ型ベース領域３の周囲を包囲するように配設さ
れている。このＰ一領域１０は、エミツタ領域４の直下
部には存在しないので、トランジスタのベース幅を変え
ることはなく、従つて、トランジスタ素子が本来持つ電
流増幅率などの電気的特性を損傷することはない。しか
も、Ｐ一領域はベース領域に局部的に形成されるために
、従来の半導体装置とほぼ同様な占有面積を有する。次
に、かかる本発明の半導体装置の製造方法を述べる。This impurity concentration is defined to be lower than the impurity concentration of the P-type base region 3 (for example, 1018 at0 ms'). As is clear from the plan view of FIG. 1d, this P-type region 10 is a P-type base region immediately below the contact portion 8 where the metal wiring layer 101 for supplying input signals is in ohmic contact with the base region 3. It is arranged so as to surround 3. Since this P-region 10 does not exist directly below the emitter region 4, it does not change the base width of the transistor, and therefore does not damage the electrical characteristics such as the current amplification factor that the transistor element originally has. do not have. Moreover, since the P1 region is formed locally in the base region, it has an occupied area almost the same as that of a conventional semiconductor device. Next, a method for manufacturing the semiconductor device of the present invention will be described.
第１図ｂにおいて、Ｐ型基板１を用意し、この上に周知
のエピタキシヤル成長技術によつてＮ型ＥＰ層を形１成
し、このＥＰ層中にｐ＋アイソレーシヨン領域５を周知
の拡散技術により形成する。その結果できたＮ型島領域
２中に、外部入力端子７に接続される金属層１０１とコ
ンタクト８を形成すべき部分の直下にＰ一型の領域１０
を拡散技術により形成する。そして、このＰ一型領域１
０よりも浅いＰ型ベース領域３を、Ｎ型島領域２中に拡
散により形成する。その時、第１図ｄに示すように金属
層１０１のコンタクト部８直下に、形成されたＰ一型領
域１０にその一部が、包囲されるように、Ｐ型ベース碩
域３が形成される。そのあと、Ｎ＋型エミツタ領域４を
拡散技術によつて形成し、このＮ＋型エミツタ領域４及
びＰ型ベース領域３、さらにＮ型島領域２に接続される
金属層１０１，１０２および１０３を蒸着等の手段によ
り形成する。なお、上記Ｐ一型領域は拡散技術によつて
形成する他に、イオン打込み技術によつても形成するこ
とができる。すなわち、Ｐ型基板１中に、ｐ＋アイソレ
ーシヨン須域５を拡散技術によつて形成したのち、Ｎ型
島領域２中に、ボロンなどのＰ型不純物をイオン打込み
することによりＰ一型領域１０を形成する。そのあと、
第１図Ｂ，ｄに示すように少くなくともこのＰ一型領域
１０にその一部が含まれるように、Ｐ一型領域１０より
高濃度なＰ型のベース領域を拡散技術によつて形成する
。本発明のかかる半導体装置によれば、予期せぬ過渡状
態においてサージ電圧が印加されても、その半導体装置
のコレクタ、ベース間のＰＮ接合は破壊から防止される
。In FIG. 1b, a P-type substrate 1 is prepared, an N-type EP layer 1 is formed thereon by a well-known epitaxial growth technique, and a p+ isolation region 5 is formed in this EP layer by a well-known epitaxial growth technique. Formed by diffusion technology. In the resulting N-type island region 2, there is a P-type region 10 immediately below the part where the contact 8 is to be formed with the metal layer 101 connected to the external input terminal 7.
is formed using diffusion technology. And this P type region 1
A P type base region 3 shallower than 0 is formed in the N type island region 2 by diffusion. At this time, as shown in FIG. 1d, a P-type base subregion 3 is formed directly below the contact portion 8 of the metal layer 101 so as to be partially surrounded by the formed P-type region 10. . After that, an N+ type emitter region 4 is formed by diffusion technology, and metal layers 101, 102, and 103 connected to this N+ type emitter region 4, P type base region 3, and N type island region 2 are formed by vapor deposition, etc. Formed by means of. Note that the P-type region described above can be formed not only by the diffusion technique but also by the ion implantation technique. That is, after forming a p+ isolation region 5 in a P-type substrate 1 by diffusion technology, a P-type region 5 is formed by ion-implanting P-type impurities such as boron into the N-type island region 2. form 10. after that,
As shown in FIGS. 1B and d, a P-type base region having a higher concentration than the P-type region 10 is formed by diffusion technology so that at least a part of the P-type base region is included in the P-type region 10. do. According to the semiconductor device of the present invention, even if a surge voltage is applied in an unexpected transient state, the PN junction between the collector and base of the semiconductor device is prevented from being destroyed.
いま、第１図ｂに示す半導体装置の入力端子７に数百ボ
ルトの波高値を持つ負のサージ電圧Ｅｉが印加された場
合を考えてみるに、サージ電流は金属層１０１のオーミ
ツクコンタクト部８からＰ型ベース領域３を通し、さら
にエミツタ・ベース間のＰＮ接合を横切つてエミツタ金
属層１０２および導体１４を通してアースに流れようと
する。一方、このサージ電圧は、電源Ｖｃｃおよび抵抗
１３を通して、Ｎ型コレクタ領域（島領域）２とＰ型ベ
ース領域３との間のコレクタ、ベースＰＮ接合９に、該
ＰＮ接合９を逆バイアスする方向に印加される。このサ
ージ電圧は、ベース領域３に存在する分布抵抗１０４に
サージ電流が流れるがために、ベースコンタクト部８の
直下のコレクタ、ベースＰＮ接合部に一番大きな逆バイ
アス電圧を供給し、このコンタクト部８直下の接合部か
ら離間された、エミツタ領域４の直下のコレクタ、ベー
スＰＮ接合部に比較的小さな逆バイアス電圧が印加され
ることになる。すなわち、第１図ｃに示すように、ベー
スコンタクト部８の直下のＰＮ接合部に印加される電界
はＥ５となり一番強く、エミツタ領域４の直下のＰＮ接
合部の電界はＥ１であり一番弱くなる。しかるに、本発
明によれば、電界強度の一番強いベースコンタクト部８
直丁のＰＮ接合部には特に低濃度なＰ一型の半導体領域
１０が配設されているために、ＰＮ接合部のブレークダ
ウン電圧は補強されており、従つて、たとえ、電界強度
の強い逆バイアス電圧がＰＮ接合に印加されても、その
ＰＮ接合は破壊から防止される。一般にＰＮ接合部を形
成する隣接するＰ又はＮ型の半導体領域の不純物濃度が
より低濃度になるに従つて、Ｐ又はＮ型の半導体領域に
おける、ＰＮ接合のブレークダウンし始めるときの電界
（以下、臨界電界と言う）は、より低くなることが知ら
れている。これは例えばＸＰｈｙｓｉｃｓａｎｄＴｅｃ
ｈｎＯｌＯｇｙＯｆＳｍｉ一ＣＯｎｄｕｃｔＯｒＤｅｖ
ｉｃｅｓＩＡ．Ｓ．ＧＲＯＶＥの１９３頁，Ｆｉｇ．６
，２７に記載されている。従つて、本発明においてＰ一
型低濃度領域とＮ型領域とのＰ−Ｎ接合の臨界電界が従
来の場合よりも、低いためにｐ−Ｎ接合で消費されるエ
ネルギーが少くなり発生する熱も従来より低くなる。つ
まり、この接合での発熱による温度がＳｉの溶解温度に
まで達つしにくくなるのである。従つて外部端子に予期
せぬサージ電圧が印加されてもつこの端子が接続されて
いる直下のｐ−Ｎ接合の破壊強度が向上されるのである
。さらに、Ｐ一型の半導体碩域１０は、ベースコンタク
ト部直下のみに形成されているため、Ｐ一領域１０によ
つてベース幅を大きくすることはなノブ
く、本来のトランジスタの特性を、そこなうことはない
。Now, consider the case where a negative surge voltage Ei having a peak value of several hundred volts is applied to the input terminal 7 of the semiconductor device shown in FIG. 8 through the P-type base region 3, further across the PN junction between the emitter and base, through the emitter metal layer 102 and the conductor 14 to ground. On the other hand, this surge voltage is applied to the collector-base PN junction 9 between the N-type collector region (island region) 2 and the P-type base region 3 through the power supply Vcc and the resistor 13 in a direction that reverse biases the PN junction 9. is applied to Since this surge voltage causes a surge current to flow through the distributed resistance 104 existing in the base region 3, the highest reverse bias voltage is supplied to the collector and base PN junction immediately below the base contact portion 8, and this contact portion A relatively small reverse bias voltage is applied to the collector-base PN junction directly below the emitter region 4, which is spaced apart from the junction directly below the emitter region 8. That is, as shown in FIG. 1c, the electric field applied to the PN junction directly under the base contact portion 8 is E5, which is the strongest, and the electric field applied to the PN junction directly under the emitter region 4 is E1, which is the strongest. become weak. However, according to the present invention, the base contact portion 8 with the strongest electric field strength
Since a particularly low concentration P-type semiconductor region 10 is arranged in the direct PN junction, the breakdown voltage of the PN junction is reinforced, and therefore even if the electric field strength is strong, Even if a reverse bias voltage is applied to the PN junction, the PN junction is prevented from being destroyed. In general, as the impurity concentration of the adjacent P or N type semiconductor region forming the PN junction becomes lower, the electric field (hereinafter referred to as , the critical electric field) is known to be lower. This is for example XPhysicsandTec
hnOlOgyOfSmi-CONductOrDev
icesIA. S. GROVE page 193, Fig. 6
, 27. Therefore, in the present invention, the critical electric field of the P-N junction between the P-type low concentration region and the N-type region is lower than in the conventional case, so that less energy is consumed in the p-N junction and the heat generated is reduced. is also lower than before. In other words, it becomes difficult for the temperature generated by the heat generated in this bonding to reach the melting temperature of Si. Therefore, even if an unexpected surge voltage is applied to an external terminal, the breaking strength of the p-N junction directly below the external terminal connected to this terminal is improved. Furthermore, since the P-type semiconductor region 10 is formed only directly under the base contact portion, the base width is not increased by the P-type region 10, and the original characteristics of the transistor are impaired. Never.
また、Ｐ一領域１０はベース領域に局部的に存在するの
で、半導体装置の集積度を減少させるという心配もない
。第２図Ａ，ｂは、本発明をＭＯＳ型集積回路装置のゲ
ート保護用抵抗領域に応用した他の実施例を示す。Further, since the P-region 10 exists locally in the base region, there is no fear that the degree of integration of the semiconductor device will be reduced. FIGS. 2A and 2B show another embodiment in which the present invention is applied to a gate protection resistor region of a MOS type integrated circuit device.
同図ｂは、ＭＯＳ型集積回路装置の断面図を示し、同図
ａは、ＭＯＳ型集積回路装置の等価回路図を示す。第１
図ｂ中、３１は、Ｎ型半導体基板である。３７は、Ｐ型
ソース須域で導体２０１を通して接地される。Figure b shows a sectional view of a MOS integrated circuit device, and figure a shows an equivalent circuit diagram of the MOS integrated circuit device. 1st
In FIG. b, 31 is an N-type semiconductor substrate. 37 is a P-type source region and is grounded through conductor 201.
３８はＰ型ドレイン領域でＤＤに接続される。38 is a P-type drain region connected to DD.
３４は、外部入力端子３２と、ゲート２０２間に接続さ
れるＰ型のゲート保護用抵抗領域である。34 is a P-type gate protection resistance region connected between the external input terminal 32 and the gate 202.
３３は、Ｐ一型の低濃度領域で、外部入力端子３２のコ
ンタクト部３５直下に形成されている。Reference numeral 33 denotes a P-type low concentration region, which is formed directly below the contact portion 35 of the external input terminal 32.
この構造にすれば外部入力端子３２に予期せぬサージ電
圧が印加されても、ゲート保護用抵抗領域３４には、低
濃度のＰ一型須域３３があるため、この抵抗領域３４と
Ｎ型半導体基板３１との間のＰＮ接合で消費されるエネ
ルギーが減少されるため、このゲート保護用抵抗領戚３
４の破壊強度は向上する。さらに、コンタクト部３５直
下のみに、Ｐ一型領域があるために、Ｐ一型領域によつ
て包囲された以外のゲート保護用抵抗領域３４が基板３
１に対し形成するＰＮ接合は絶縁ゲート２０３の破壊電
圧より低い所望のツエナ一電圧に設定できるので、ゲー
ト２０２に印加されるサージ電圧をツエナ一電圧に制限
する。すなわち、ゲート保護用抵抗碩域３４のサージ電
圧をクランプするという本来の特性を損うことなく、抵
抗碩域３４自体のサージ電圧に対する破壊強度を改善す
ることができる。しかも、Ｐ一領域３３は局部的に設け
られるので、集積度を著しく悪化させることはない。さ
らに第３図Ａ，ｂは、本発明を、バイポーラ型集積回路
装置に適用した他の実施例を示す。With this structure, even if an unexpected surge voltage is applied to the external input terminal 32, since the gate protection resistor region 34 has a low concentration P-type subregion 33, this resistor region 34 and the N-type Since the energy consumed in the PN junction with the semiconductor substrate 31 is reduced, this gate protection resistive region 3
The fracture strength of No. 4 is improved. Furthermore, since there is a P-type region only directly below the contact portion 35, the gate protection resistor region 34 other than that surrounded by the P-type region is exposed to the substrate 3.
1 can be set to a desired Zener voltage lower than the breakdown voltage of the insulated gate 203, thereby limiting the surge voltage applied to the gate 202 to the Zener voltage. In other words, the breakdown strength of the resistor region 34 itself against surge voltage can be improved without impairing the original characteristic of the gate protection resistor region 34 to clamp surge voltage. Furthermore, since the P-region 33 is provided locally, the degree of integration does not deteriorate significantly. Furthermore, FIGS. 3A and 3B show another embodiment in which the present invention is applied to a bipolar integrated circuit device.
同図ｂは、バイポーラ型集積回路装置の断面図を示し、
同図ａはその等価回路図を示す。第３図ｂ中、４１は半
導体基板を示す。４２は、Ｎ型島碩域で、ｐ＋型アイソ
レーシヨン領域５１によつて、分離されている。Figure b shows a cross-sectional view of a bipolar integrated circuit device,
Figure a shows its equivalent circuit diagram. In FIG. 3b, 41 indicates a semiconductor substrate. 42 is an N-type island region separated by a p + type isolation region 51 .
４３は、Ｎ型島碩域４２中に形成されたＰ型ベース碩域
である。43 is a P-type base area formed in the N-type island area 42.
４４は、Ｐ型ベース領域４３中に形成されたＮ＋型エミ
ツタ領域である。44 is an N+ type emitter region formed in the P type base region 43.
４８は、Ｎ型島領域４２中に形成された、Ｐ型抵抗領域
である。48 is a P-type resistance region formed in the N-type island region 42.
このＰ型抵抗須域は、外部入力端子５０とＰ型ベース須
域４３間に接続される。Ｐ一型領域４７は、外部入力端
子５０のコンタクト部４５の直下に形成されている。こ
の構造も、外部入力端子５０に予期せぬサージ電圧が印
加されても抵抗領域４８は、Ｐ一型領域４７により、破
壊強度は向上する。この場合も、コンタクト部４５直下
のみに、Ｐ一型須域４７があるため、Ｐ型抵抗碩域４８
の面積はさほど大きくならず、集積回路装置全体の集積
度は減少しない。以上述べた第１図、第２図、および第
３図に示した実施例においてはいずれも外部接続端子と
なる金属層のコンタクト部直下にＰ一型領域を形成して
いるがこのＰ一型碩域のかわりに第４図に示すように、
Ｎ型基板６１より不純物濃度の低いＮ一型領域６３を形
成しても良い。This P-type resistor area is connected between the external input terminal 50 and the P-type base area 43. The P-type region 47 is formed directly below the contact portion 45 of the external input terminal 50. In this structure, even if an unexpected surge voltage is applied to the external input terminal 50, the resistance region 48 has improved breakdown strength due to the P-type region 47. In this case as well, since the P-type resistance region 47 exists only directly below the contact portion 45, the P-type resistance region 48
The area of the integrated circuit device does not increase significantly, and the degree of integration of the entire integrated circuit device does not decrease. In the embodiments shown in FIGS. 1, 2, and 3 described above, a P-type region is formed directly under the contact portion of the metal layer that serves as an external connection terminal. As shown in Figure 4, instead of a sub-region,
An N1 type region 63 having a lower impurity concentration than the N type substrate 61 may be formed.
さらに上記したＰ一型領域又はＮ一型領域のかわりに第
５図に示すように真性半導体領域７１としても良い。本
発明は、第１図、第２図、第３図に示すように、バイポ
ーラ型集積回路およびＭＯＳ型東積回 シ路への適用は
もちろんのこと、一般に、半導体装置において、接地用
端子、電源接続用端子、信号入力端子等の外部接続用端
子が直接接続されるＰＮ接合を有する半導体素子に対す
る破壊防止として広く適用されるものである。Further, instead of the above-mentioned P type region or N type region, an intrinsic semiconductor region 71 may be used as shown in FIG. As shown in FIGS. 1, 2, and 3, the present invention is applicable not only to bipolar integrated circuits and MOS integrated circuits, but also generally to ground terminals, It is widely applied to prevent destruction of semiconductor elements having PN junctions to which external connection terminals such as power supply connection terminals and signal input terminals are directly connected.
第１図ａは、本発明を適用したバイポーラ型集積回路装
置の回路図を示す。
第１図ｂは、同図ａに示したバイポーラ型集積回路装置
のトランジスタＱ１の断面図を示す。第１図ｃは、同図
ｂに示したバイポーラトランジスタＱ１にサージ電圧が
印加された時のＰ型ベース領域とＮ型領域とに加わる電
界の分布を示す。第１図ｄは、同図ｂに示したトランジ
スタＱ１の外部入力端子７と、Ｐ−型須域１０、Ｐ型領
域３との関係を示す平面図である。第２図Ａ，ｂは、本
発明を、ＭＯＳ型集積回路のゲート保護用抵抗領域に応
用した場合を示す。第３図Ａ，ｂは、本発明をバイポー
ラ型集積回路の入力抵抗部分に応用した場合を示す。第
４図、第５図は本発明の他の実施例を示す。１，４１・
・・・・・Ｐ型領域、２，４２・・・・・・Ｎ型島領域
、３，４３・・・・・・Ｐ型ベース領域、４，４４・・
・・・・Ｎ＋型エミツタ領域、７，３２，５０・・・・
・・外部入力端子、９，３９，４９・・・・・・ＰＮ接
合、８，３５，４５・・・・・・外部入力端子とＰ型領
域とのコンタクト部、１０，３３，４７・・・・・・Ｐ
一型領域、３７・・・・・・ソース領域、３８・・・・
・・ドレイン領域、３４・・・・・・ゲート保護用抵抗
領域、４８・・・・・・抵抗領域、６１，７１・・・・
・・Ｎ型領域、６２，７２・・・・・・Ｐ型領域、６３
・・・・・・Ｎ一型領域、７３・・・・・・真性半導体
領域、１０５，５２・・・・・・コレクタ電極取出し層
。FIG. 1a shows a circuit diagram of a bipolar integrated circuit device to which the present invention is applied. FIG. 1b shows a sectional view of the transistor Q1 of the bipolar integrated circuit device shown in FIG. 1a. FIG. 1c shows the distribution of the electric field applied to the P-type base region and the N-type region when a surge voltage is applied to the bipolar transistor Q1 shown in FIG. 1B. FIG. 1d is a plan view showing the relationship between the external input terminal 7 of the transistor Q1 shown in FIG. 1b, the P-type region 10, and the P-type region 3. FIGS. 2A and 2B show a case where the present invention is applied to a gate protection resistor region of a MOS type integrated circuit. FIGS. 3A and 3B show a case where the present invention is applied to an input resistance portion of a bipolar integrated circuit. FIGS. 4 and 5 show other embodiments of the present invention. 1,41・
...P type region, 2,42...N type island region, 3,43...P type base region, 4,44...
...N+ type emitter region, 7, 32, 50...
...External input terminal, 9,39,49...PN junction, 8,35,45...Contact part between external input terminal and P-type region, 10,33,47... ...P
Type 1 region, 37... Source region, 38...
...Drain region, 34...Resistance region for gate protection, 48...Resistance region, 61, 71...
...N-type region, 62,72...P-type region, 63
. . . N-type region, 73 . . . Intrinsic semiconductor region, 105, 52 . . . Collector electrode extraction layer.
Claims (1)
領域中に形成され、該第１の半導体領域とＰＮ接合を形
成して１つの終端部から他の終端部に延長する第２導電
型の第２の半導体領域と、前記第２の半導体領域の両終
端部に対応してそれぞれ接続された２つの外部接続手段
と、前記外部接続手段が設けられた前記第２の半導体領
域の少なくとも一つの終端部において形成され、該終端
部に存在する前記ＰＮ接合を包囲する第３の半導体領域
とから成り、前記第３の半導体領域は、前記第２の半導
体領域よりも濃度が低い第２導電型の領域もしくは前記
第１の半導体領域よりも濃度が低い第１導電型の領域、
または真性半導体領域のいずれか一つの領域より成るこ
とを特徴とする半導体装置。 ２ 前記２つの外部接続手段は、前記第２の半導体領域
の両終端部にそれぞれ直接的にオーミック接続された金
属層より成る特許請求の範囲第１項記載の半導体装置。 ３ 前記２つの外部接続手段の１つは、前記第２の半導
体領域の一つの終端部に直接的にオーミック接続された
金属層より成り、また、前記外部接続手段の他は、前記
第２の半導体領域の他の終端部の前記第２の半導体領域
中に形成された第１導電型の第４の半導体領域を具備し
て成り、さらに、前記第３の半導体領域は前記一つの終
端部を包囲するように形成されて成ることを特徴とする
特許請求の範囲第１項記載の半導体装置。 ４ 第３項記載の半導体装置であつて、第１の半導体領
域はコレクタ、第２の半導体領域はベース、第４の半導
体領域はエミッタとしてそれぞれ作用するバイポーラト
ランジスタであることを特徴とする半導体装置。[Claims] 1. A first semiconductor region of a first conductivity type; A second semiconductor region of a second conductivity type extending to a termination portion, two external connection means respectively connected to both termination portions of the second semiconductor region, and the external connection means are provided. a third semiconductor region formed at at least one terminal end of the second semiconductor region and surrounding the PN junction present at the terminal end, the third semiconductor region a second conductivity type region having a lower concentration than the first conductivity type region or a first conductivity type region having a lower concentration than the first semiconductor region;
or a semiconductor device comprising any one of an intrinsic semiconductor region. 2. The semiconductor device according to claim 1, wherein the two external connection means each comprise a metal layer that is directly ohmically connected to both end portions of the second semiconductor region. 3. One of the two external connection means is made of a metal layer that is directly ohmically connected to one end of the second semiconductor region, and the other external connection means are connected to the second semiconductor region. a fourth semiconductor region of the first conductivity type formed in the second semiconductor region at the other end of the semiconductor region; 2. The semiconductor device according to claim 1, wherein the semiconductor device is formed so as to surround the semiconductor device. 4. The semiconductor device according to item 3, wherein the semiconductor device is a bipolar transistor in which the first semiconductor region acts as a collector, the second semiconductor region acts as a base, and the fourth semiconductor region acts as an emitter. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11771075A JPS5916413B2 (en) | 1975-10-01 | 1975-10-01 | semiconductor equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11771075A JPS5916413B2 (en) | 1975-10-01 | 1975-10-01 | semiconductor equipment |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59278879A Division JPS60246662A (en) | 1984-12-28 | 1984-12-28 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5243374A JPS5243374A (en) | 1977-04-05 |
| JPS5916413B2 true JPS5916413B2 (en) | 1984-04-16 |
Family
ID=14718378
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11771075A Expired JPS5916413B2 (en) | 1975-10-01 | 1975-10-01 | semiconductor equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5916413B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6314646Y2 (en) * | 1983-01-20 | 1988-04-25 |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55115162A (en) * | 1979-02-26 | 1980-09-04 | Toshiba Corp | Skew check unit |
| JPS55128858A (en) * | 1979-03-28 | 1980-10-06 | Mitsubishi Electric Corp | Surge preventive circuit for bipolar integrated circuit |
| DE3035462A1 (en) * | 1980-09-19 | 1982-05-13 | Siemens AG, 1000 Berlin und 8000 München | SEMICONDUCTOR ELEMENT |
| JPS61263285A (en) * | 1985-05-17 | 1986-11-21 | Matsushita Electronics Corp | Semiconductor device |
| JPH0682788B2 (en) * | 1989-11-02 | 1994-10-19 | ローム株式会社 | Semiconductor device with built-in resistor |
-
1975
- 1975-10-01 JP JP11771075A patent/JPS5916413B2/en not_active Expired
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6314646Y2 (en) * | 1983-01-20 | 1988-04-25 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5243374A (en) | 1977-04-05 |
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