JPH0462838A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH0462838A
JPH0462838A JP16714390A JP16714390A JPH0462838A JP H0462838 A JPH0462838 A JP H0462838A JP 16714390 A JP16714390 A JP 16714390A JP 16714390 A JP16714390 A JP 16714390A JP H0462838 A JPH0462838 A JP H0462838A
Authority
JP
Japan
Prior art keywords
interconnection
layer
diffusion layer
type diffusion
aluminum
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16714390A
Other languages
Japanese (ja)
Inventor
Joji Nakane
譲治 中根
Tatsumi Sumi
辰己 角
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP16714390A priority Critical patent/JPH0462838A/en
Publication of JPH0462838A publication Critical patent/JPH0462838A/en
Pending legal-status Critical Current

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  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To prevent an aluminum interconnection from being brought into contact with an N-type diffusion layer for increasing a surge resistance by installing a polycide interconnection and a contact window between the aluminum interconnection and the N-type diffusion layer in an input protection network, one of semiconductor devices. CONSTITUTION:This semiconductor device is constituted of a p-type semiconductor substrate 1, an N-type diffusion layer 2, an insulating layer 3, contact windows 4 and an aluminum interconnection 5. The structure is the same as conventional semiconductor devices. The difference of this semiconductor device from the conventional ones is a polycide interconnection (a two-layer-structured interconnection with polysilicon in the lower layer and high-melting point metal such as tungsten silicide WSix in the upper layer) 6. The polycide interconnection 6 is connected to the N-type diffusion layer through the lower contact windows 4 while it is connected to the aluminum interconnection 5 through the upper contact windows 4. The polycide interconnection 6 and the lower contact windows 4 can be made only by modifying a part of a layout pattern of a multilayer interconnection used in a densely integrated semiconductor device.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、入力保護回路のサージ耐圧向上させることか
可能な半導体装置に関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor device capable of improving the surge withstand voltage of an input protection circuit.

従来の技術 従来より、半導体装置は、人体や機械などの外部から入
ってくる過大な静電気(以下、サージと称す)より、内
部回路を保護するために入力保護回路を用いてサージに
対する耐圧を向上させている。
Conventional technology Traditionally, semiconductor devices have improved their voltage resistance against surges by using input protection circuits to protect internal circuits from excessive static electricity (hereinafter referred to as surges) that enters from external sources such as the human body or machinery. I'm letting you do it.

以下、従来の半導体装置の入力保護回路について説明す
る。第2図は従来の半導体装置の入力保護回路の要所断
面図である。P型半導体基板1の上部にN型拡散層2を
、イオン注入により(深さ約0.2ミクロン)形成する
。P型半導体基板1の電位は0ホルトかそれ以下の電位
が与えられている。N型拡散層2の上部には、化学的気
相成長法により、酸化シリコンを主成分にする層間絶縁
膜3を形成する。コンタクト窓4は層間絶縁膜3にエツ
チングにより形成し、アルミニウム配線5をN型拡散層
3と接続する。
A conventional input protection circuit for a semiconductor device will be described below. FIG. 2 is a cross-sectional view of important parts of an input protection circuit of a conventional semiconductor device. An N-type diffusion layer 2 is formed on the top of a P-type semiconductor substrate 1 by ion implantation (to a depth of about 0.2 microns). The potential of the P-type semiconductor substrate 1 is set to zero or lower. An interlayer insulating film 3 containing silicon oxide as a main component is formed on the N-type diffusion layer 2 by chemical vapor deposition. A contact window 4 is formed in the interlayer insulating film 3 by etching, and connects the aluminum wiring 5 to the N-type diffusion layer 3.

発明が解決しようとする課題 しかしながら、上記従来の構造では、P型半導体基板1
とN型拡散層2とのPN接合部の逆方向接合耐圧(通常
12〜15ポルト程度)以上のサージ電圧が加わる場合
過大電流が流れ、PN接合部近傍の温度が上昇し、アル
ミニウム配線5の融点(660,4度)に達するとアル
ミニウムか溶融する。ひいてはN型拡散層3を破壊し、
P型半導体基板1にまでアルミニウム配線5か達し、P
N接合が破壊し入力保護回路部でのリーク電池が急増す
る不都合が生じる。
Problems to be Solved by the Invention However, in the above conventional structure, the P-type semiconductor substrate 1
When a surge voltage higher than the reverse junction breakdown voltage (usually about 12 to 15 ports) is applied to the PN junction between the aluminum wire 5 and the N-type diffusion layer 2, an excessive current flows, the temperature near the PN junction rises, and the aluminum wiring 5 Aluminum melts when it reaches its melting point (660.4 degrees). In turn, the N-type diffusion layer 3 is destroyed,
The aluminum wiring 5 reaches the P-type semiconductor substrate 1, and the P
This causes the inconvenience that the N junction is destroyed and the number of battery leaks in the input protection circuit increases rapidly.

課題を解決するための手段 この目的を達成するために、本発明の半導体装置は、入
力保護回路のアルミニウム配線とN型拡散層を接続する
コンタクト窓の下部に、ポリ→ノーイド配線(下層にポ
リシリコン、上層にタングステンシリサイドW S r
 xなどの高融点金属との2層構造配線)とコンタクト
窓を有する。
Means for Solving the Problems In order to achieve this object, the semiconductor device of the present invention has a poly->noid wiring (polygon in the lower layer) below the contact window connecting the aluminum wiring of the input protection circuit and the N-type diffusion layer. Silicon, upper layer tungsten silicide W S r
It has a two-layer wiring structure with a high melting point metal such as x) and a contact window.

作用 この構造によってサージ電圧印加時にアルミニウムが溶
融し、N型拡散層とアルミニウムが直接的に反応するこ
とをポリサイド配線により抑制される。従来アルミニウ
ムの融点に律速されていたザージに対する耐圧を、ポリ
サイド配線の融点(下層のポリシリコンの融点1414
℃、上層のタングステンシリサイドの融点3387℃)
にまで向」ニすることができる。
Effect: This structure prevents aluminum from melting when a surge voltage is applied and direct reaction between the N-type diffusion layer and aluminum, which is suppressed by the polycide wiring. The withstand voltage against surge, which was conventionally determined by the melting point of aluminum, has been changed by the melting point of polycide wiring (the melting point of the underlying polysilicon layer, 1414
°C, the melting point of the upper layer tungsten silicide is 3387 °C)
You can move up to "ni".

実施例 以下、本発明の一実施例について、図面を参照しながら
説明する。
EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings.

第1図は、本発明の一実施例における、半導体装置の入
力保護回路の要所断面図を示すものである。なお、1は
P型半導体基板、2はN型拡散層、3は層間絶縁膜、4
はコンタクト窓、5はアルミニウム配線であり、これら
は、従来例の構成と同じである。6はポリサイド配線(
下層にポリシリコン、上層にタングステンシリサイドW
Si、、などの高融点金属との2層構造配線)であり、
コンタクト窓4によりN型拡散層と接続し、上部コンタ
クト窓4によりアルミニウム配線5とも接続する。なお
、ポリサイド配線6、および下部コンタクト窓4は高集
積半導体装置に用いられる多層配線のレイアウトパター
ンを一部変更するだけで形成することができる。
FIG. 1 shows a cross-sectional view of important parts of an input protection circuit of a semiconductor device in an embodiment of the present invention. Note that 1 is a P-type semiconductor substrate, 2 is an N-type diffusion layer, 3 is an interlayer insulating film, and 4 is a P-type semiconductor substrate.
5 is a contact window, and 5 is an aluminum wiring, which are the same as those of the conventional example. 6 is polycide wiring (
Polysilicon on the bottom layer, tungsten silicide W on the top layer
It is a two-layer wiring structure with high melting point metals such as Si, etc.
It is connected to the N-type diffusion layer through the contact window 4, and also connected to the aluminum wiring 5 through the upper contact window 4. Note that the polycide wiring 6 and the lower contact window 4 can be formed by only partially changing the layout pattern of the multilayer wiring used in highly integrated semiconductor devices.

発明の効果 本発明の半導体装置入力保護回路は、アルミニウム配線
5とN型拡散層2との接続の間にポリサイド配線6とコ
ンタクト窓4を設けることにより、アルミニウムとN型
拡散層との接触を回避し、サージ印加時の温度上昇にと
もなう、アルミニウムの溶融によるPN接合部の破壊臨
界温度をポリシリコンの融点にまで上昇すること、すな
わち、ザージ耐圧を著しく高める効果が奏される。
Effects of the Invention The semiconductor device input protection circuit of the present invention prevents contact between aluminum and the N-type diffusion layer by providing the polycide wiring 6 and the contact window 4 between the connection between the aluminum wiring 5 and the N-type diffusion layer 2. This has the effect of raising the critical temperature for failure of the PN junction due to melting of aluminum to the melting point of polysilicon as the temperature rises when a surge is applied, that is, the surge withstand voltage is significantly increased.

また、従来品に比較してレイアウト面積を縮小させる効
果も奏される。
Additionally, the layout area can be reduced compared to conventional products.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例における半導体装置の断面図
、第2図は従来の半導体装置の断面図である。 1・・・・・・P型半導体基板、2・・・・・・N型拡
散層、3・・・・・・層間絶縁膜、4・・・・・・コン
タクト窓、5・・・・・・アルミニウム配線、6・・・
・・・ポリサイド配線。
FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a sectional view of a conventional semiconductor device. DESCRIPTION OF SYMBOLS 1... P-type semiconductor substrate, 2... N-type diffusion layer, 3... Interlayer insulating film, 4... Contact window, 5... ...Aluminum wiring, 6...
...Polycide wiring.

Claims (1)

【特許請求の範囲】[Claims]  半導体基板上に形成された第1の拡散層と、前記第1
の拡散層に第1の絶縁膜のコンタクト窓を介して接続さ
れた少なくともアルミニウムより融点の高い第1の導電
層と、前記第1の導電層と第2の絶縁膜のコンタクト窓
を介して接続されたアルミニウム層を備えたことを特徴
とする半導体装置。
a first diffusion layer formed on a semiconductor substrate;
A first conductive layer having a melting point higher than that of at least aluminum is connected to the diffusion layer of the first conductive layer through a contact window of a first insulating film, and the first conductive layer is connected through a contact window of a second insulating film. A semiconductor device comprising an aluminum layer.
JP16714390A 1990-06-25 1990-06-25 Semiconductor device Pending JPH0462838A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16714390A JPH0462838A (en) 1990-06-25 1990-06-25 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16714390A JPH0462838A (en) 1990-06-25 1990-06-25 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH0462838A true JPH0462838A (en) 1992-02-27

Family

ID=15844222

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16714390A Pending JPH0462838A (en) 1990-06-25 1990-06-25 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH0462838A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0722187A2 (en) * 1995-01-11 1996-07-17 Nec Corporation Semiconductor integrated circuit device with electrostatic protective function
US5968449A (en) * 1997-07-28 1999-10-19 Nippon Steel Welding Products & Engineering Co., Ltd. Iron base Si--Mn alloy or iron base Si--Mn--Ni alloy having good crushability and alloy powder thereof

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6439059A (en) * 1987-04-20 1989-02-09 Nec Corp Semiconductor device
JPH01283851A (en) * 1988-05-10 1989-11-15 Seiko Epson Corp Semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6439059A (en) * 1987-04-20 1989-02-09 Nec Corp Semiconductor device
JPH01283851A (en) * 1988-05-10 1989-11-15 Seiko Epson Corp Semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0722187A2 (en) * 1995-01-11 1996-07-17 Nec Corporation Semiconductor integrated circuit device with electrostatic protective function
EP0722187A3 (en) * 1995-01-11 1996-11-06 Nec Corp Semiconductor integrated circuit device with electrostatic protective function
US5844281A (en) * 1995-01-11 1998-12-01 Nec Corporation Semiconductor integrated circuit device with electrostatic protective function
US5968449A (en) * 1997-07-28 1999-10-19 Nippon Steel Welding Products & Engineering Co., Ltd. Iron base Si--Mn alloy or iron base Si--Mn--Ni alloy having good crushability and alloy powder thereof

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