EP0397780A1 - Ic with means for reducing esd damage - Google Patents

Ic with means for reducing esd damage

Info

Publication number
EP0397780A1
EP0397780A1 EP89902440A EP89902440A EP0397780A1 EP 0397780 A1 EP0397780 A1 EP 0397780A1 EP 89902440 A EP89902440 A EP 89902440A EP 89902440 A EP89902440 A EP 89902440A EP 0397780 A1 EP0397780 A1 EP 0397780A1
Authority
EP
European Patent Office
Prior art keywords
dielectric
layer
substrate
temperature
junction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP89902440A
Other languages
German (de)
French (fr)
Other versions
EP0397780A4 (en
Inventor
Jerome F. Lapham
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Analog Devices Inc
Original Assignee
Analog Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Analog Devices Inc filed Critical Analog Devices Inc
Publication of EP0397780A1 publication Critical patent/EP0397780A1/en
Publication of EP0397780A4 publication Critical patent/EP0397780A4/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • This invention relates to integrated circuits (ICs) comprising a substrate carrying a large number of circuit elements such as transistors and the like. More particularly, this invention relates to ICs having means to reduce damage from the effects of electrostatic dis ⁇ charge (ESD) .
  • ESD electrostatic dis ⁇ charge
  • Electrostatic Dis ⁇ charge (ESD) events It is well known that ICs are subject to serious damage or destruction as a result of Electrostatic Dis ⁇ charge (ESD) events.
  • the electrostatic voltage associated with the discharge can be developed by any of many sources, such as lightning, or friction between insulating bodies such as synthetic fiber clothing. Damage occurs when the ESD voltage is accidentally coupled to one of the circuit terminals and thence to some portion of the metal inter ⁇ connect layer of the IC.
  • the metal interconnect is typically an Aluminum layer laid down over an oxide coating overlying the top surface of the semiconductor.
  • the ESD voltage can cause a current to flow from the metal through the normally nonconducting oxide coating to the underlying semi ⁇ conductor. The current then leaves the IC through some other circuit terminal. The magnitude of the current is often sufficient to cause significant dam ⁇ age to the oxide, particularly by leaving it permanently conducting. The resulting shunt path often causes circuit failure.
  • ICs are made with semiconductive elements which, unlike MOS transistors, do not require thin oxides, for example bipolar transistors. These ICs nevertheless may as a result of the particular process steps carried out have thin oxides in certain places, or may have had the usual thermal oxide completely or almost completely removed in selected places, and are thus susceptible to ESD induced damage. This inven ⁇ tion describes a process for use with such ICs which eliminates the need to provide specific protection devices in accordance with prior practice.
  • a critical characteristic in accordance with the invention is that the total thickness of the insula- tive coating between the substrate and the metal intercon ⁇ nect is made great enough to assure that the dielectric breakdown voltage through the insulation is greater than the breakdown voltage of any of the junctions formed in the substrate.
  • the breakdown occurs at a junction, not through the insulative coating. Since junction damage is self-healing, the injury to the IC will not be permanent as it would be if the breakdown occurred in the insulative coating.
  • a second critical characteristic in accordance with the invention is that the thick insulative coating on the substrate is at least partly comprised of low- temperature (LT) dielectric material deposited after formation of the junctions. Deposition at relatively low temperatures assures that no detrimental changes occur in the already-formed junctions.
  • LT low- temperature
  • an IC structure wherein the insulative coating for the sub ⁇ strate comprises two adjacent layers just beneath the metal interconnect.
  • the first layer of the coating is the usual thermally-grown Silicon dioxide, formed at a relatively high temperature during conventional process ⁇ ing of the integrated circuit.
  • the second layer is a deposited layer of Silicon dioxide, developed at a rela ⁇ tively low temperature, sufficiently low to assure that already-formed junctions in the IC are not altered detri ⁇ mentally during deposition of the oxide.
  • the thermally-grown oxide laid down during conventional IC processing may be partially or wholly removed, at least in selected regions of the substrate, prior to deposition of a low-temperature insulative coating of thickness suf ⁇ ficient to minimize the possibility of ESD damage in accordance with the invention.
  • FIGURE 1 is a vertical section through an inte ⁇ grated circuit chip, not to scale and with certain aspects shown pictorially;
  • FIGURE 2 is a schematic diagram representing elements of the IC chip of Figure 1;
  • FIGURE 3 is a graphical presentation to aid in explaining the operation of the invention.
  • an integrated circuit comprising a substrate 10, commonly made of Silicon and shown in this example as being p-type.
  • This substrate is supplied with n-type impurities by conven ⁇ tional techniques, such as chemical vapor deposition (CVD) or ion implantation. These impurities are driven-in (diffused) into the substrate so as to form an n-type region 12 estab ⁇ lishing a junction 14 with the p-type substrate material.
  • a diode symbol 16 is shown at the junction to illustrate pic ⁇ torially the electrical characteristics of the junction.
  • a typical IC will of course include a multiplic ⁇ ity of other junctions (not shown) , forming both diodes and transistors which together comprise the elements of the cir ⁇ cuit of the particular IC device. These other junctions are not shown herein in order to simplify the presentation.
  • a protective insulating di ⁇ electric layer such as Silicon dioxide, illustrated at 20, is thermally grown over the surface of the substrate, in known fashion.
  • This layer is formed at a relatively high temperature, preferably above 700°C.
  • 0 2 oxygen
  • H_0 water vapor
  • Si ⁇ 2 Silicon dioxide
  • portions of the ther ⁇ mally-grown oxide must be removed in various places, as part of the implant and/or diffusion processes involved in making the many IC junctions, the final thickness of this oxide layer 20 will vary considerably from place to place, as shown in Figure 1.
  • a layer of metallization such as illustrated at 22 normally is laid down next, over the thermally-grown oxide 20, in order to make electrical connections to selected regions of the sub ⁇ strate surface.
  • ESD electrostatic discharge
  • Such ESD voltage is diagrammatic- ally illustrated in Figure 1 by a symbolic voltage source 24 with one terminal poised to be connected to the metalli ⁇ zation layer 22, and its other terminal connected to ground. It has been found that the excessive sensitivity to ESD in the prior art IC constructions can be overcome or substantially mitigated by a new IC construction, and process of making such an IC, as will now be described.
  • an additional layer 26 of oxide is laid down, in this case over the thermally-grown layer 20, just beneath the metallization layer 22.
  • This addi ⁇ tional layer is formed at a relatively low temperature (below 700°C) .
  • This distinction is important, because the addition of a low- temperature (LT) oxide assures that creation of the layer does not adversely affect the junctions which already have been formed in the substrate.
  • the additional layer 26 is made sufficiently thick so as to assure that the total thickness of the oxide coating (20, 26) is sufficient that the dielectric break ⁇ down voltage (V-- TM ..) of the dielectric material between the substrate and metallization layer 22 is greater than the junction breakdown voltage ( v ⁇ BKr of the IC, in this case, the breakdown voltage of the junction 14.
  • Figure 2 illustrates how the ESD source 24 is in effect connected to the paralleled combination of the minimum breakdown- voltage dielectric region (i.e., where the dielectric is thinnest, and shown as a capacitor 30) and the minimum breakdown-voltage junction (diode 16, illustratively).
  • the current in the dielectric gradually increases (the magnitude being shown exaggeratedly in Figure 3) with increases in voltage until the dielectric breakdown voltage is reached. At that point, the current increases rapidly, and the voltage decreases to a very low level (reflecting the near short circuit represented by the dielectric material after break ⁇ down) .
  • the magnitude of the dielectric breakdown voltage V__, VT _. is increased as compared to the breakdown voltage for the thermally-grown layer (20) by itself.
  • the actual dielectric breakdown voltage is given (somewhat conservatively) by the following relationship:
  • V DBKD ( * 06 Vo l ts / A ngstroms) (thickness in Angstroms)
  • a thickness of 10,000 A thus will provide protection against an ESD event of about 600 volts. With rare exceptions, all IC junctions break down at voltages less than 600 volts.
  • the final dielectric coating (20, 26) prefer ⁇ ably is made sufficiently thick that its breakdown voltage V BKD is greater than the junction breakdown voltage V , shown as a vertical dotted line in the first quadrant of the Figure 3 graph.
  • the diode 16 will be forward-biased and will pass current at volt ⁇ ages much less than the dielectric breakdown voltage of the oxide, thus protecting the oxide in the same way.
  • the low-temperature oxide coating can be depos ⁇ ited prior to the metallization mask step in any of various ways.
  • chemical vapor deposition CVD
  • silane gas SiH.
  • Sputtering also can be employed.
  • Still other sources and oxidants can be used, e.g. tetraethyl orthosilicate and nitrous oxide.
  • the Silicon for the low temperature SiOick coating is supplied externally, i.e. it is not derived from the substrate as it is with thermally-grown (high-temperature) oxide.
  • the substrate is provided with a multilayer oxide coating, wherein one layer is a high-temperature (HT) layer next to the substrate, and the other is a low-temper ⁇ ature (LT) layer 26 just beneath the metallization layer.
  • HT high-temperature
  • LT low-temper ⁇ ature
  • the high-temperature oxide may be partially or fully removed, at least in some places, prior to deposit of the low-temper ⁇ ature (LT) insulative coating, in which event the LT coat ⁇ ing thickness must be made sufficient by itself to assure the necessary dielectric breakdown voltage.
  • LT low-temper ⁇ ature

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

La puce de circuit intégré décrite, qui est pourvue d'organes empêchant ou réduisant les dommages dus aux décharges électrostatiques, utilise un revêtement diélectrique épais (20, 26) en oxyde isolant placé entre la surface du substrat de la puce et le film de métallisation (22) utilisé pour établir un contact avec des régions du substrat (10). Au moins une partie de cette couche (26) est formée à des températures inférieures à 700°C. Le revêtement (20, 26) est suffisamment épais partout, de sorte que sa tension de rupture est supérieure à la tension de rupture de n'importe quelle jonction (14) présente dans le substrat (10), ce qui est une assurance que les ruptures causées par des décharges électrostatiques se produisent toujours dans la jonction (14), qui se répare d'elle même, plutôt que dans le revêtement diélectrique (20, 26), où le dommage pourrait être permanent.The integrated circuit chip described, which is provided with means preventing or reducing damage due to electrostatic discharges, uses a thick dielectric coating (20, 26) of insulating oxide placed between the surface of the chip substrate and the metallization film (22) used to make contact with regions of the substrate (10). At least part of this layer (26) is formed at temperatures below 700 ° C. The covering (20, 26) is sufficiently thick everywhere, so that its breaking tension is greater than the breaking tension of any junction (14) present in the substrate (10), which is an assurance that the ruptures caused by electrostatic discharges always occur in the junction (14), which repairs itself, rather than in the dielectric coating (20, 26), where the damage could be permanent.

Description

IC WITH MEANS FOR REDUCING ESD DAMAGE
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to integrated circuits (ICs) comprising a substrate carrying a large number of circuit elements such as transistors and the like. More particularly, this invention relates to ICs having means to reduce damage from the effects of electrostatic dis¬ charge (ESD) .
2. Prior Art
It is well known that ICs are subject to serious damage or destruction as a result of Electrostatic Dis¬ charge (ESD) events. The electrostatic voltage associated with the discharge can be developed by any of many sources, such as lightning, or friction between insulating bodies such as synthetic fiber clothing. Damage occurs when the ESD voltage is accidentally coupled to one of the circuit terminals and thence to some portion of the metal inter¬ connect layer of the IC.
The metal interconnect is typically an Aluminum layer laid down over an oxide coating overlying the top surface of the semiconductor. The ESD voltage can cause a current to flow from the metal through the normally nonconducting oxide coating to the underlying semi¬ conductor. The current then leaves the IC through some other circuit terminal. The magnitude of the current is often sufficient to cause significant dam¬ age to the oxide, particularly by leaving it permanently conducting. The resulting shunt path often causes circuit failure.
Various attempts have been made to prevent damage from ESD events. For example, semiconductor elements which require thin oxides, such as MOS tran¬ sistors and MOS capacitors, are often protected by additional devices which bypass the ESD current and thereby protect the element in question. In general, a separate bypass device must be provided for each ele¬ ment requiring protection. However, in some particular cases the protection device may be shared by more than one element requiring protection. In any event, pro¬ viding protection devices to prevent damage from ESD events adds to the complexity of the IC, requires addi¬ tional IC area, and generally is a quite undesirable practice.
Many ICs are made with semiconductive elements which, unlike MOS transistors, do not require thin oxides, for example bipolar transistors. These ICs nevertheless may as a result of the particular process steps carried out have thin oxides in certain places, or may have had the usual thermal oxide completely or almost completely removed in selected places, and are thus susceptible to ESD induced damage. This inven¬ tion describes a process for use with such ICs which eliminates the need to provide specific protection devices in accordance with prior practice. SUMMARY OF THE INVENTION A critical characteristic in accordance with the invention is that the total thickness of the insula- tive coating between the substrate and the metal intercon¬ nect is made great enough to assure that the dielectric breakdown voltage through the insulation is greater than the breakdown voltage of any of the junctions formed in the substrate. Thus, when electrostatic discharge occurs of sufficient intensity to cause breakdown, the breakdown occurs at a junction, not through the insulative coating. Since junction damage is self-healing, the injury to the IC will not be permanent as it would be if the breakdown occurred in the insulative coating.
A second critical characteristic in accordance with the invention is that the thick insulative coating on the substrate is at least partly comprised of low- temperature (LT) dielectric material deposited after formation of the junctions. Deposition at relatively low temperatures assures that no detrimental changes occur in the already-formed junctions.
In one preferred embodiment of the invention, to be described hereinbelow in detail, an IC structure is provided wherein the insulative coating for the sub¬ strate comprises two adjacent layers just beneath the metal interconnect. The first layer of the coating is the usual thermally-grown Silicon dioxide, formed at a relatively high temperature during conventional process¬ ing of the integrated circuit. The second layer is a deposited layer of Silicon dioxide, developed at a rela¬ tively low temperature, sufficiently low to assure that already-formed junctions in the IC are not altered detri¬ mentally during deposition of the oxide. In other embodiments of the invention, the thermally-grown oxide laid down during conventional IC processing may be partially or wholly removed, at least in selected regions of the substrate, prior to deposition of a low-temperature insulative coating of thickness suf¬ ficient to minimize the possibility of ESD damage in accordance with the invention.
Still other objects, aspects and advantages of this invention will in part be pointed out in and in part apparent from, the following detailed description of one embodiment considered together with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS FIGURE 1 is a vertical section through an inte¬ grated circuit chip, not to scale and with certain aspects shown pictorially;
FIGURE 2 is a schematic diagram representing elements of the IC chip of Figure 1; and
FIGURE 3 is a graphical presentation to aid in explaining the operation of the invention.
DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT
Referring first to Figure 1, there is shown an integrated circuit (IC) comprising a substrate 10, commonly made of Silicon and shown in this example as being p-type. This substrate is supplied with n-type impurities by conven¬ tional techniques, such as chemical vapor deposition (CVD) or ion implantation. These impurities are driven-in (diffused) into the substrate so as to form an n-type region 12 estab¬ lishing a junction 14 with the p-type substrate material. A diode symbol 16 is shown at the junction to illustrate pic¬ torially the electrical characteristics of the junction. A typical IC will of course include a multiplic¬ ity of other junctions (not shown) , forming both diodes and transistors which together comprise the elements of the cir¬ cuit of the particular IC device. These other junctions are not shown herein in order to simplify the presentation.
During the formation of the various junctions throughout the substrate 10, a protective insulating di¬ electric layer such as Silicon dioxide, illustrated at 20, is thermally grown over the surface of the substrate, in known fashion. This layer is formed at a relatively high temperature, preferably above 700°C. In such growth, 02 (oxygen) , in pure gaseous form or as part of water vapor (H_0) , combines with Silicon atoms from the substrate to form Silicon dioxide (Siθ2) • Since portions of the ther¬ mally-grown oxide must be removed in various places, as part of the implant and/or diffusion processes involved in making the many IC junctions, the final thickness of this oxide layer 20 will vary considerably from place to place, as shown in Figure 1.
In accordance with known prior art, a layer of metallization such as illustrated at 22 normally is laid down next, over the thermally-grown oxide 20, in order to make electrical connections to selected regions of the sub¬ strate surface. Experience with devices formed in that fashion has shown an excessive degree of sensitivity to electrostatic discharge (ESD) voltages developed on the metallization layer 22. Such ESD voltage is diagrammatic- ally illustrated in Figure 1 by a symbolic voltage source 24 with one terminal poised to be connected to the metalli¬ zation layer 22, and its other terminal connected to ground. It has been found that the excessive sensitivity to ESD in the prior art IC constructions can be overcome or substantially mitigated by a new IC construction, and process of making such an IC, as will now be described. In this new construction, an additional layer 26 of oxide is laid down, in this case over the thermally-grown layer 20, just beneath the metallization layer 22. This addi¬ tional layer, however, unlike the initial layer 20, is formed at a relatively low temperature (below 700°C) . This distinction is important, because the addition of a low- temperature (LT) oxide assures that creation of the layer does not adversely affect the junctions which already have been formed in the substrate.
The additional layer 26 is made sufficiently thick so as to assure that the total thickness of the oxide coating (20, 26) is sufficient that the dielectric break¬ down voltage (V--™..) of the dielectric material between the substrate and metallization layer 22 is greater than the junction breakdown voltage (v τBKr of the IC, in this case, the breakdown voltage of the junction 14. Figure 2 illustrates how the ESD source 24 is in effect connected to the paralleled combination of the minimum breakdown- voltage dielectric region (i.e., where the dielectric is thinnest, and shown as a capacitor 30) and the minimum breakdown-voltage junction (diode 16, illustratively). When the ESD reaches a level sufficient to cause break¬ down, that breakdown will in accordance with the invention occur in the junction (e.g. diode 16) , not in the dielectric (20, 26) of the capacitor 30. This can graphically be explained by reference to Figure 3 which is a current-voltage (I-V) plot where the solid-line curve 36 is for a dielectric layer such as repre¬ sented by the composite coating 20, 26, and the dotted line curve 38 is for a junction such as diode 16.
As shown by the solid-line curve 36, the current in the dielectric gradually increases (the magnitude being shown exaggeratedly in Figure 3) with increases in voltage until the dielectric breakdown voltage is reached. At that point, the current increases rapidly, and the voltage decreases to a very low level (reflecting the near short circuit represented by the dielectric material after break¬ down) .
By providing an additional oxide coating (i.e. by applying a deposited layer (26) of low-temperature oxide as discussed above) , the magnitude of the dielectric breakdown voltage V__,VT_. is increased as compared to the breakdown voltage for the thermally-grown layer (20) by itself. The actual dielectric breakdown voltage is given (somewhat conservatively) by the following relationship:
VDBKD = (*06 Volts/Angstroms) (thickness in Angstroms)
o
A thickness of 10,000 A thus will provide protection against an ESD event of about 600 volts. With rare exceptions, all IC junctions break down at voltages less than 600 volts. The final dielectric coating (20, 26) prefer¬ ably is made sufficiently thick that its breakdown voltage V BKD is greater than the junction breakdown voltage V , shown as a vertical dotted line in the first quadrant of the Figure 3 graph. Thus, for positive ESD voltage excur¬ sions, breakdown will first occur at the junction (e.g. junction 14) , and this will prevent any subsequent break¬ down in the dielectric material. Since such a junction breakdown is self-healing (i.e. it returns to operative condition after a short period of time) , there will be no permanent damage to the IC as a result of the electrostatic discharge. For a negative ESD voltage excursion, the diode 16 will be forward-biased and will pass current at volt¬ ages much less than the dielectric breakdown voltage of the oxide, thus protecting the oxide in the same way.
The low-temperature oxide coating can be depos¬ ited prior to the metallization mask step in any of various ways. Typically, chemical vapor deposition (CVD) will be used. For example, silane gas (SiH.) can be caused to flow over the wafers together with oxygen, there¬ by to form Si02. Sputtering also can be employed. Still other sources and oxidants can be used, e.g. tetraethyl orthosilicate and nitrous oxide. In each case, the Silicon for the low temperature SiO„ coating is supplied externally, i.e. it is not derived from the substrate as it is with thermally-grown (high-temperature) oxide. The deposition of the additional layer is performed at a temperature less than 700°C so as to assure that the already-formed junc¬ tions in the IC are not adversely affected as a result of the additional processing. In the particular preferred embodiment described hereinabove, the substrate is provided with a multilayer oxide coating, wherein one layer is a high-temperature (HT) layer next to the substrate, and the other is a low-temper¬ ature (LT) layer 26 just beneath the metallization layer. It will be understood, however, that the concept of the invention is to deposit low-temperature dielectric insula¬ tion on the substrate in sufficient thickness to assure that the overall dielectric breakdown voltage is greater than the junction breakdown voltage. In some cases, the high-temperature oxide may be partially or fully removed, at least in some places, prior to deposit of the low-temper¬ ature (LT) insulative coating, in which event the LT coat¬ ing thickness must be made sufficient by itself to assure the necessary dielectric breakdown voltage.
Accordingly, although a specific preferred embod¬ iment of the invention has been described hereinabove in detail, it is to be understood that this is for the purpose of providing an illustrative example of the invention and is not to be construed as necessarily limitative, since it is apparent that those skilled in this art can make many modifications as required for specific applications without departing from the scope of the invention.

Claims

What is claimed is:
1. In an integrated circuit of the type comprising a semiconductive substrate with selected regions having impurities forming at least one junction, and wherein metal interconnect is laid down over the substrate to make connection to at least one of said regions, there also being dielectric insulation between said metal inter¬ connect and the surface of said substrate; that improvement for reducing damage to said integrated circuit due to electrostatic discharges wherein said dielectric insulation comprises at least one layer of low-temperature dielectric sufficiently thick that the dielectric breakdown voltage of said di¬ electric insulation is greater than the breakdown voltage of said junction.
2. The integrated circuit as claimed in Claim 1, wherein said dielectric insulation comprises two layers, one thermally-grown layer, and the other a low-temperature deposited layer.
3. The integrated circuit as claimed in Claim 1, wherein said substrate is formed of Silicon and said dielectric is Silicon dioxide.
4. The method of making an integrated circuit which is resistant to damage from electrostatic discharge, com¬ prising the steps of: providing a se iconductive substrate with impur¬ ities to form at least one junction; growing high-temperature dielectric over said susbtrate as part of the IC forming process; depositing a layer of low-temperature dielectric over said substrate of sufficient thickness that said sub¬ strate is formed with dielectric material having a dielec¬ tric breakdown voltage greater than the junction breakdown voltage; and forming a metal interconnect layer over said layer of low-temperature dielectric to make electrical connection to said junction as well as to other regions of said IC.
5. The method of Claim 4, wherein said dielectric material on said substrate includes two layers, one being said layer of high-temperature dielectric, and the other being said layer of low-temperature dielectric laid down over said layer of high-temperature dielectric, said two layers having a combined thickness sufficient to create a dielectric breakdown voltage greater than the breakdown voltage of said junction.
6. The method of Claim 5, wherein said first layer is thermally grown at a temperature greater than 700°C; and said second layer is deposited at a temperature less than 700°C.
7. The method of Claim 4, wherein said low-temper¬ ature dielectric is deposited by chemical vapor deposition.
8. The method of Claim 4, wherein said low-temper¬ ature dielectric is deposited by sputtering.
EP19890902440 1988-02-02 1989-01-23 Ic with means for reducing esd damage Withdrawn EP0397780A4 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15155588A 1988-02-02 1988-02-02
US151555 1988-02-02

Publications (2)

Publication Number Publication Date
EP0397780A1 true EP0397780A1 (en) 1990-11-22
EP0397780A4 EP0397780A4 (en) 1991-09-18

Family

ID=22539291

Family Applications (1)

Application Number Title Priority Date Filing Date
EP19890902440 Withdrawn EP0397780A4 (en) 1988-02-02 1989-01-23 Ic with means for reducing esd damage

Country Status (4)

Country Link
EP (1) EP0397780A4 (en)
JP (1) JPH03502389A (en)
CA (1) CA1303753C (en)
WO (1) WO1989007334A1 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2268328B (en) * 1992-06-30 1995-09-06 Texas Instruments Ltd A capacitor with electrostatic discharge protection
GB9907910D0 (en) * 1999-04-07 1999-06-02 Koninkl Philips Electronics Nv Thin film capacitor element
US7838965B2 (en) 2005-03-02 2010-11-23 Nxp B.V. ESD protected integrated capacitor with large capacity
JP5633663B1 (en) * 2013-01-23 2014-12-03 株式会社村田製作所 Composite electronic component of thin film capacitor and Zener diode and method for manufacturing the same

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0057024A1 (en) * 1981-01-26 1982-08-04 Koninklijke Philips Electronics N.V. Semiconductor device having a safety device
US4435447A (en) * 1978-12-26 1984-03-06 Fujitsu Limited Method for forming an insulating film on a semiconductor substrate surface

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0732237B2 (en) * 1985-04-08 1995-04-10 エスジ−エス−トムソン マイクロエレクトロニクス インコーポレイテッド Electrostatic discharge input protection circuit
US4763184A (en) * 1985-04-30 1988-08-09 Waferscale Integration, Inc. Input circuit for protecting against damage caused by electrostatic discharge
US4806999A (en) * 1985-09-30 1989-02-21 American Telephone And Telegraph Company, At&T Bell Laboratories Area efficient input protection
US4736271A (en) * 1987-06-23 1988-04-05 Signetics Corporation Protection device utilizing one or more subsurface diodes and associated method of manufacture

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4435447A (en) * 1978-12-26 1984-03-06 Fujitsu Limited Method for forming an insulating film on a semiconductor substrate surface
EP0057024A1 (en) * 1981-01-26 1982-08-04 Koninklijke Philips Electronics N.V. Semiconductor device having a safety device

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
ELECTRICAL OVERSTRESS/ELECTROSTATIC DISCHARGE SYMPOSIUM PROCEEDINGS, Philadelphia PA, 1984, pages 202-209; C.M. LIN et al.: "A CMOS VLSI ESD input protection device, DIFIDW" *
See also references of WO8907334A1 *

Also Published As

Publication number Publication date
EP0397780A4 (en) 1991-09-18
WO1989007334A1 (en) 1989-08-10
CA1303753C (en) 1992-06-16
JPH03502389A (en) 1991-05-30

Similar Documents

Publication Publication Date Title
US4405933A (en) Protective integrated circuit device utilizing back-to-back zener diodes
US5248892A (en) Semiconductor device provided with a protection circuit
US4892844A (en) Making a low resistance three layered contact for silicon devices
KR100517770B1 (en) Electrostatic Discharge Protection Element
US4057844A (en) MOS input protection structure
EP0656152A1 (en) Mos device having protection against electrostatic discharge
US4609931A (en) Input protection MOS semiconductor device with zener breakdown mechanism
US4928157A (en) Protection diode structure
EP0289431B1 (en) Integrated circuit protected against overvoltages
US5141898A (en) Integrated circuit with means for reducing ESD damage
EP0397780A1 (en) Ic with means for reducing esd damage
US6208011B1 (en) Voltage-controlled power semiconductor device
EP0356039A1 (en) MOS semiconductor integrated circuit
US6677207B1 (en) Vanishingly small integrated circuit diode
JPH0462838A (en) Semiconductor device
GB2295049A (en) Overvoltage protection for integrated circuits
JPS63301555A (en) Semiconductor device
EP0186567A1 (en) Diac with coplanar electrodes
JPH01166562A (en) Semiconductor device
JPH06204407A (en) Diode element
JPH01140655A (en) Semiconductor integrated circuit
JPS5963772A (en) Semiconductor device
JPS61102766A (en) Semiconductor integrated circuit
JPH0214781B2 (en)
JPH06252349A (en) Semiconductor device and manufacture of semiconductor device

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 19900627

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): DE FR GB

A4 Supplementary search report drawn up and despatched
AK Designated contracting states

Kind code of ref document: A4

Designated state(s): DE FR GB

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION HAS BEEN WITHDRAWN

18W Application withdrawn

Withdrawal date: 19930203