JPS59207652A - Semiconductor integrated circuit device and manufacture thereof - Google Patents

Abstract

PURPOSE:To form resistor regions in a wiring formed by a silicide forming metallic wiring material, by providing a silicide forming metal or its silicide layer on a part other than a resistor region in a silicon layer. CONSTITUTION:The first wiring layer is formed on an insulating film 2'. An insulating film 5 is formed on a lower layer part 4. Impurities are diffused in the lower layer part 4, and a lower layer part 4' is formed. An upper layer part 6 of molibdenum silicide is formed so that it is overlapped on the lower layer part 4'. Photoresist is formed on the upper layer part 6. With the photoresist as a mask, a resistor region part and a gate region part are formed. Diffused layers 9 of source and drain regions are formed. Then, a window is formed in the resistor region part and phosphorus glass 13 is deposited in the window. The insulating film in the diffused layers and the insulating film on the upper layer part 6 are removed and contact holes 12 are formed. Thereafter, a phosphorus diffused layer 14 is formed by phosphorus deposition or ion implantation. Then an aluminum wiring 15 is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit device having a resistance element in wiring, and a method for manufacturing the semiconductor integrated circuit device.

Recent trends in semiconductor integrated circuit devices (10) include higher integration, higher speed, and lower power consumption. Molybdenum (Mo) is used as a countermeasure against this tendency.

Tungsten (W), tantalum (Ta), titanium (T1)
) and other high-melting point metal wiring materials [hereinafter simply referred to as silicide (S
It is considered to use a silicide-forming metal wiring material] or a silicide wiring material formed from the silicide-forming metal wiring material and a silicon (Si) material. These wiring materials have low resistance,
Therefore, the information propagation speed is fast, and it has the advantage of being suitable for reducing power consumption.

However, for example, static memory [hereinafter simply referred to as SRAM (Static Random Access)]
When forming a memory element (called "Memory"), a resistor is required on the wiring within the element, but at present it has not been possible to form a resistor on the wiring using the silicide wiring material.

An object of the present invention is to provide a semiconductor integrated circuit device in which a resistance region is formed in a wiring formed from a silicide-forming metal wiring material, and a method for manufacturing the same.

Hereinafter, the present invention will be described in detail along with one embodiment.

In addition, in all the figures, parts having similar functions are given the same symbols, and explanations of overlapping parts are omitted. This embodiment describes an insulated gate field effect transistor (hereinafter simply referred to as MISFET) for forming an SRAM memory element made of a single layer of polycrystalline silicon, and the MISFET.
A semiconductor integrated circuit device having a resistance element having a high resistance value connected to the drain side of an SFET will be described.

1 to 10 are partial cross-sectional views of a semiconductor device at each manufacturing step 2 for explaining an embodiment of the present invention.

As shown in FIG. 1, a semiconductor substrate 1 made of silicon single crystal containing p-type impurities and having a resistivity of about 20 [Ω·Cm] is coated with a resistivity of 40% by heat treatment at about 1000°C.
An insulating film 2 of silicon dioxide having a current of about 0 A is formed. Silicon nitride (SI3N4
) insulating film with OvD (Ochemical Vapo)
It is formed by the ur Deposition method.

The thickness of this insulating film may be about 600A. The insulating film 3 of the oxidation-resistant mask is formed by removing the insulating film formed by the OvD method except for the semiconductor element forming portion.

After the above step, as shown in FIG. 2, the semiconductor substrate 1 exposed from the oxidation-resistant mask insulating film 3 is oxidized by heat treatment at about 1000° C. to form a field insulating film portion 20 of silicon dioxide. form. The thickness of this field insulating film portion 20 is, for example, 1 μm.
It is enough.

After the step shown in FIG. 2, the insulating film 3 is removed and the entire surface of the insulating film 2 is etched (Pitch-ing) so that the surface of the semiconductor substrate 1 in the semiconductor element forming portion is exposed. Thereafter, as shown in FIG. 3, an insulating film 2' which also serves as a gate insulating film is formed on the surface of the semiconductor substrate by thermal oxidation treatment at about 1000°C. The thickness of this insulating film 2' may be, for example, about 400 Å in the semiconductor element forming portion.

On the formed insulating film 2', as shown in FIG.
A lower layer portion 4 of layer wiring is formed. This lower layer portion 4 has a high resistance value, and may be formed, for example, of polycrystalline silicon to a thickness of about 3000 Å using a low-pressure OvD method.

An insulating film of silicon nitride with a thickness of about 500 A is formed on the lower layer portion 4 formed above, and as shown in FIG.
The insulating film other than the area where the resistor is to be formed is removed, and an insulating film 5 serving as a diffusion mask is formed. Thereafter, an impurity such as phosphorus (P), for example, is diffused into the lower layer 4 to form a lower layer 4' in which the resistance value of the lower layer 4 is reduced to about 40 [Ω/hole]. Note that the resistance value of the lower layer portion 4 under the insulating film 5 remains substantially unchanged and becomes a high resistance region.

Next, as shown in FIG. 6, molybdenum, a high melting point metal, or molybdenum silicide (for example, Mo5i
z) form the upper layer part 6. The upper layer portion 6 may be formed by depositing the above material to a thickness of about 4000 Å using, for example, sputtering technology.

Further, although molybdenum or molybdenum silicide was used as the wiring material in this example, silicide-forming metal wiring materials such as tungsten, tantalum, titanium, etc.
A silicide wiring material made of the silicon-forming metal wiring material and a silicon material may be used. In addition, the wiring materials of the lower layer part 4' and the upper layer part 6 are partially or entirely removed from the interface between the wiring materials by the sputtering technique for forming the upper layer part 6 and the heat treatment performed thereafter. They fuse together to form silicide.

The degree of this fusion can be controlled by each heat treatment step and the thickness of each wiring material. In addition, the lower layer 4
' and the upper layer 6 may not be silicided if necessary. Further, when the upper layer portion 6 is formed by sputtering technology, even incomplete silicide is formed into silicide by each of the heat treatment steps described above.

After the process shown in FIG. 6, a photoresist (not shown) is formed on the upper layer portion 6 to form a source of the semiconductor element portion.

A mask is formed by removing the photoresist in the region where the drain region is to be formed. Using this formed mask, as shown in FIG. 7, a resistance region section 7 and a gate region section 8 are formed by, for example, seven-layer dry etching. Furthermore, using the mask, n'' type impurities are implanted into the formation portions of the source and drain regions by ion implantation, and diffusion layers 9 of the source and drain regions are formed by heat treatment,
Remove mask. In the ion implantation for forming the diffusion layer 9, impurities of arsenic (As) ions were added to 100 [Ke
V], with an energy of 2X10”C atoms/cm]
All you have to do is add impurities.

After the process shown in FIG. 7, a photoresist is formed on the entire surface of the resistive region 7. The photoresist on the diffusion layer 9 is removed and the eighth
As shown in the figure, a mask 10 is formed. This mask 1
0, the upper layer 6 on the insulating film 5 in the resistance region 7 is removed by fluorine-based dry etching to form a window 11. As a result, the upper layer 6 formed of molybdenum or molybdenum silicide is electrically disconnected, and only the high-resistance lower layer 4 is electrically connected, forming a high-resistance resistance region. After this, the mask 10 is removed.

After the above step, as shown in FIG.
was deposited at about 7000A and heated at about 1000℃.
Heat treat for about 0 minutes. After that, the insulating film on the diffusion layer 9 and the insulating film on the upper layer part 6 are removed by photoetching,
A contact hole 12 is formed. Furthermore, phosphorus is deposited in contact hole 1 by phosphorus deposition or ion implantation.
2 and is diffused deeper than the diffusion layer 9, forming a layer 14 as shown by the dotted line. This phosphorus diffusion layer 14 improves the reliability of contact with the electrode formed on the diffusion layer 14. For example, if the depth of the diffusion layer 9 is 0.4 μm, the depth of the diffusion layer 14 can be 0.711 m.

After the step shown in FIG. 9, as shown in FIG. 10, an aluminum wiring 15 having a thickness of about 1 μm is formed, and the semiconductor device of this example is completed. In FIG. 10, a MISFET is formed in the X section and a resistor is formed in the Y section.

Incidentally, in the above embodiment, the steps after FIG. 8 may be as shown in FIGS. 11 to 13.

That is, after the step shown in FIG. 7, as shown in FIG. 11, the phosphor glass 13 is formed on the entire surface, and after heat treatment, the upper layer 6 and the phosphor glass 13 on the insulating film 5 of the resistance region 7 are removed by photo-etching. The insulating film 2' and the phosphor glass 13 on the diffusion layer 9 and the phosphor glass 13 on the upper layer 6 are removed. As a result, the upper layer 6 formed of molybdenum or molybdenum silicide is electrically disconnected.
Only the lower layer portion 4 of high resistance is electrically connected to form a high resistance region and a contact hole 12. Thereafter, as shown in FIG. 12, the contact hole 12 is formed by phosphorus deposition or ion implantation.
Phosphorus is diffused deeper than the diffusion layer 9 through the phosphorus layer 9 to form a layer 14 as shown by the dotted line. Thereafter, as shown in FIG. 13, the AJ wiring 15 is formed to complete the semiconductor device of this embodiment.

This method can reduce the number of photoresist steps by one compared to the steps described above with reference to FIGS. 8 to 10.

FIG. 14 is a circuit diagram for configuring one element of the SRAM according to the embodiment. 30 is the power line, 31A, 31
B is a data line, 32 is a word line, 33A, 33B, 33
0 and 33D are MOSFETs (Metal Qxi
de Sem1conductor FieldE
effect Transistor), 34A, 34B
is a resistance, and 35 is a ground. The high-resistance resistance regions of the embodiment described above are formed in the resistors 34A and 34B.

FIG. 15 shows an example of a layout diagram for configuring the memory element section of the SRAM formed according to the above embodiment, and FIG. 14 shows an equivalent circuit diagram thereof. The symbols in FIG. 15 correspond to those in FIG. 14, and as shown in the figure, the shaded portions are the resistors 34A and 34B.

It goes without saying that the present invention is not limited to the embodiments described above, and can be modified in various ways without changing the gist thereof. For example, although the above embodiments have been described with respect to a semiconductor device made of one layer of polycrystalline silicon, the present invention may also be applied to a semiconductor device made of two or more layers of polycrystalline silicon.

Furthermore, although the above embodiments have been described with respect to the formation of an SRAM, the present invention may be applied to other circuits or peripheral resistance regions.

As explained above, according to the present invention, wiring of a semiconductor device is formed using a silicide-forming metal wiring material with extremely high conductivity, or a silicide formed from the silicide-forming metal wiring material and a silicon material, and A resistance region can be easily formed in the wiring. Therefore,
Since a highly conductive wiring layer and a resistance region can be formed within one element of a semiconductor integrated circuit device, a semiconductor device with improved speed and higher integration can be provided.

[Brief explanation of the drawing]

1 to 13 are partial cross-sectional views of a semiconductor device in each manufacturing process for explaining one embodiment of the present invention, and FIG. 14 is a structure configuring a memory module of an SRAM according to the embodiment. FIG. 15 is a layout diagram of a semiconductor integrated circuit device in which the memory section of the SRAM shown in FIG. 14 is formed according to the present invention. 1... semiconductor substrate, 2. 2', 3. Death...Insulating film, 20...Field insulating film part, 4.4'...
Lower layer part, 6... Upper layer part, 7... Resistance area part, 8...
・Gate region portion, 9...diffusion layer, 10...mask,
11...Window, 12...Contact hole, 13...
- Phosphorus glass, 14... Phosphorus diffusion layer, 14'... Double layer of arsenic and phosphorus, 15... Aluminum wiring, 30
...Power line, 31A, 31B...Data line, 32
...Word line, 33A-33D...MISFEIT
, 34A, 34B...resistance, 35...earth. Agent Patent Attorney Akira Takahashi Mistake 1 Diagram? Fig. 2 Fig. 3 Fig. 4 Fig. 5 Fig. 12 Fig. 13 /, f, f4 /, s ) I I / / Fig. 14 Fig. 15 jil)

Claims (1)

[Claims] 1. A semiconductor integrated circuit device characterized in that a silicide-forming metal or a silicide layer thereof is provided on a portion of a silicon layer other than a resistance region. 2. A semiconductor integrated circuit comprising the steps of forming a silicon layer on a semiconductor substrate via an insulating film, and forming a silicide-forming metal or its silicide layer on the silicon layer other than the portions that are to become resistance regions. A method of manufacturing a circuit device.