JPH03114267A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To connect diffused layers in mutually different conductivity type formed in a substrate in stable state by a method wherein a silicide layer connected to diffused layers is formed on the surface of openings formed in an insulating film and a polycrystalline silicon as well as on the surface of the polycrystalline silicon. CONSTITUTION:Openings in diameter of about 0.5mum are made in the upper parts of a P<+> layer 30 and an N<+> layer 20 out of a P<+> polysilicon film 6 and then a gate film 5 beneath the said openings is etched away using fluoric acid water solution to form connecting holes 7. Next, the whole surface is coated with a tungsten silicide (WSi2) film 8 1000Angstrom thick by sputtering process. At this time, in the said connecting holes 7, the WSi2 film 8 is directly ohmic connected with the P<+> layer 30 and the N<+> layer 20. Finally, a connecting wiring 9b and gate electrodes 9a are completed by processing the P<+> polysilicon layers 6 and the WSi2 film 8 in specified shape by dryetching process in high anisotropy using an etching gas mainly comprising carbon tetrachloride.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device and a method for manufacturing the same that are suitable for high integration and high performance.

(Prior Art) In order to improve the degree of integration in large-scale semiconductor integrated circuit devices, it is necessary to use a plurality of insulated gate field effect transistors (hereinafter referred to as MIS transistors or MOS transistors) that have different conductivity types. Connecting diffusion layers (source/drain regions) with each other using connection wiring,
Furthermore, a technique is required to extend the connection wiring to the gate region of the third MOS transistor to function as a gate electrode.

Conventionally, the method of connecting a diffusion layer and a connection wiring is to remove only the connection part from the oxide film deposited on the entire surface of the semiconductor substrate, and connect an electrode to the diffusion layer by a buried contact method. A method has been known in which the formed electrodes are interconnected using another wiring material.

However, with the method of connecting via electrodes, it is difficult to reduce the area of the connecting portion, and high integration and performance cannot be achieved. Therefore, in recent years, technology has been developed to directly connect the diffusion layer and the wiring.

Regarding this type of device, for example, the International Electron Device Meeting (1984), held in 1984 by the American Academy of Sciences.

Technical Digest, pages 67 to 70 (I
EDM84, Tech, Dig.

PP67-70). In Figure 5,
A sectional view of this prior art is shown.

In the figure, an N well 55 and a P well 56 are formed on the surface of an N type silicon substrate 50. On the surface of the N well 55, there is a P-type MOsFET (hereinafter simply PMOS) with the P diffusion layer 53 as a source/drain region.
51 is formed, and on the surface of the P well 56, an N type MOSFET with the N diffusion layer 54 as a source/drain region is formed.
(hereinafter simply referred to as NMO8) 52 is formed.

The source/drain regions 53, 54 are connected to each other by an electrode 60, and the source/drain regions 53, 54 and the electrode 60 are directly connected without a connection hole.

In addition, when connecting diffusion layers of different conductivity types to each other using polycrystalline silicon (polysilicon) T4 electrodes, if the polysilicon electrode is formed of only one conductivity type, the connection with either diffusion layer will occur. A PN junction is formed in the area, and that part becomes non-ohmic.

Therefore, as shown in the figure, the electrode 60 is made of P+ type polysilicon 57 in the part connected to the p+ type source/drain region 53, and made of N+ type polysilicon 57 in the part connected to the N type source/drain region 54. It has a structure in which silicon 59 is used and a silicide layer 58 is formed on its surface.

As a result, P+ polysilicon 57 and N2 polysilicon 59 are ohmically connected.

As shown in FIG. 3, in a 6MO3 type memory cell configured by combining six MOS transistors, the electrode wiring interconnecting the source/drain regions of the MOS transistors constituting the memory cell is connected to the other MOS transistors. )
It is configured to function as the gate electrode of a transistor, but even in such cases, in conventional technology, the conductivity type of the electrode wiring was changed each time the conductivity type of the connected source/drain region changed. .

On the other hand, as other prior art, Japanese Patent Application Laid-Open No. 62-257
As described in Japanese Patent No. 749, after forming a plurality of MOS transistors on a semiconductor substrate, the source/drain regions of each transistor and the surface of a gate electrode made of polysilicon are exposed, and titanium (Ti) is coated on the entire surface.
) and heat-treated in a nitrogen atmosphere.
After forming titanium nitride (T i N) and titanium silicide (TiSi2) on the exposed portion of i in a self-aligned manner and titanium nitride on the oxide film, the titanium nitride is patterned into a desired shape. Methods have been proposed for interconnecting the source/drain regions and gate electrodes on each surface.

(Problems to be Solved by the Invention) In the conventional technique shown in FIG. The impurity element in the N+ polysilicon 59 easily interdiffuses with the impurity element through the silicide layer 58 even at low temperatures, changing the conductivity type of the polysilicon in contact with the diffusion layer and forming a PN junction between the polysilicon electrode and the diffusion layer. There was no consideration given to the possibility of being exposed.

When this PN junction is formed, it becomes a non-ohmic connection and has a serious adverse effect on CMOS operation or 5MO8 type memory cell operation.Furthermore, in the above technology, diffusion is sensitive to heat treatment temperature, There is a problem in that variations tend to occur in the PN junction characteristics in the silicon electrode, resulting in deterioration and variations in device characteristics and circuit characteristics.

Additionally, if the impurity concentration within the electrode changes due to interdiffusion, the threshold voltage of the MOS transistor will fluctuate.
As a result, there has been a problem in that element characteristics and circuit characteristics deteriorate and vary.

Furthermore, in this conventional technique, the polysilicon electrodes must be formed using polysilicon of two types of conductivity, which significantly increases the number of steps, and the difference in etching speed when processing electrodes of different conductivity types may result in etch residue. There were also problems such as the tendency for this to occur.

On the other hand, in the prior art described in Japanese Patent Application Laid-open No. 62-257749, there is a wiring that connects diffusion layers of different conductivity types, and a wiring that is electrically connected to the wiring and serves as a gate electrode of another MOS transistor. Since the wiring and wiring are formed separately, there is a problem in that a large number of steps are required.

An object of the present invention is to solve the above-mentioned problems and provide a semiconductor device having a contact structure that allows diffusion layers of different conductivity types formed in a substrate to be interconnected in a stable state. It is in.

(Means for Solving the Problems) In order to solve the above problems, the present invention is characterized in that it includes the following means.

(1) An insulating film formed on the surface of a semiconductor substrate, a polycrystalline silicon formed on the surface of the insulating film, and a diffusion layer on the main surface of the semiconductor substrate are exposed. and a silicide layer formed on the inner surface of the opening and on the surface of the polycrystalline silicon and connected to the diffusion layer.

(2) In a semiconductor device formed by interconnecting diffusion layers of different conductivity types formed on the main surface of a semiconductor substrate, an insulating film formed on the surface of the semiconductor substrate and one layer formed on the surface of the insulating film a first opening formed in the insulating film and one conductivity type polycrystalline silicon such that the conductivity type polycrystalline silicon and at least the other conductivity type diffusion layer are exposed; an inner surface of the first conductivity type polycrystalline silicon; A silicide layer was formed on the surface of the one conductivity type polycrystalline silicon and connected to the exposed diffusion layer.

(3) Forming an insulating film on the main surface of the semiconductor substrate in which one conductivity type diffusion layer and the other conductivity type diffusion layer are formed at predetermined positions, and forming one conductivity type polycrystalline silicon on the surface of the insulating film. a step of exposing at least the other conductive type diffusion layer among the one and the other conductive type diffusion layers;
forming a first opening in the insulating film and polycrystalline silicon of one conductivity type; forming a silicide layer on the inner surface of the first opening and the surface of the polycrystalline silicon;
The method included a step of ohmically connecting this to the exposed diffusion layer, and a step of etching the silicide layer and polycrystalline silicon to form a predetermined wiring.

(4) Furthermore, a barrier metal is formed between the silicide layer and the upper surface of the polycrystalline silicon, as well as the sides and bottom of the first opening.

(Function) According to the configuration (1) above, since the diffusion layer and polycrystalline silicon do not come into contact with each other, a PN junction is not formed even if the conductivity types of the diffusion layer and polycrystalline silicon are different. do not have.

According to the configuration (2) described above, diffusion layers having different conductivity types can be connected using the same wiring material.

According to the configuration (3) described above, the semiconductor device having the configuration (2) described above can be easily formed.

According to the configuration (4) described above, the barrier metal formed between the diffusion layer and the silicide layer can prevent impurities in the diffusion layer from diffusing into the polycrystalline silicon through the silicide layer.

(Example) Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a partial cross-sectional view showing a CMO 8 type memo type upper Mori cell method according to a first embodiment of the present invention.

In the figure, first an N well 3 and a P well 2 are formed on the main surface of a silicon substrate l, then a field oxide film 4 for isolating the well 3 and the P well 2 is formed, and then a predetermined area is formed. A high concentration P (P) layer 30 and an N layer 20 are formed in the region by ion implantation.

Next, after forming the gate insulating film 5, a film with a thickness of 1
000 polysilicon film is deposited by CVD method,
Boron (B) ions are implanted into the polysilicon film to form a P 2 polysilicon film 6 (FIG. 2(a)).

Next, of the P polysilicon film 6, the P+ layer 30, the N
An opening of about 0.5 μm in diameter is formed in the upper part of the layer 20 by photolithography and dry etching, and further,
The gate oxide film 5 below the gate oxide film 5 is removed by etching with a hydrofluoric acid aqueous solution to form a connection hole 7 (FIG. 2(b)).

Next, a tungsten silicide (W S l 2 ) film 8 is deposited on the entire surface by sputtering to a thickness of 1000 nm. At this time, the WS i2 film 8 is directly ohmically connected to the P layer 30 and the N layer 20 at the connection hole 7 (see (C) in the same figure).
).

Next, the P polysilicon film 6 and the W Sl 2 film 8 are processed into a desired shape by highly anisotropic dry etching using an etching gas containing carbon tetrachloride (CCI4) as a main component, thereby forming the connection wiring. 9b and gate electrode 9a are completed.

Furthermore, boron is applied to N-well 3 at 20 keV.

2×1015 (to)-2 ions are implanted to form a P source/drain region 31, and the P well 2 is filled with arsenic (As).
) is ion-implanted at 50 keV and 2.times.10@15 am@-2 to form N source/drain regions 21. The main steps of the CMOS memory cell are completed by the above steps (FIG. 4(d)).

According to this embodiment, only the portion of the W S l 2 film 8 that functions as the connection wiring 9b is connected to the source/drain region 201.
Since the P polysilicon film 6 and the source/drain region 20.30 are not connected to each other, the N
At the connection portion with the source/drain region 2°, no PN junction is formed, and the connection wiring 9b and the source/drain regions of different conductivity types can be interconnected in an ohmic state.

According to this embodiment, diffusion layers having different conductivity types can be connected using the same wiring material, thereby simplifying the manufacturing process.

Figure 2 shows 5MO3 using the connection structure described above.
FIG. 3 is a plan view of the type memory cell and its equivalent circuit diagram.

In the figure, the 6MO3 type memory cell includes a first inverter, a load MOS transistor (pMOS), and a load MOS transistor (pMOS) consisting of a load MOS transistor (pMO8) Pi and a driver MOS transistor (nMOS) Nl, as is well known. P2 and driver MO3) transistor (n
a second inverter constituted by M OS ) N2, and a transfer MO8) transistor (n M
OS) Consists of T1 and T2.

One of the source/drain regions of the transistors Pi and P2 is connected to the power supply VDD, and one of the source and drain regions of the transistors Nl and N2 is connected to the power supply vss.

Further, the gate electrodes of the transistors T1 and T2 are connected to the word line WL, and one of the source and drain regions is connected to the data lines DL and DL, respectively.

As is clear from FIG. 2, according to this embodiment, the connection wiring (the hatched part in the figure) that connects diffusion layers of different conductivity types is extended to the gate region of another transistor, It can be seen that it also functions as a gate electrode.

In this way, if the same wiring material is used to connect the gate electrode and the diffusion layer with a different conductivity type, an electrode for a buried contact becomes unnecessary, and furthermore, the electrodes can be connected to each other. Since multilayer wiring for connection is not required, high integration of the semiconductor device and simplification of the manufacturing process can be easily achieved.

FIG. 4 is a cross-sectional view showing a method for manufacturing a CMOS type memory cell according to a second embodiment of the present invention, and the same reference numerals as in FIG. 1 represent the same or equivalent parts, so a detailed explanation thereof will be given. is omitted.

In this example, the manufacturing steps up to (a) and (b) in the same figure are the same as in the first example, but as shown in (C) in the same figure, after drilling the connection hole 7, titanium nitride (TiN)
) 80 to a thickness of 1,000 by sputtering, and further coated with tungsten silicide (W) on the entire surface.
S T2 ) Film 8 was sputtered to
It is unique in that it is applied to a person's thickness.

According to this embodiment, the gate electrode 9a and the connection wiring 9b
is P polysilicon/TiN80/W S l 2
Since TiN 80 functions as a diffusion barrier material for the impurity elements in the diffusion layers 20 and 30 to the P polysilicon layer, the source/drain region 2 on the St substrate side
0,30 and the P polysilicon of the gate electrode 9 via the WS l 210, the contact characteristics are further stabilized and the semiconductor integrated circuit device is improved. High reliability can be achieved.

FIG. 6 is a CMO8 type memory cell diagram of the third embodiment of the present invention, and since the same reference numerals as in FIG. 1 or 2 represent the same or equivalent parts, detailed explanation thereof will be given below. Omitted.

In this example, N has a conductivity type different from that of P polysilicon.
Only the region of the diffusion layer 20 and the gate electrode 9a
and are ohmically connected through the connection hole 7,
A feature is that in the region of the P 2 diffusion layer 30 having the same conductivity type, the diffusion layer 30 and the P 2 polysilicon are directly connected.

Generally, the contact resistance between a diffusion layer and a silicide tends to be higher than that between semiconductors, but according to this example, the conductivity type of the polysilicon layer and the diffusion layer are the same. In this case, since the diffusion layer and the P polysilicon are directly connected, the contact area between the diffusion layer and the silicide can be minimized, and a semiconductor device with even better characteristics can be provided. Become.

Note that in this embodiment as well, as in the second embodiment,
If a barrier metal is provided between the polysilicon layer 8 and the silicide 8, the contact characteristics will be further stabilized, and the reliability of the semiconductor device can be improved.

In each of the embodiments described above, the gate electrode is made of P 2 polysilicon, but the same effect can be achieved even if the gate electrode is made of N 2 polysilicon.

Similarly, in each embodiment, W S l as the silicide layer
Although the present invention has been described as using a metal with a high melting point such as molybdenum, titanium, tantalum, etc., the present invention is not limited to this.

Further, in each of the above-described embodiments, the present invention was explained by applying it to a memory cell with a CMO8 structure, but it is also possible to apply the present invention to a memory cell with a CMO8 structure.
It can also be applied to a BiCMO8 device, a bipolar device, or a BiCMO8 device that is a combination of both.

(Effects of the Invention) As is clear from the above description, according to the present invention, the following effects are achieved.

(1) Since diffusion layers having different conductivity types can be connected using the same wiring material, the manufacturing process is simplified.

(2) Since the gate electrode and the diffusion layer having a different conductivity type can be connected using the same wiring material, high integration of the semiconductor device and simplification of the manufacturing process can be easily achieved.

(3) By providing a barrier metal between the diffusion layer and the silicide layer, it is possible to prevent impurities in the diffusion layer from diffusing into the polycrystalline silicon through the silicide layer, further stabilizing the contact characteristics and making the semiconductor High reliability of the device can be achieved.

(4) As explained with reference to FIG. 6, the connection between the connection wiring and the diffusion layer is made by silicide only between the polysilicon forming the connection wiring and the diffusion layer of a different conductivity type, and the diffusion layer of the same conductivity type is By using polysilicon to connect the layers, it is possible to provide a semiconductor device with even better characteristics.

[Brief explanation of drawings]

FIG. 1 is a partial cross-sectional view showing a method for manufacturing a CMOS type memory cell according to the first embodiment of the present invention, FIG. 2 is a plan view of a 6M0S type memory cell to which the present invention is applied, and FIG.
An equivalent circuit diagram of an S-type memory cell, FIG. 4 is a cross-sectional view showing a method for manufacturing a CMOS-type memory cell according to a second embodiment of the present invention, FIG. 5 is a cross-sectional view of the conventional technology, and FIG. f of invention
FIG. 3 is a cross-sectional view of a CMOS type memory cell which is an f13 embodiment. DESCRIPTION OF SYMBOLS 1... Silicon substrate, 2-P well, 3... N well, 4... Field oxide film, 5... Gate insulating film, 6... Polysilicon film, 7... Connection hole, 8...
Silicide film, 9a...gate electrode, 9b...connection wiring, 20...N layer, 30...P layer

Claims (12)

[Claims] (1) A diffusion layer formed on the main surface of a semiconductor substrate, an insulating film formed on the surface of the semiconductor substrate, polycrystalline silicon formed on the surface of the insulating film, and the diffusion layer exposed. an opening formed by opening the insulating film and the polycrystalline silicon, the sides and bottom of the opening, and the diffusion formed on the surface of the polycrystalline silicon and exposed at the bottom of the opening; 1. A semiconductor device comprising a silicide layer connected to a silicide layer. (2) In a semiconductor device formed by interconnecting diffusion layers of different conductivity types formed on the main surface of a semiconductor substrate, an insulating film formed on the surface of the semiconductor substrate and an insulating layer formed on the surface of the insulating film are provided. one conductivity type polycrystalline silicon; a first opening formed in the insulating film and one conductivity type polycrystalline silicon such that at least the other conductivity type diffusion layer of the one conductivity type diffusion layer is exposed; , a silicide layer formed on the side and bottom of the first opening and on the surface of the one conductivity type polycrystalline silicon and connected to the exposed diffusion layer at the bottom of the first opening; A semiconductor device characterized by comprising: (3) The one conductivity type diffusion layer is a one conductivity type MISFET.
3. The semiconductor device according to claim 2, wherein the diffusion layer of the other conductive type is a source/drain region of a MISFET of the other conductive type. (4) At least one conductivity type MISFET in which one conductivity type diffusion layer serves as a source/drain region and the other conductivity type MISFET in which the other conductivity type diffusion layer serves as a source/drain region.
FET, and the connection wiring interconnecting the one conductivity type diffusion layer and the other conductivity type diffusion layer is a third MISFET.
In a semiconductor device that extends to a gate region of a semiconductor substrate and functions as a gate electrode, an insulating film formed on a surface of a semiconductor substrate, polycrystalline silicon of one conductivity type formed on a surface of the insulating film, and one conductivity type and the other conductivity type. a first opening formed in the insulating film and one conductivity type polycrystalline silicon such that at least the other conductivity type diffusion layer of the diffusion layer is exposed; a side part and a bottom part of the first opening part; and a silicide layer formed on the surface of the one conductivity type polycrystalline silicon and connected to the exposed diffusion layer at the bottom of the first opening. (5) further comprising a second opening formed in the insulating film so that the one conductivity type diffusion layer is exposed in a region where the first opening is not formed; 5. The semiconductor device according to claim 2, wherein the one conductivity type diffusion layer and the one conductivity type polycrystalline silicon are connected at the bottom of the semiconductor device. (6) A barrier metal is formed between the silicide layer and the upper surface of the polycrystalline silicon and the sides and bottom of the first opening. The semiconductor device according to any one of Item 5. (7) At least one conductivity type MISFET in which one conductivity type diffusion layer serves as a source/drain region and the other conductivity type MISFET in which the other conductivity type diffusion layer serves as a source/drain region.
FET, and the connection wiring interconnecting the one conductivity type diffusion layer and the other conductivity type diffusion layer is a third MISFET.
In the semiconductor device that extends to a gate region of the semiconductor device and functions as a gate electrode, the connection wiring is formed of polycrystalline silicon and a silicide layer formed thereon, and the connection wiring and one conductivity type diffusion layer and the other conductivity type diffusion layer A semiconductor device, wherein the connection to at least the other conductivity type diffusion layer is performed by connecting the silicide layer and the other conductivity type diffusion layer through an opening in polycrystalline silicon. (8) The semiconductor device according to any one of claims 1 to 7, wherein the silicide layer is an alloy of silicon and any one of Ti, Ta, W, and Mo. . (9) forming an insulating film on the main surface of the semiconductor substrate on which a diffusion layer is formed at a predetermined position; forming polycrystalline silicon with a high impurity concentration on the surface of the insulating film; and forming a first opening in polycrystalline silicon and exposing the diffusion layer in the first opening; and forming silicide on the sides and bottom of the first opening and on the surface of the polycrystalline silicon. A method for manufacturing a semiconductor device, comprising: forming a layer; and etching the silicide layer and polycrystalline silicon to form a predetermined wiring. (10) Forming an insulating film on the main surface of the semiconductor substrate in which one conductivity type diffusion layer and the other conductivity type diffusion layer are formed at predetermined positions, and forming one conductivity type polycrystalline silicon on the surface of the insulating film. forming a first opening in the insulating film and one conductivity type polycrystalline silicon so that at least the other conductivity type diffusion layer among the one conductivity type diffusion layer and the other conductivity type diffusion layer is exposed; forming a silicide layer on the sides and bottom of the opening of No. 1 and the surface of the polycrystalline silicon, and ohmically connecting the silicide layer to the exposed diffusion layer; etching the silicide layer and the polycrystalline silicon; 1. A method of manufacturing a semiconductor device, comprising the step of forming a planned wiring. (11) Following the step of forming an insulating film, the step further includes forming a second opening in the insulating film so that one conductivity type diffusion layer in a region where the first opening is not formed is exposed. 11. The method of manufacturing a semiconductor device according to claim 10, wherein the one conductivity type diffusion layer and the one conductivity type polycrystalline silicon are then connected at the bottom of the second opening. (12) Following the step of forming the first opening, a barrier metal is formed on the surface of the polycrystalline silicon and the inner surface of the first opening, and is diffused with the barrier metal at the bottom of the first opening. Claims 9 to 11 further include the step of making an ohmic connection between the barrier metal and the silicide layer, and then etching the barrier metal together with the silicide layer and polycrystalline silicon. A method for manufacturing a semiconductor device according to .