JPH04165613A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce generating ratio of a grain boundary particularly in a channel region of an active layer by patterning an amorphous semiconductor thin film formed on a base corresponding to an element forming region, and then solid growing the thin film. CONSTITUTION:An amorphous silicon thin film 5 formed on a substrate 1 is patterned in the shape of an active layer 6, and then annealed to be solid grown as a polycrystalline silicon thin film 8, thereby forming an active layer 6. Thus, the number of generated nuclei in the film 5 at the time of solid growing is reduced, and reaching grain size of the crystal grains after solid growing is increased. Thus, generating probability of a grain boundary particularly in a channel region 6c of the layer 6 is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for forming an active layer of polycrystalline silicon such as a thin film transistor (TF″T).

[Summary of the invention]

In a method for manufacturing a semiconductor device, the present invention involves forming an amorphous semiconductor thin film on a substrate, patterning the amorphous semiconductor thin film corresponding to an element formation region, and then converting the amorphous semiconductor thin film into a solid phase. This growth reduces the incidence of grain boundaries in the active layer, particularly in the channel region, and improves the characteristics of devices (such as TPT) formed on the active layer.

C. Prior Art Conventionally, when forming an active layer of polycrystalline silicon for a thin film transistor (hereinafter simply referred to as TPT), first, as shown in FIG. 8A, a quartz substrate or a silicon substrate (
41) After forming 5i02 pus (42) on the 5i
A polycrystalline silicon film (43) having a thickness of approximately 800 mm is formed on the O7 film (42).

Next, as shown in FIG. 8, the polycrystalline silicon film (
The polycrystalline silicon film (43) is made amorphous by ion-implanting S-bis or the like into the polycrystalline silicon film (43), thereby forming an amorphous silicon film (44).

Next, as shown in FIG. 8C, an amorphous silicon film (44) is grown in solid phase by annealing to form a polycrystalline silicon film (45) with large crystal grains. As shown in Figure 8, the polycrystalline silicon film (45) is patterned to form an island-shaped active layer (46) (see Japanese Unexamined Patent Publication No. 127118/1983).

[Problems to be Solved by the Invention] However, in the above conventional manufacturing method, the amorphous silicon film (44) is grown in a solid phase and the polycrystalline silicon film (44) is grown in a solid phase.
5), the polycrystalline silicon film (45) is patterned into an island shape to form an active layer (46). 44)
In sparse regions where nuclei are generated randomly and few nuclei occur, the final grain sizes of the crystal grains become larger than each other in the solid-phase growth described above, and in dense regions where many nuclei occur, the crystal grains The final particle sizes of the two become smaller than each other. Therefore, in the above-mentioned buttering, a region (dense region) where crystal grains having mutually smaller ultimate grain sizes exist may be patterned as the active layer (46). In this case, many grain boundaries will exist in the channel region, which is the operating region of the TPT, and the characteristics (leakage current, mobility, gate voltage swing, etc.) of the TPT formed on the active layer (46) will be significantly deteriorated. There is the inconvenience of doing so.

The present invention has been made in view of these points, and its purpose is to reduce the incidence of grain boundaries in the active layer, particularly in the channel region, and to reduce the occurrence of grain boundaries formed on the active layer. An object of the present invention is to provide a method for manufacturing a semiconductor device that can improve the characteristics of a device (TPT, etc.).

[Means to solve the problem]

The method for manufacturing a semiconductor device of the present invention includes forming an amorphous semiconductor thin film [5] on a substrate (1), and then forming an amorphous semiconductor thin film [5] on a substrate (1).
) is patterned corresponding to the element forming area, and then
An amorphous semiconductor thin film (5) is grown in a planar phase.

[Effect]

According to the manufacturing method of the present invention described above, an amorphous semiconductor thin film (5)
Since the amorphous semiconductor thin film (5) is patterned into the shape of the active layer (6) (for example, island shape) before solid phase growth, the patterned pattern during the subsequent solid phase growth is The generation of nuclei in the amorphous semiconductor thin film (5) is reduced, and the grain sizes of crystal grains become larger than each other after surface phase growth.

Therefore, the probability of occurrence of grain boundaries in the active layer (6), especially in the channel region (6C), is significantly reduced, making it possible to improve the characteristics of devices (TPT, etc.) formed on the active layer (6). .

〔Example〕

Hereinafter, the present invention will be explained in detail with reference to FIGS. 1 to 7.

FIG. 1 is a process diagram showing a method for manufacturing a semiconductor device according to this embodiment, particularly a method for forming an active layer in a thin film transistor (hereinafter simply referred to as TPT).

The steps will be explained in order below.

First, as shown in FIG. 1A, after forming a 3102 film (2) on a quartz substrate or an silicon substrate (1),
A polycrystalline silicon film (3) having a film thickness of, for example, 800 mm is deposited on the 02 film (2) using, for example, LPCVD (low pressure chemical vapor deposition).
Formed by law.

Next, as shown in Figure 1, a polycrystalline silicon film (3) is formed.
For example, implant S-bi at an energy of 40 KeV and a dose of 1.
．． By ion implantation at 5 xlO”am-2,
The polycrystalline silicon film (3) is made amorphous to form an amorphous silicon film (4).

Next, as shown in FIG. 1C, the amorphous silicon film (
4), the amorphous silicon film (4) is thinned to a thickness of about 200 by light etching to form an amorphous silicon film (5).

Next, as shown in the first diagram, an amorphous silicon thin film (5
) is removed by etching, and the amorphous silicon thin film (5) is removed from the island-shaped active layer (6) (see F# in FIG. 1), which is the device formation region, as shown in FIG. Buttering into a shape that corresponds to the shape. This shape is particularly characterized by the width β of the portion (6C) that will later become the channel region. is another source region or drain region (6S) or (6d
) or βd (for example, approximately 1 μm).

Next, as shown in Figure 1, the entire surface including the patterned amorphous silicon thin film (5) (see Figure 1) is
After forming the in2 film (Cap-3in2 film) (7), for example! For example, at a temperature of 600°C in a 112 atmosphere.
Perform annealing treatment. Through this annealing treatment, the amorphous silicon thin film (5) grows in a solid phase, resulting in a polycrystalline silicon thin film (8) whose crystal grains reach an extremely large grain size (grain size - 1 μm).

After this, as shown in FIG.
An active layer (6) is obtained.

As mentioned above, according to this example, the amorphous silicone thin film (5)
After patterning into the shape of an active layer (6), the amorphous thin film M (5) is grown solidly by annealing to form a polycrystalline thin film (8). ,; Since the old layer (6) is formed, the number of nuclei generated in the amorphous silicon thin film (5) during the solid phase growth is reduced, and the final grain size of the crystal grains after the planar phase growth is reduced. are larger than each other.

Therefore, the probability of occurrence of grain boundaries in the active layer (6), especially in the channel region (6C), is significantly reduced, and the characteristics of the TPT formed on the active layer (6) can be improved, such as leakage current. The leakage current can be reduced, the mobility can be improved, the gate voltage swing can be reduced, and even if there are manufacturing variations, the leakage current can be reliably reduced. This leads to a reduction in standby current, making it suitable for use in, for example, low power consumption type SRAMs. Furthermore, when applied to a drive element of a liquid crystal display device, it also leads to faster switching operation.

In the above example, when forming the amorphous silicon film (4), S is applied to the polycrystalline silicon film (3) formed in advance.
Although the amorphous silicon film (4) is formed by ion implantation of silicon, it is also possible to form the amorphous silicon film (4) by directly depositing it.

Next, an example in which the above active layer (6) is applied to an S RAM will be explained based on FIGS. 3 to 7.

Before explaining this, let's look at recent technical trends regarding SRAM.
In tSRAM, etc., the high resistance load stacked type SRA shown in Fig. 3 is used for reasons such as reducing the operating margin and standby current. , 1, it has become essential to transition from the CAl0S system shown in FIG. 4, particularly to the TPT laminated type stacked SRAM in which polycrystalline silicon is used as the active layer. In FIGS. 3 and 4, (B) and (B) are bit lines, and (W) is a word line.

In FIG. 4, the specific structure of the CMO3) transistor indicated by Ql and Q2, for example, is as shown in FIG.
A gate electrode (13) is formed through a gate insulating film (12) consisting of n, and using this gate electrode (13) as a mask, an N-type source region (14s
) and drain region (14d) and then remove the underlying NM.
O3) A transistor Q1 is formed, and a glue flow film (1
5) is formed and planarized, an active layer (16) made of a polycrystalline silicon thin film is formed on the reflow film (15), and P-type impurities are introduced into predetermined regions of the active layer (16). A P-channel thin film transistor Q2 having the gate electrode (13) in common is formed.

This configuration is suitable for CMO, which had the disadvantage of large cell size.
It has an excellent structure that eliminates the drawbacks of the three types of SRA R4.

In the above structure, the gate electrode (13) is formed of a low-resistance polycide layer, such as tungsten (W), in order to increase the speed.

However, the problem here is that the thin film transistor Q2
This is the side gate insulating film (17). That is, the gate electrode (
Even if the tungsten (W) silicide layer constituting 13) is directly oxidized, it is not possible to obtain a gate insulating film (17) with good film quality (for example, high breakdown voltage).

Alternatively, a method of forming the gate insulating film (17) by CVD or the like may be considered, but many pinholes and the like occur, which is not preferable in terms of characteristics.

Therefore, in this example, as shown in FIG. 6, a polycrystalline silicon layer (2
1), a tungsten (W) silicide layer (22) is formed on the polycrystalline silicon layer (21) to form a tungsten (W) polycide layer (23), and further this tungsten (W) polycide layer < 23) After forming a polycrystalline silicon layer (24) thereon, it is patterned to form a gate electrode (25). This structure requires only one step of forming the polycrystalline silicon layer (24), and may be performed using a normal LP-CVD method. At this time, the formation temperature by the LP-CVD method may be 580° C. or lower. In this case, the polycrystalline silicon layer (24) may be an amorphous silicon layer. That is, by making the surface of the gate electrode (25) a phosphor-based film, the subsequent thermal oxidation produces a good 51 film of good quality (high withstand voltage, few pinholes) and difficult to peel off.
02 film (gate insulating film (26)). In this configuration, a new polycrystalline silicon layer (24) is formed on the tungsten (W) polycide layer (23), but since the tungsten (W) polycide layer (23) is dominant for wiring, , there is no problem with speeding up.

Further, by using the active layer (6) formed by the formation method of this example as the active layer of the thin film transistor Q2, the standby current can be further reduced, and the power consumption of the SRAM can be efficiently reduced. Also, ~MOS transistor Q
The element forming region (11) may be formed of the active layer (6) according to this example.

Note that, for activation annealing of the impurity diffusion region, lamp annealing, laser (eximer laser) annealing, etc. are used, for example. Further, the above gate structure can be applied to, for example, an EPROM.
It can also be applied as a gate for EEPROM, EEPROM, etc.

Next, a case where only a polycrystalline silicon layer is used as a gate electrode will be explained with reference to FIG.

The key point in this case is that the underlying ~M[]S transistor Q
.

Before forming the transistor, the gate insulating film on the side of the thin film transistor Q2 of the P transistor is formed.

That is, as shown in FIG. 7A, after forming a gate insulating film (12) made of a SiO2 film on the element formation region (11), a polycrystalline silicon layer (12) is formed on the gate insulating film (12).
31).

Thereafter, as shown in FIG. 7, thermal oxidation is performed to form a thermal oxide film (Si02 film) on the surface of the polycrystalline silicon layer (31).
(32) is formed. In this case, the thermal oxide film (32
) has a thickness of approximately 100 mm, and the temperature of thermal oxidation is:
Since a source region and a drain region are not formed in the element formation region (11), a high temperature, for example ~1000° C., can be used.

Next, as shown in FIG. 7C, the thermal oxide film (32), the polycrystalline silicon layer 31), and the gate insulating film (12) are selectively etched away, and the gate formed by the polycrystalline silicon layer (31) is removed. Form an electrode (33).

Next, as shown in the seventh diagram, after forming a photoresist 1-(34) on the thermal oxide film (32), using the photoresist 1-(34) as a mask, the element formation area (11) is
N-type impurity ions are implanted into the element forming region (11
) in the source region (14S) and drain region (14d)
form.

Next, as shown in FIG. 7F, the above photoresist)
After peeling off (34), a glue flow film (15) such as PSG is formed on the entire surface. After that, reflow is performed to flatten the surface. Thereafter, the thermal oxide film (32) is exposed by etchback using wet etching. During this etchback, the thermal oxide film (32) is dense and selective with respect to the reflow film (15) such as PSG, so it is not etched together with the reflow film (15).

Thereafter, as shown in FIG. 7F, an active layer (6) made of a polycrystalline silicon thin film according to this example is formed on the exposed thermal oxide film, that is, the gate insulating film (32), and the active layer (6) A P-type impurity is introduced into a predetermined region of the CMO8) transistor of the SRAM according to this example.

According to this embodiment, the gate insulating film (32) on the P-channel thin film transistor Q2 side is covered with a polycrystalline silicon layer (
31) can be obtained by high temperature thermal oxidation of the surface,
It is possible to obtain film quality with high voltage resistance and few pinholes, and S
It is possible to improve the yield and reliability of RAM.

Note that this formation method is applicable to the SRAM CM shown in FIG. 6 above.
O5) It can also be applied to transistors, and a higher performance SRAM can be obtained.

Furthermore, in the method for forming a cusos transistor in an S RAM shown in FIG. 7, the element forming region (11) may be formed of the active layer [6] according to this example.

[Tj1 Ri of the Invention] According to the method for manufacturing a semiconductor device according to the present invention, the occurrence rate of grain boundaries in the active layer, particularly in the channel region, can be reduced, and devices formed on the active layer (such as T P T etc.) can be reduced. ) characteristics can be improved.

[Brief explanation of drawings]

FIG. 1 is a process diagram showing a method for manufacturing a semiconductor device according to this embodiment, FIG. 2 is a plan view showing an example of the shape of an active layer according to this embodiment, and FIG. 3 is a high resistance load stacked type SRA! (Fig. 4 is a circuit diagram showing 1DS system S RA!, + is not shown. Fig. 3 is a configuration diagram showing a normal ', 1JDSh transistor in SR^1,1 of CM OS system.
Fig. 6 is a configuration diagram showing the CMO3 transistor of this example in SRA',l of the CMOS system, Fig. 7 is a process diagram showing other examples, and Fig. 8 shows a manufacturing method of a semiconductor device according to a conventional example. It is a process diagram. (1) is a quartz substrate or silicone substrate, (2) is 5102
(3) is a polycrystalline silicon film, (4) is an amorphous silicon film, (5) is an amorphous silicon thin film, and (6) is an active layer. Agent: Hide Matsukuma, Morisan μ Ikugan no Wa 4 Chido Tsumesu plan view Figure 2 1 Ishisara ￥ 4 Tomome 1] Kakon omission 4 Sword book history and examples 5 1st line I diagram / r77 Kamikura Soko & S evening drinking /) CMO 5) Laregi mata ni ni 1 δ 18 Fig. 5 21 Lid 4 f 3 I r〉 Sokorel
25 Ryohizuishi 22 Tank Matamaten (W Shisobui b
Figure 7

Claims (1)

[Claims] The method comprises the steps of forming an amorphous semiconductor thin film on a substrate, patterning the amorphous semiconductor thin film in correspondence with an element formation region, and growing the amorphous semiconductor thin film in a solid phase. Manufacturing method for semiconductor devices.