JP3522440B2 - Thin film semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film integrated circuit using a non-single crystal semiconductor formed on an insulating surface and a circuit element used for the thin film integrated circuit, for example, a thin film transistor (TFT) structure. In the present invention, the insulating surface means an insulating layer provided on the surface of a semiconductor or a metal, in addition to the surface of an insulator. That is, the integrated circuit and the thin film transistor manufactured by the present invention are not only those formed on an insulating substrate such as glass, but also those formed on an insulator formed on a semiconductor substrate such as single crystal silicon. Also includes.

[0002]

2. Description of the Related Art In a thin film semiconductor device such as a TFT, a substantially intrinsic thin film semiconductor region (active layer) is formed like an island on an insulating surface and then used as a gate insulating film by an insulating film by a CVD method or a sputtering method. Is formed and a gate electrode is formed on it. Conversely, the gate electrode is formed first,
A gate insulating film and an active layer may be formed on it.
In the former case, the source / drain regions are
It is formed by diffusing (doping) N-type or P-type impurities in an intrinsic thin film semiconductor. In the latter method, an impurity diffusion method may be used, but a method of separately forming an N-type or P-type semiconductor film is generally used.

A conventional TFT has an N-type or P-type source region / drain region, a channel region of substantially intrinsic conductivity type, and a gate insulating film and a gate electrode above or below the channel region. In the region and drain region,
In order to establish an electrical connection with the outside, wirings / electrodes (referred to as source electrode / wiring and drain electrode / wiring, respectively) are connected, and these are controlled by three terminals of the gate electrode. In particular, since the distinction between the source region and the drain region is not clear depending on the circuit, in the following description, the source region and the drain region are not distinguished based on the circuit, but can be set arbitrarily. That is,
An N-type or P-type region to which a terminal is connected, which is not a region arbitrarily set as a source region, is defined as a drain region. In recent years, since it is necessary to increase the electric field mobility of TFT,
As a semiconductor of the active layer, instead of an amorphous semiconductor,
Attempts have been made to use crystalline semiconductors.

[0004]

The biggest problem with a TFT using such a non-single-crystal semiconductor, especially a crystalline non-single-crystal semiconductor (for example, polycrystalline silicon), is a large leak current (OFF current). Was that. That is, when no voltage is applied to the gate electrode or when a reverse voltage is applied (non-selected state, OFF state)
Since no channel (current path) is formed in, no current should flow. However, in reality, a current higher than the leakage current normally observed in a single crystal semiconductor was observed. Therefore, this phenomenon is considered to be peculiar to non-single crystal semiconductors.

Such a large leak current has been a problem particularly in applications requiring dynamic operation (charge retention, etc.). Further, it is not preferable because it increases power consumption even in applications requiring static operation. In an active matrix circuit such as a liquid crystal display, which is expected to have a large use as a TFT, the TFT operates as a switching transistor of a pixel provided in the matrix. At that time, the pixel electrode and its auxiliary capacitor (holding capacity) ) Was required to not leak the charge accumulated in
If the leak current was large, the electric charge could not be retained for a sufficient time.

Conventionally, it has been considered effective to increase the channel length or the channel width to reduce the leak current. However, in this way, although the absolute value of the leak current becomes small, the drain current (ON current) when a voltage is applied to the gate electrode (selected state, ON state) also becomes small, and the required operation is performed. There were cases where it could not be done. That is, in this method, the ratio of the drain current to the leakage current (ON / OF
The F ratio) could not be improved. The present invention has been made in view of such a problem, and provides a method of reducing a leak current and improving an ON / OFF ratio in a TFT using a non-single crystal semiconductor in an active layer. To aim.

[0007]

The present invention relates to a thin film semiconductor having a thin film semiconductor, a gate insulating film and a gate electrode. In the present invention, a base region and a floating island region which are not provided in the conventional TFT are provided. Conceptually, the base region is close to the conventional channel region, but it is not an exact match, so it will be referred to as an alias in the description of the present invention. Further, in the present invention described below, the definition of the base region is slightly different. However, in the thin film semiconductor device which is the basis of the present invention, the thin film semiconductor is formed separately and has a source region and a drain region.
Further, a gate electrode is provided above or below the base region via a gate insulating film.

In addition to this gate electrode, another gate electrode (overlap gate electrode) is provided above or below at least one floating island region. The overlap gate electrode is formed in a layer different from that of the gate electrode, and is usually formed in a layer above the gate electrode. A signal is not applied unlike the gate electrode, and it is always held at a constant voltage regardless of selection / non-selection. Further, the source region, the drain region, and the base region are all formed by diffusing impurities using the gate electrode as a mask. However, the diffusion of the impurities may be performed simultaneously in all of these regions, or may be performed separately.

In the present invention, the insulation between the gate electrode 9 and the overlap gate electrode 17 may be a problem. In this regard, in addition to a method of depositing an insulator by a known vapor phase growth method, a method of forming an insulator film on the surface of the gate electrode 9 using a selective oxidation / combining reaction such as an anodic oxidation method. Is also effective. In the present invention, the materials for the gate electrode and the overlap gate electrode are not particularly limited. Therefore, various metals used for ordinary transistors, such as aluminum, tantalum, titanium,
It is formed of a material such as molybdenum, tungsten, silicon whose resistance is lowered by doping, or an alloy (silicide) of the metal and silicon. Further, the gate electrode and the overlap gate electrode may have a structure (multilayer structure) in which two or more layers of different materials are stacked.

In the present invention, various known materials can be used as the thin film semiconductor. For example, a silicon-based semiconductor such as single crystal silicon, polycrystalline silicon, or amorphous silicon, a compound semiconductor such as gallium arsenide, gallium / antimony, or a germanium semiconductor can be used. Also,
These semiconductor materials may contain other impurities as needed. The first aspect of the present invention is as follows (1) and (2)
Satisfy the condition of. (1) A thin film semiconductor exists between a source region and a drain region and has a base region having the same conductivity type as the intrinsic or source / drain region and a source / drain region having the same conductivity type as the source / drain region. The region has a floating island region separated by the base region. (2) The shortest distance from the source region to the drain region via only the base region is larger than the shortest distance from the source region to the drain region via the base region and the floating island region.

The second aspect of the present invention satisfies the following condition (3). (3) A thin film semiconductor has a base region connected from a source region to a drain region and having a conductivity type opposite to that of the intrinsic or source / drain region, and a source / drain region having the same conductivity type as the source / drain region. A floating island region separated from the region. Third of the present invention
Satisfies the following condition (4). (4) The thin film semiconductor has a unique base region having a conductivity type opposite to that of the intrinsic or source / drain region and a floating island which has the same conductivity type as the source / drain region and is separated from the source region and the drain region by the base region. And a region.

The fourth aspect of the present invention is to provide the following (5) and (6).
Satisfy the condition of. (5) The thin film semiconductor has the same conductivity type as the source / drain region, and the source region, the drain region, the base region connected to the drain region from the source region and having a conductivity type opposite to that of the intrinsic / source / drain region, The source region and the drain region are composed of only floating island regions separated by the base region. (6) A value obtained by dividing the area of the base region by the shortest path length from the source region to the drain region via only the base region leads to the area other than the source region and the drain region of the thin film semiconductor from the source region to the drain region. It is smaller than the value divided by the shortest path length.

Regarding the second aspect of the present invention, the following condition may be added. (7) The average width of the route from the source region to the drain region through the base region is smaller than the average width of the route from the source region to the drain region through the thin film semiconductor. This regulation is a regulation on the width of the current (leakage current in this case) as in the above (6). However, in the second aspect of the present invention, since the thin film semiconductor may have an undefined region other than the source region, the drain region, the base region, and the floating island region, the definition of (6) is added. Difficult to do. Since the present invention may be combined with the known low-concentration impurity region (LDD) technique, the following conditions may be added to the first to fourth aspects of the present invention. (8) At the boundary between the floating island region and the base region, a region intentionally provided with an impurity of the first conductivity type whose concentration is lower than that of the floating island region is provided.

The offset gate structure is not limited to the low concentration impurity region. FIG. 4 shows some examples. Each of the transistors shown in FIG. 4 is formed on an insulating substrate 100, and has a source region 101, a drain region 102, a base region 107, a gate insulating film 119, and a gate electrode 10.
9, having floating island regions 103 and 104. In the example of FIG. 4A, an offset gate structure is obtained by using a sidewall forming technique. That is, by the known side wall forming technology,
An insulator side wall 121 is formed on the side surface of the gate electrode 109 (these are all the same material). Then, using the gate electrode and the side wall (collectively referred to as a gate electrode portion) as a mask, impurities are diffused into the thin film semiconductor, and the source region 1
01, drain region 102, floating island regions 103 and 10
Get 4.

At this time, since the impurities are not injected into the lower part of the side wall 121 or the injection amount is extremely low, an offset region 122 where the gate electrode and the impurity region do not overlap is formed. By providing such an offset area,
Although the leak current can be reduced, the reduction of the leak current can be further promoted by combining with the present invention. (Fig. 4
(A)) FIG. 4B shows an example in which a well-known sidewall formation technique and a low-concentration impurity region formation technique are applied. That is, the gate electrode 1
09 (these are all the same material) as a mask,
A low-concentration impurity (concentration is preferably 1/100 to 1/10000 of that of the source / drain region) is diffused into the thin film semiconductor (first doping) to obtain a low-concentration impurity region 123. After that, by a known side wall forming technique,
A side wall 121 is formed on the side surface of the gate electrode 109. This side wall may be conductive or insulating.

Then, using the gate electrode and the side wall (collectively referred to as a gate electrode portion) as a mask, impurities are diffused into the thin film semiconductor (second doping), and the source region 1 is formed.
01, drain region 102, floating island regions 103 and 10
Get 4. During the second doping, the impurities do not diffuse to the lower portion of the sidewall 121, so that the low-concentration impurity region 123 obtained by the first doping is retained.
By providing such a low-concentration impurity region, it is possible to prevent deterioration due to the shortening of the channel of the device. (Fig. 4
(B))

FIG. 4C shows an example in which an offset gate structure is obtained by using the anodic oxidation technique of the gate electrode as described in JP-A-6-291315. That is, by forming the anodic oxide film 124 on the side surface and the upper surface of the gate electrode 109 and using them as a mask, the offset region 122 similar to that in FIG. 4A can be provided in the thin film semiconductor. (Fig. 4 (C))

FIG. 4D also uses the anodic oxidation technique. That is, as described in Japanese Patent Application Laid-Open No. 7-169974, the gate insulating film is selectively etched by using the side surface anodic oxidation technique, and this is used to form a source region 101 and a drain region 102 in a thin film semiconductor. The floating island regions 103 and 104 and the low-concentration impurity region 123 are provided between the surroundings and the base region. In this case, the gate electrode 109 is anodized in two steps, and the obtained anodic oxide film is used as a mask to form the gate insulating film 11
9 is etched to form a new gate insulating film 125. After that, a part of the anodic oxide film 124 is left, but the other anodic oxide is removed, and two-step doping is performed using the gate insulating film 125 thus obtained as a mask to form the low concentration impurity region 123. obtain. (Fig. 4 (D))

[0019]

In the first to fourth aspects of the present invention, the conventional T
The base region and the floating island region are provided in the portion corresponding to the channel region of the FT. Considering the non-selected (OFF) state, it is unlikely that the leak current flows from the source region to the drain region across the floating island region existing therebetween. This is because a large potential barrier is formed between the base region and the floating island region. Therefore, the leak current mainly flows in the base region.

However, since the base region has a floating island region, its width (average width) is narrower than that of the conventional channel region, and the path from the source region to the drain region is long. Could be. Therefore, due to the presence of the floating island region, the substantial channel length in the non-selected state can be longer and the channel width can be shorter. Therefore, the leak current is reduced. Next, considering the selected (ON) state, the base region is inverted because a voltage is applied to the gate electrode, the potential barrier between the base region and the floating island region becomes small, and the (drain) current is not generated only in the base region. Instead, it will flow across the floating island region. This is because the distance is shorter when crossing the floating island region. That is, in the selected state, the substantial channel length is shorter and the channel width is larger than in the non-selected state. For this reason,
The drain current increases.

In this way, the ON / OFF ratio can be increased. In order to further increase the substantial channel length in the non-selected state, the number of floating island regions should be 2 or more, preferably 5 or more, as will be apparent from the following examples. Similarly, in order to make the substantial channel width narrower, the spacing between the floating island regions should be made as narrow as possible. FIG. 1 is a diagram for explaining the basic concept of the present invention. In the thin film semiconductor 8, the source region 1, the drain region 2,
Floating island regions 3 to 6 and base region 7 are formed. Further, a gate electrode 9 is provided on the thin film semiconductor 8 via a gate insulating film (not shown). The source / drain region and the floating island region are formed in a self-aligned manner using the gate electrode 9 as a mask. The conductivity type of the base region 107 remains the same as the original conductivity type of the thin film semiconductor 8, and is the conductivity type opposite to the intrinsic or source / drain regions and floating island regions.

A method for obtaining such a structure will be described with reference to FIGS. 1 (B) and 1 (C). First, the gate electrode 9 is formed on the undoped thin-film semiconductor 8 via the gate insulating film. At that time, the holes 13 to 16 are formed in the portions forming the floating island regions.
(FIG. 1B) After that, impurity doping is performed to form a necessary conductivity type region in the thin film semiconductor region. In this way, the source region 1, the drain region 2, and the floating island regions 3 to 6 are formed. However, even in the thin film semiconductor region, the portion below the gate electrode 9 is not intentionally doped,
Remaining authentic, this becomes the base region 7. (Fig. 1
(C))

In the source region 1, the source wiring / electrode 10
In addition, the drain wiring / electrode 12 is provided in the drain region 2.
To form. The gate electrode 9 is directly connected to the gate wiring 11
1 is electrically connected. A drawing of the thin film semiconductor 8 of such a semiconductor device viewed from above is shown in FIG. The device having such a structure satisfies the above first to fourth conditions. For example, regarding the first of the above conditions, the thin film semiconductor 8 includes a source region 1 and a drain region 2, a base region 7 existing therebetween, and a floating island in which the source region 1 and the drain region 2 are separated by the base region 7. Area 3-
Since it has 6, the condition (1) is satisfied.

Furthermore, the shortest distance from the source region 1 to the drain region 2 via only the base region 7 is the base region 7 and the floating island regions 3 to 6 (that is, except the source region 1 and the drain region 2 of the thin film semiconductor 8). Condition (2) is satisfied because the distance is about 2.07 times the shortest distance from the source region to the drain region via (all of the above). Similarly, regarding the second condition, the thin film semiconductor 8 is connected to the drain region 2 from the source region 1 and the intrinsic base region 7 is connected.
And the floating island region 3 separated from the source region 1 and the drain region 2 by the base region 7, the condition (3) is satisfied.

The average width of the path from the source region to the drain region in the base region is about 1 / W of the average width (here, W) from the source region to the drain region in the thin film semiconductor.
Since it is 6, the above condition (7) is also satisfied. Similarly, regarding the third condition, the thin film semiconductor 8 is
And has floating island regions 3 to 6 which have the same conductivity type as the source / drain regions and are separated from the source region 1 and the drain region 2 by the base region 7.
The condition (4) is satisfied.

Similarly, regarding the fourth of the above conditions, the thin film semiconductor 8 includes a source region 1, a drain region 2, an intrinsic base region 7 connected from the source region to the drain region,
The condition (5) is satisfied because the source / drain regions have the same conductivity type as the source / drain regions and only the floating island regions 3 to 6 are separated by the base region. Further, the value obtained by dividing the area of the base region 7 by the shortest path length from the source region to the drain region via only the base region is the area of the thin film semiconductor 8 other than the source region and the drain region from the source region to the drain region. Since it is about 1/3 of the value divided by the shortest path length to reach, the condition (6) is satisfied.

The flow of current when the semiconductor device of FIG. 1 is operated is shown in FIGS. 2 (B) and 2 (C). Figure 2
(B) shows a non-selected (OFF) state, and the flowing current is a leak current. A vertical band diagram of the base region in this case is shown in FIG. Here, the semiconductor device is an N-channel type. Since a negative voltage is applied to the gate electrode 9, holes are induced near the surface of the semiconductor layer, which plays a role in conduction. (FIG. 10 (A)) As a result, as shown by the arrow in FIG. 2 (B), the leak current zigzags the base region from the source region to the drain region so as to pass between the floating island regions in the non-selected state. Flows to. In this case, the apparent channel size is the length L and the width W, but the substantial channel size based on the actual leakage current flow is longer than the apparent channel length and narrower than the channel width. (Fig. 2 (B))

On the other hand, in the selected (ON) state, the base region is inverted by the voltage applied to the gate electrode, that is, the base region has the same conductivity type as the floating island region. A vertical band diagram of the base region in this case is shown in FIG. Here, the semiconductor device is an N-channel type. Since a negative voltage is applied to the gate electrode 9, electrons are induced near the surface of the semiconductor layer, which plays a role in conduction. (FIG. 10B) A drain current having electrons as carriers flows across the floating island. Therefore, in the selected state, the substantial channel size is substantially the same as the apparent channel size. (Fig. 2 (C))

For example, to realize the same non-selected state as the semiconductor device of FIG. 1, even if the same design rule is used,
The structure in which the floating island regions 3 to 6 are removed from FIG. 2A may be manufactured. That is, the channels are arranged in a zigzag manner, and the channel length becomes extremely long (see FIG. 2).
(D)). However, such a TFT cannot flow a large drain current in the selected state as in the semiconductor device of this embodiment. This is the conventional TF
This is because the substantial channel is the same as the geometrical channel when T is in the selected state or the non-selected state. On the other hand, the basic concept of the present invention is characterized in that the substantial channel changes greatly in the selected state and the non-selected state, and therefore the ON state
The / OFF ratio can be increased.

The above is also the same as the equivalent circuit of the semiconductor device being different between the selected state and the non-selected state. In FIG. 11A, a solid arrow indicates a drain current in a selected state, and a dotted arrow indicates a leak current in a non-selected state. In the case of the N-channel type, in the selected state, a positive voltage + V is applied to the gate electrode, and at this time, since the drain current with electrons as carriers flows across the floating island region, A cross-sectional view of the semiconductor device is as shown in FIG. 11B, and an equivalent circuit thereof is a multigate type as shown in FIG. 11C.

On the other hand, in the non-selected state, a negative voltage -V is applied to the gate electrode, and at this time, a leak current having holes as carriers flows along the base region. 1 is a sectional view of the semiconductor device.
It becomes long like 1 (D). The equivalent circuit is an insulating gate type element having a large channel width as shown in FIG. If the design rule is optimized with the values of L and W in FIG. 2 unchanged, the semiconductor device turns on.
The ON / O ratio is 15 times that of the TFT in Figure 2 (D).
The FF ratio can be obtained.

To further improve the ON / OFF ratio, W
/ L should be increased. Thus, in the non-selected state, the substantial channel length increases, while in the selected state, the channel width increases, so that the leak current decreases and the drain current increases. By doing so, the substantial channel length in the non-selected state is 5 to 50 times that in the selected state, and the substantial channel width in the non-selected state is 1/2 to 1/1 of that in the selected state.
It is possible to increase by 20 times, and as a result, ON / OF
The F ratio can be expanded up to 100 times.

FIG. 3 shows a case in which the overlap gate electrode 17 is provided in the apparatus of FIG. In FIG. 3, the other structure is basically the same as that of FIG.
In order to simplify the drawing, the number of floating island regions is set to one, and the shape of the gate electrode 9 is simplified accordingly. The numbers indicate the same as those in FIG. The overlap gate electrode 17 is provided with a wiring 18 for supplying a voltage. FIG. 3A shows a layer structure of the semiconductor device of the present invention. Also,
FIG. 3B shows a schematic cross section of the device of the present invention. The overlap gate electrode 17 is insulated from the gate electrode 9 and the floating island region 3. The structure of the semiconductor device of FIG. 3 is obtained by adding an overlap gate electrode to the semiconductor device of FIG.
All of (7) are satisfied, and therefore the first to fourth conditions of the present invention are satisfied.

When a reverse bias (negative for N-channel type) voltage is applied to the gate electrode 9, carriers (holes for N-channel type) corresponding thereto are generated on the surface of the base region 7. Induced. However, the overlap gate electrode is forward biased (if it is an N-channel type,
When a positive voltage is applied, the corresponding carriers (electrons in the case of N-channel type) are attracted from the base region 7 toward the floating island region 3, and the depletion layer 20 is formed. Since the depletion layer has a very high resistance, it does not contribute to conduction. That is, by providing an overlap gate electrode and applying a forward bias voltage to it, the width of the base region can be substantially narrowed, and the resistance between the source / drain regions in the non-selected state can be further increased. be able to. That is, the leak current is reduced.

On the other hand, in the selected state, since the forward bias voltage is applied to both the gate electrode and the overlap gate electrode, the depletion layer is not formed, but rather the channel is induced on the surface of the base region. This state is the same as the case of FIG. That is, by adding an overlap gate electrode and applying a constant forward bias voltage thereto, the drain current of the semiconductor device of FIG. 1 remains unchanged, and only the leak current is reduced. The present invention is particularly effective when an offset region or a low concentration impurity region is provided around the floating island region. The conductivity type of these offset regions and low-concentration impurity regions varies depending on the voltage of the gate electrode, but if these regions are not sufficiently inverted, resistance will be generated between the base region and the floating island region. As described above, it becomes difficult to flow the drain current across the base region and the floating island region.

In particular, since there is no gate electrode above or below the offset region and the low concentration impurity region formed in self-alignment, it is difficult to invert this portion. Of course, when a higher current is applied to the gate electrode, the offset region is also sufficiently inverted. However,
Applying an excessive voltage to the gate electrode may damage the device. Further, repeated application of high voltage reduces the reliability of the device. In the present invention, by applying a positive voltage to the overlap gate electrode provided so as to cover the offset region and the low concentration impurity region, it is possible to promote the inversion of the offset region and the low concentration impurity region.

[0037]

【Example】

Example 1 This example will be described with reference to FIGS. 5 and 6. In this embodiment, a circuit including not only the transistor of the present invention but also other transistors and wirings will be described. The main manufacturing steps of the circuit are as follows. Formation of semiconductor active layer (thin film semiconductor), gate insulating film, gate electrode / wiring, and gate electrode section Doping and activation of doping impurities Interlayer insulator film formation Source / drain contact holes and gate wiring contact holes Formation of holes for overlap gate electrodes Formation of wiring (including overlap gate electrodes) using conductive material (metal etc.) in the upper layer

In this embodiment, as described in JP-A-6-291315, the surface of the metal gate electrode / wiring is anodized to form a gate electrode portion. First, the steps will be described with reference to FIG. Thin film semiconductors,
The gate insulating film, the gate electrode / wiring, and the gate electrode portion are formed by using a known technique or the technique described in JP-A-6-291315. In this embodiment, a TFT to which the present invention is mainly applied is a thin film semiconductor 50.
8 is formed on the thin film semiconductor 551. The former is used in applications where a high ON / OFF ratio is required. In the example of the active matrix type liquid crystal display, it is a switching transistor of a pixel or a buffer transistor (transfer transistor) that outputs a signal to a matrix. The latter is used for other logic circuits and the like. Thin film semiconductors 508 and 5
51 is formed on a substrate 500 having an insulating surface.

As the thin film semiconductor material, single crystal silicon, polycrystalline silicon, amorphous silicon or the like is used.
As the single crystal silicon, a single crystal silicon layer epitaxially grown on a sapphire substrate or a high concentration oxygen ion is implanted into the central portion of the single crystal silicon wafer and the portion is oxidized to leave a single crystal silicon layer only on the surface. Those obtained by the method for obtaining the structure (SIMOX method) or those grown by various lateral epitaxy methods may be used. Further, if polycrystalline silicon is used, those obtained by vapor phase growth by various known film forming techniques, or polycrystalline silicon or amorphous silicon thus obtained by laser annealing, lamp annealing, A material having a higher degree of crystallinity by performing a thermal annealing method or the like may be used.

A gate insulating film 519, gate electrodes 509 and 552, and a gate wiring 553 are formed so as to cover such a thin film semiconductor. As the gate insulating film, a silicon oxide film obtained by a manufacturing method used in a usual semiconductor technique is preferable. Gate electrode / wiring 509, 5
The surfaces of 52 and 553 are covered with anodic oxide. Therefore, the material of the gate electrode needs to be capable of forming an anodic oxide film on its surface. For example, a metal material containing aluminum, tantalum or the like as a main component is preferable. (Figure 5 (A))

Next, the steps will be described with reference to FIG. This step is performed using a known impurity doping method. As a result, N type source regions 501 and 554, drain regions 502 and 555, and floating island regions 503 to 505 are formed in a self-aligned manner. Further, the impurities introduced into the thin film semiconductor by doping are activated by a known method. For example, methods such as thermal annealing, laser annealing, and lamp annealing are adopted. (Fig. 5
(B)) FIG. 6A shows a state in which the impurity region of the thin film semiconductor 508 obtained by this doping is viewed from above. That is, the sectional view taken along line XX ′ of FIG.
(Fig. 6 (A))

Next, the steps will be described with reference to FIG. This step is performed using a known interlayer insulating film forming technique, and as a result, an interlayer insulating film 556 is formed. The material for the interlayer insulator is selected from materials used in ordinary semiconductor technology. For example, silicon oxide and silicon nitride are preferable. (FIG. 5C) Next, the process will be described with reference to FIG. This step is performed using a known contact hole forming technique, and as a result, source regions 501 and 554, drain regions 502 and 555, and contact holes 557 to 561 to the gate wiring 553 are formed.

In forming the contact hole, for example, in the contact hole 559 to the gate wiring, the interlayer insulator 556 and the anodic oxide film must be etched, whereas in the other contact holes, the interlayer insulator 556 is formed. The gate insulating film 519 must be etched. Therefore, the contact hole etching process may be performed separately. (Fig. 5
(D)) Next, the process will be described with reference to FIG. This step is also performed using a known contact hole forming technique. As a result, the opening 562 that forms the overlap gate electrode is formed. In this etching process,
Only the interlayer insulator is etched. When silicon oxide is used as the interlayer insulator and aluminum is used as the material of the gate electrode, anodic oxide (aluminum oxide) is significantly less likely to be etched (higher selection ratio) than silicon oxide. Easily achieved. Note that it is necessary to avoid etching the gate insulating film 519 in this etching process. (Fig. 5
(E))

Next, the steps will be described with reference to FIG. This step is performed by using a known metal film forming technique and etching technique. As a result, the metal wiring 510,
512, 563, 564 and overlap gate electrode 517 are formed. Thus, in this embodiment,
The overlap gate electrode is formed of the same film as the source / drain electrode / wiring. (FIG. 5F) The operation state of the transistor thus obtained will be described with reference to FIG. The numbers in FIG. 6 correspond to those in FIG. Source 501 and overlap gate electrode 51
When a large negative voltage is applied to the gate electrode 509 in a state where 7 is grounded and a positive voltage is applied to the drain 502,
As shown in FIG. 6B, the leakage current is the base region 507.
It flows through. (Fig. 6 (B))

Next, the overlap gate electrode 517
When a positive voltage is applied to, the depletion layer 520 is formed around the floating island regions 503 to 505. Since the depletion layer 520 does not contribute to the conduction of the leakage current, the width of the leakage current conduction path is narrowed and the leakage current is reduced. (FIG. 6 (C)) Further, when a large positive voltage is applied to the overlap gate electrode 517, the depletion layers 520 around the floating island regions 503 to 505 expand and are coupled to each other as shown in the figure, resulting in Basically, the base region 507 has three regions 507a.
It is divided into ~ c. In such a state, the leak current can no longer flow, so that the leak current is significantly reduced. (FIG. 6 (D)) The above is nothing but the TF described in JP-A-6-291315.
This is not applicable only to T, and as shown in FIG. 4D, a TFT in which an offset region and a low-concentration impurity region are formed by using the side surface anodic oxidation technique described in JP-A-7-169974. However, it will be clear that the same can be done.

[Embodiment 2] This embodiment will be described with reference to FIG. In the present embodiment as well, as in the case of the first embodiment, the fabrication of a circuit including not only the transistor of the present invention but also other transistors and wirings will be described. The main manufacturing steps of the circuit of this embodiment are as follows. Formation of semiconductor active layer (thin film semiconductor), gate insulating film, gate electrode / wiring, and gate electrode section Doping and activation of doped impurities Deposition of interlayer insulating film Contact hole to source / drain region and overlap gate Formation of holes for electrodes Formation of contact holes for gate wiring Formation of wiring (including overlapping gate electrodes) using conductive material (metal etc.) in the upper layer

In this embodiment, as described in Japanese Patent Laid-Open No. 6-291315, the surface of the metal gate electrode / wiring is anodized to form the gate electrode portion. However, nothing is disclosed in the TFT disclosed in JP-A-6-291315.
However, it is not applicable only to Japanese Patent Laid-Open No. 7-16
By using the side surface anodic oxidation technique described in Japanese Patent Publication 9974, the same can be carried out in a TFT in which an offset region and a low concentration impurity region are formed. First, the process is shown in FIG.
Will be explained. The present invention is mainly applied to T
FT to thin film semiconductor 708 and TF not
T is formed on the thin film semiconductor 751. The thin film semiconductors 708 and 751 are formed on the SIMOX substrate 700.
A SIMOX substrate is a silicon oxide layer 766 formed near the surface of a substrate by implanting oxygen ions only at a specific depth near the substrate of the single crystal silicon wafer, and the single crystal silicon layer is left on the silicon oxide layer 766. It is a thing. Therefore, the single crystal silicon layer over the silicon oxide layer 766 may be etched to form the thin film semiconductors 708 and 751.

The gate insulating film 719 and the gate electrodes 709 and 75 are covered with the thin film semiconductor thus obtained.
2. Gate wiring 753 is formed. In this embodiment, silicon oxide formed by the plasma CVD method is used as the gate insulating film, and aluminum (0.1 to 3) is used as the gate electrode.
% Scandium). The surfaces of the gate electrodes / wirings 709, 752, and 753 are covered with anodic oxide. (FIG. 7 (A)) Next, a process is demonstrated using FIG. 7 (B). This step is performed using a known impurity doping method. As a result, the N type source regions 701 and 754 and the drain region 7 are formed.
02, 755 and floating island regions 703 to 705 are formed in a self-aligned manner. Further, the impurities introduced into the thin film semiconductor by doping are activated by a known method. In this embodiment, laser annealing using an excimer laser is adopted. (Fig. 7 (B))

Next, steps and steps will be described with reference to FIG. This step is performed by using a known interlayer insulating film forming technique and contact hole forming technique. In this embodiment, silicon oxide is used as the interlayer insulator. further,
Source regions 701, 754 and drain regions 702,
755, contact hole 757 to gate wiring 753
~ 761 are formed. At the same time, overlap
An opening 762 is formed to form the gate electrode. In the above steps, etching is performed by the dry etching method until the gate insulating film is etched. However, since the etching rate of anodic oxide (aluminum oxide) is significantly lower than that of silicon oxide, the anodic oxide is not etched in this step, and the anodic oxide serves as an etching stopper. (Fig. 7 (C))

Next, the steps will be described with reference to FIG. In this step, only the contact hole 759 is exposed, the others are covered with a photoresist mask, and the anodic oxide in the contact hole 759 is etched by a wet etching method. By doing so, a contact hole reaching the gate wiring 753 is formed. (FIG. 7D) Next, the process will be described with reference to FIG. This step is performed by using a known metal film forming technique and etching technique, and as a result, the metal wirings 710, 712, 76 are formed.
3, 764 and overlap gate electrode 717 are formed. (Fig. 7 (E))

[Embodiment 3] This embodiment will be described with reference to FIG. In this embodiment, as in Embodiments 1 and 2, fabrication of a circuit including not only the transistor of the present invention but also other transistors and wirings will be described. The main manufacturing steps of the circuit of this embodiment are as follows. Formation of semiconductor active layer (thin film semiconductor), gate insulating film, gate electrode / wiring and gate electrode part Doping and activation of doped impurities Overlap gate electrode formation Interlayer insulator film formation Source and drain regions Formation of contact holes in contact holes and gate wiring Formation of wiring using conductive material (metal, etc.) in the upper layer

In this embodiment, as described in Japanese Patent Laid-Open No. 6-291315, the surface of the metal gate electrode / wiring is anodized to form the gate electrode portion. However, nothing is disclosed in the TFT disclosed in JP-A-6-291315.
However, it is not applicable only to Japanese Patent Laid-Open No. 7-16
By using the side surface anodic oxidation technique described in Japanese Patent Publication 9974, the same can be carried out in a TFT in which an offset region and a low concentration impurity region are formed. First, the process is shown in FIG.
Will be explained. The present invention is mainly applied to T
FT to thin film semiconductor 808 and TF not
T is formed on the thin film semiconductor 851. The thin film semiconductors 808 and 851 are formed on the insulating substrate 800. In this embodiment, a polycrystalline silicon film crystallized by a laser annealing method is used as the thin film semiconductor.

A gate insulating film 819, gate electrodes 809 and 852, and a gate wiring 853 are formed so as to cover such a thin film semiconductor. In this embodiment, silicon oxide formed by a low pressure CVD method is used as the gate insulating film, and aluminum (containing 0.1 to 3% scandium) is used as the gate electrode. Gate electrode / wiring 809, 852,
The surface of 853 is covered with anodic oxide.
(FIG. 8A) Next, the process will be described with reference to FIG. This step is performed using a known impurity doping method. As a result, the N type source regions 801, 854 and the drain region 8 are formed.
02, 855 and floating island regions 803 to 805 are formed in a self-aligned manner. Further, the impurities introduced into the thin film semiconductor by doping are activated by a known method. In this embodiment, laser annealing using an excimer laser is adopted. (Fig. 8 (B))

Next, the process is shown in FIG. In this step, the floating island regions 803 to 805 are covered and overlapped by a known metal film forming and etching technique.
The gate electrode 817 is formed. (FIG. 8C) Next, steps and will be described with reference to FIG. This step is performed by using a known interlayer insulating film forming technique and contact hole forming technique. In this embodiment, silicon oxide is used as the interlayer insulator 856. (FIG. 8D) Then, the interlayer insulator 856 is etched to form the source regions 801, 854 and the drain regions 802, 855.
Contact holes 857 to 861 to the gate wiring 853
Is formed. The above etching process may be performed in multiple steps. (Figure 8 (D))

Next, the steps will be described with reference to FIG. This step is performed by using a known metal film forming technique and etching technique, and as a result, the metal wiring 810,
812, 863, 864 are formed. (FIG. 8 (E)) Compared with the first and second embodiments, one more metal wiring layer is added in this embodiment, but the overlap gate electrode may be crossed with the source wiring and the drain wiring. it can. The overlap gate electrode 817 may be formed so as to cover only the floating island regions 804 and 805, as shown in FIG. Even in this case, the effect of the present invention is not lost.

[Embodiment 4] This embodiment will be described with reference to FIG. The main manufacturing steps of the transistor of this example are as follows. Formation of semiconductor active layer (thin film semiconductor), gate insulating film, gate electrode / wiring, and gate electrode part Doping and activation of doped impurities Forming a film for an etching stopper Forming an interlayer insulator Contacting source and drain regions Formation of holes and holes for overlap gate electrodes Formation of wiring (including overlap gate electrodes) using conductive material (metal, etc.) in the upper layer

In this embodiment, as described in Japanese Patent Laid-Open No. 6-291315, the surface of the metal gate electrode / wiring is anodized to form the gate electrode portion. However, nothing is disclosed in the TFT disclosed in JP-A-6-291315.
However, it is not applicable only to Japanese Patent Laid-Open No. 7-16
By using the side surface anodic oxidation technique described in Japanese Patent Publication 9974, the same can be performed in a TFT in which an offset region and a low concentration impurity region are formed. First, the process is shown in FIG.
Will be explained. The present invention is mainly applied to T
The FT is formed on the thin film semiconductor 908. Thin film semiconductor 90
8 is formed on the insulating substrate 900.

A gate insulating film 919 and a gate electrode 909 are formed so as to cover such a thin film semiconductor. In this embodiment, silicon oxide formed by a low pressure CVD method is used as the gate insulating film, and aluminum (containing 0.1 to 3% scandium) is used as the gate electrode. The surface of the gate electrode / wiring 909 is covered with anodic oxide. (FIG. 9A) Next, the process will be described with reference to FIG. This step is performed using a known impurity doping method. As a result, the source region 901, the drain region 902, and the floating island regions 903 to 905 are formed in a self-aligned manner. Further, the impurities introduced into the thin film semiconductor by doping are activated by a known method. In this embodiment, laser annealing using an excimer laser is adopted. (Fig. 9 (B))

Next, steps and are shown in FIG. 9 (C).
In this step, the silicon nitride film 965 is formed by covering the floating island regions 903 to 905 by a known insulating film forming technique. Further, an interlayer insulator 956 of silicon oxide is also formed. (FIG. 9C) Next, the process will be described with reference to FIG. This step is performed using a known contact hole forming technique. The interlayer insulator 956 is etched to form contact holes 957 to the source region 901 and the drain region 902,
958 and hole 96 for the overlap gate electrode
2 is formed. In this etching step, the etching is stopped at the silicon nitride film 965 by utilizing the difference in etching rate between silicon oxide and silicon nitride.
(Fig. 9 (D))

After that, contact holes 957 and 958 are formed.
The silicon nitride film 965 is etched in a state where only the film is exposed and the others are covered with a photoresist. Thus, contact holes reaching the source region 901 and the drain region 902 are obtained. (FIG. 9E) Next, the process will be described with reference to FIG. This step is performed by using the known metal film forming technique and etching technique, and as a result, the source electrode / wiring 910, the drain electrode / wiring 912, and the overlap gate electrode 917 are formed. (Fig. 9 (F))

This embodiment is similar to the first and second embodiments, but is characterized in that a silicon nitride film is newly provided as an etching stopper. In Examples 1 and 2, there was a risk that the gate insulating films (519, 719) would be etched when the holes (562, 762) for the overlap gate electrodes were provided. If the coating 965 of the etching stopper is provided on the above, such a problem is eliminated. Furthermore, although silicon nitride easily traps positive charges, the overlap gate electrode has N
Considering that the channel type transistor is always held at a positive potential, there is no problem, and rather, the depletion layer is expanded by the trapped charges in addition to the applied voltage, which is more preferable.

[Embodiment 5] This embodiment will be described with reference to FIG. Unlike the first to fourth embodiments, the transistor of this embodiment is a bottom gate type in which the position of the gate electrode is on the substrate side. The main manufacturing steps of the semiconductor device of this embodiment are as follows. Gate electrode / wiring, gate insulating film, semiconductor active layer (thin film semiconductor) formation Doping mask formation Doping and activation of doped impurities Interlayer insulator formation Contact hole formation to source and drain regions Conduction of upper layer Of wiring (including overlap gate electrode) using conductive material (metal etc.)

In this embodiment, Japanese Patent Laid-Open No. 5-275452,
Alternatively, as described in JP-A 7-99317,
In order to obtain a bottom-gate type thin film transistor, a self-aligned doping mask is formed, and a thin film semiconductor is ion-doped and activated. The detailed conditions of this example, the thickness of the coating, etc. may be referred to the above publication. First, the process is described with reference to FIG. First, the gate electrode 209 is formed on the glass substrate 200. Since the glass substrate uses the backside exposure technique, it is required to transmit the light used for exposure.

As the gate electrode, aluminum (0.
Containing 1-2% silicon). The gate electrodes 209 in the figure are all obtained from the same film and are electrically connected. In order to increase the breakdown voltage, an anodic oxide film may be formed on the upper surface and the side surface of the gate electrode by the anodic oxidation method. Further, a gate insulating film of silicon oxide and a polycrystalline or amorphous silicon film 208 are formed thereon. In this example, silicon oxide was formed by a low pressure CVD method, and an amorphous silicon film was formed by a plasma CVD method, which was crystallized by a laser annealing method. Next, the steps will be described. This step uses a backside exposure technique. That is, after depositing a film of silicon nitride and applying a photoresist thereon, light is irradiated from the back surface to expose the photoresist. Then, the silicon nitride film is etched thereby, and the doping mask 265 is obtained. Although the doping masks 265 appear to be separate in the figure, they are all connected as well as the gate electrode 209 because the backside exposure technique is adopted. (Fig. 12
(B))

Next, the steps will be described. This step is performed using a known impurity doping method. As a result, the source region 201, the drain region 202, the floating island region 203
˜205 are formed in a self-aligned manner. Further, the impurities introduced into the thin film semiconductor by doping are activated by lamp annealing. Next, the process is shown in FIG.
An explanation will be given using (C). In this step, a silicon oxide film 256 as an interlayer insulator is formed by covering the thin film semiconductor 208 and the doping mask 265 by a known insulating film forming technique. The thickness of the inter-layer insulator 256 is not only the inter-layer insulation but also the gate insulation film of the overlap gate electrode, so that it must be avoided to be excessively thick. For example, in the case of silicon oxide, 1000
~ 3000Å is preferred. (Figure 12 (C))

Next, the steps will be described with reference to FIG. This step is performed using a known contact hole forming technique. The interlayer insulator 256 is etched to form contact holes 257 and 258 to the source region 201 and the drain region 202. (FIG. 12D) Next, the process will be described with reference to FIG. This step is performed using a known metal film forming technique and etching technique, and as a result, the source electrode / wiring 210, the drain electrode / wiring 212, and the overlap gate electrode 217 are formed. (Fig. 12 (E))

The overlap gate electrode 217 is shown in FIG.
2 (E), it may be made to continue uniformly, and FIG.
You may separate like (F). The former is effective when the etching stopper 265 is sufficiently thick. In such a case, since the etching stopper 256 exists, even if a forward bias voltage is applied to the overlap gate electrode 217, no channel is generated in the base region (non-doped portion). (Fig. 12
(F)) If the doping mask 256 is not thick enough, a channel will be generated in the base region. In order to prevent it, the overlap gate electrode 217 is formed as shown in FIG. It is necessary to divide so as not to cross the base region (that is, the overlap gate electrode 217 exists corresponding to each of the floating island regions 203 to 205).

[Sixth Embodiment] This embodiment will be described with reference to FIG. The transistor of this embodiment is a so-called top gate type in which the gate electrode is on the thin film semiconductor, but unlike the first to fourth embodiments, the source electrode / wiring and the drain electrode / wiring are under the thin film semiconductor, that is, It is a type opposite to the gate electrode (a positive stagger type). The main manufacturing steps of the semiconductor device of this embodiment are as follows. Source electrode / wiring and drain electrode / wiring, semiconductor active layer (thin film semiconductor) formation Gate insulating film, gate electrode formation Doping and activation of doped impurities Interlayer insulation film formation Overlap gate electrode formation

First, the steps will be described with reference to FIG. First, the source electrode / wiring 31 is formed on the glass substrate 300.
0 and the drain electrode / wiring 312 are formed. Molybdenum is used for the source electrode / wiring 310 and the drain electrode / wiring 312. Other metals having relatively high heat resistance (tungsten, chromium, tantalum, nickel, etc.) may be used. Further, the amorphous silicon film 30
8 is formed thereon and crystallized by a laser annealing method. (FIG. 13 (A)) Next, it moves to a process. In this step, a silicon oxide gate insulating film 319 and an aluminum gate electrode 309 are formed by a known film forming technique.
To form. (FIG. 13 (B)) Next, it moves to a process. This step is performed using a known impurity doping method. As a result, the source region 301,
The drain region 302 and the floating island regions 303 and 304 are formed in a self-aligned manner. Furthermore, the impurities introduced into the thin film semiconductor by doping are activated by laser annealing. (Figure 13 (C))

Next, the process proceeds. In this step, a silicon oxide film 356 as an interlayer insulator is formed to cover the gate electrode 309 by a known insulating film forming technique. The interlayer insulator 356 is thick enough to maintain insulation between the gate electrode 309 and the overlap gate electrode formed thereon, and at the same time, the interlayer insulator 3 is formed.
56 and the gate insulating film 319, the floating island region 30 below
3, 304 is required to be thin enough for an electric field to act on it. Therefore, if silicon oxide is used, 2
It is desired to set the thickness obtained by subtracting the thickness of the gate insulating film from 000 to 3000Å. Then move to the process.
This step is performed by using a known metal film forming technique and etching technique, and as a result, the overlap gate electrode 317 is formed. (Figure 13 (D))

[0071]

According to the present invention, it becomes possible to reduce the leak current when the thin film semiconductor device is not selected. However, the drain current at the time of selection is comparable to the conventional one, and as a result, the ON / OFF ratio can be improved. The thin film semiconductor device of the present invention has a high ON / OFF ratio and a high dynamic ON / OFF ratio like a pixel control transistor in an active matrix circuit of a liquid crystal display, which requires a low leak current between a source region and a drain region. Suitable for applications that require movement. Thus, the present invention is an industrially useful invention.

[Brief description of drawings]

FIG. 1 is a diagram for explaining the basic concept of the present invention.

FIG. 2 is a diagram for explaining the basic concept of the present invention.

FIG. 3 is a diagram showing a basic concept of the present invention.

FIG. 4 is a diagram for explaining the basic concept of the present invention.

5A to 5D are diagrams showing a manufacturing process of the semiconductor device of Example 1;

FIG. 6 is a diagram showing the operation principle of the semiconductor device of Example 1;

7A to 7C are diagrams showing a manufacturing process of a semiconductor device of Example 2;

8A to 8C are diagrams showing a manufacturing process of a semiconductor device of Example 3;

9A to 9C are diagrams showing a manufacturing process of a semiconductor device of Example 4;

FIG. 10 is a diagram for explaining the basic concept of the present invention.

FIG. 11 is a diagram for explaining the basic concept of the present invention.

12A to 12C are diagrams showing a process of manufacturing a semiconductor device of Example 5;

13A to 13C are diagrams showing a process of manufacturing a semiconductor device of Example 6;

[Explanation of symbols]

1 ... Source area 2 ... Drain region 3-6 ... Floating island region pole 7: Base area 8 ... Thin film semiconductor 9 ... Gate electrode 10 ... Source wiring / electrode 11 ... Drain wiring / electrode 12 ... Gate wiring 13 to 16 ... Doping hole (opening) 17 ... Overlap gate electrode 18 ... Overlap gate electrode wiring 20 ... Depletion layer

─────────────────────────────────────────────────── ─── Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 29/786 H01L 21/336

Claims (9)

(57) [Claims] 1. A thin film semiconductor device having an island- shaped thin film semiconductor, a gate insulating film, and a gate electrode, wherein the island-shaped thin film semiconductor has a source region of a first conductivity type to which a source electrode / wiring is connected. A drain region having the first conductivity type, to which a drain electrode / wiring is connected, and present between the source region and the drain region,
A base region exhibiting a conductivity type opposite to that of the intrinsic or first conductivity type, said first conductivity type exhibit, floating island region and the source region and the drain region separated by the base region, before An overlap gate electrode formed above or below the floating island region, and the gate electrode is provided above or below the base region via the gate insulating film, The shortest distance from the source region to the drain region via only the base region is larger than the shortest distance from the source region to the drain region via the base region and the floating island region. Thin film semiconductor device. 2. A thin film semiconductor device having an island- shaped thin film semiconductor, a gate insulating film, and a gate electrode, wherein the island-shaped thin film semiconductor has a source region of a first conductivity type to which a source electrode / wiring is connected. A drain region connected to the drain electrode / wiring and exhibiting the first conductivity type; and a base region connecting from the source region to the drain region and having an intrinsic conductivity type or a conductivity type opposite to the first conductivity type. exhibits the first conductivity type, chromatic and floating island region separated from the source region and the drain region by the base region, and the overlap gate electrode formed above or below the previous SL floating island region, the The gate electrode is provided above or below the base region via the gate insulating film. 3. A thin film semiconductor device having an island- shaped thin film semiconductor, a gate insulating film, and a gate electrode, wherein the island-shaped thin film semiconductor has a source region of a first conductivity type to which a source electrode / wiring is connected. A drain region connected to the drain electrode / wiring and having the first conductivity type; an intrinsic or a base region having a conductivity type opposite to the first conductivity type; and the first conductivity type the exhibits, the includes a floating island region separated from the drain region and the source region by the base region, a front Symbol floating islands on or overlap the gate electrodes formed below the region, and over the base region Alternatively, the gate electrode is provided below the gate insulating film, and a thin film semiconductor device is provided. 4. A thin film semiconductor device having an island- shaped thin film semiconductor, a gate insulating film, and a gate electrode, wherein the island-shaped thin film semiconductor has a source region of a first conductivity type to which a source electrode / wiring is connected. A drain region connected to the drain electrode / wiring and exhibiting the first conductivity type; and a base region connecting from the source region to the drain region and having an intrinsic conductivity type or a conductivity type opposite to the first conductivity type. the first conductivity type, and the source region and the drain region and the floating island region separated by the base region, and the overlap gate electrode formed above or below the previous SL floating island region, from only The gate electrode is provided above or below the base region via the gate insulating film, and the area of the base region is set to the base region. The value obtained by dividing the area other than the source region and the drain region of the island-shaped thin film semiconductor by the shortest path length from the source region to the drain region via only the region is the shortest distance from the source region to the drain region. A thin film semiconductor device characterized by being smaller than a value divided by a path length. 5. An average width of a route from the source region to the drain region through the base region is smaller than an average width of a route from the source region to the drain region through the island-shaped thin film semiconductor. The thin film semiconductor device according to claim 2. 6. The region having the impurity of the first conductivity type whose concentration is lower than that of the floating island region is provided at a boundary portion between the floating island region and the base region. 7. The thin film semiconductor device according to any one of 1 . 7. The thin film semiconductor device according to claim 1, wherein a forward bias voltage is applied to the overlap gate electrode. Wherein said overlap gate electrode, a thin film semiconductor device according to any one of claims 1 to 4, characterized in that it is formed on the gate electrode through the insulating film . 9. A plurality of floating island regions are formed.
The claim according to any one of claims 1 to 4.
Thin film semiconductor device.