CN101009322B - Light-emitting device - Google Patents

Light-emitting device Download PDF

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CN101009322B
CN101009322B CN 200710085012 CN200710085012A CN101009322B CN 101009322 B CN101009322 B CN 101009322B CN 200710085012 CN200710085012 CN 200710085012 CN 200710085012 A CN200710085012 A CN 200710085012A CN 101009322 B CN101009322 B CN 101009322B
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light emitting
tft
channel
emitting device
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CN 200710085012
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Chinese (zh)
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CN101009322A (en )
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宇田川诚
安西彩
小山润
早川昌彦
纳光明
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株式会社半导体能源研究所
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    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02BCLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B20/00Energy efficient lighting technologies
    • Y02B20/30Semiconductor lamps, e.g. solid state lamps [SSL] light emitting diodes [LED] or organic LED [OLED]
    • Y02B20/36Organic LEDs, i.e. OLEDs for general illumination

Abstract

The present invention provides a TFT that has a channel length particularly longer than that of an existing one, specifically, several tens to several hundreds times longer than that of the existing one, and thereby allowing turning to an on-state at a gate voltage particularly higher than the existing one and driving, and allowing having a low channel conductance gd. According to the present invention, not only the simple dispersion of on-current but also the normalized dispersion thereof can be reduced, and other than the reduction of the dispersion between the individual TFTs, the dispersion of the OLEDs themselves and the dispersion due to the deterioration of the OLED can be reduced.

Description

发光器件 The light emitting device

[0001] 本发明申请是本发明申请人于2002年11月9日提交的、申请号为02157583. 5、发明名称为“发光器件”的发明申请的分案申请。 [0001] The present application is the applicant of the present invention was invented in 2002, filed on November 9, Application No. 02157583.5, a divisional application entitled "light emitting device" of the claimed invention.

技术领域 FIELD

[0002] 本发明涉及半导体器件的制造方法,特别是,本发明涉及一种发光器件,它包括一个形成在具有绝缘表面的衬底上的有机发光器件(OLED)。 [0002] The present invention relates to a method for manufacturing a semiconductor device, in particular, the present invention relates to a light emitting device comprising an organic light emitting device on a substrate having an insulating surface (OLED) are formed. 本发明还涉及一个OLED组件,其中包括一个控制器或诸如此类的IC,被安装在OLED板上。 The present invention also relates to an OLED assembly, including a controller or the like of the IC, it is mounted on the OLED panel. 注意,在本说明书中,发光器件包括OLED板和OLED组件。 Note that, in this specification, the light emitting device includes the OLED panel and the OLED assembly. 使用发光器件的电子设备也包括在本发明之中。 An electronic device using the light emitting device are also included in the present invention.

[0003] 注意,在本说明书中,术语“半导体器件”一词通常表示能利用半导体特性起作用的器件,发光器件,电-光器件,半导体电路和电子器件统统包括在半导体器件之中。 [0003] Note that in this specification, the term "semiconductor device" generally indicates characteristics can function by utilizing semiconductor devices, the light emitting device, the electrical - optical devices, semiconductor circuits, and electronic devices were all included in the semiconductor device.

背景技术 Background technique

[0004] 近来,在一个衬底上形成TFT(薄膜晶体管)的技术有了很大进步,它在有源矩阵显示器上的应用正被积极研制。 Technology [0004] Recently, formation of TFT (thin film transistor) on a substrate has made great progress, it is used in an active matrix display are being actively developed. 特别是,使用多晶硅薄膜的TFT比传统的使用非晶硅薄膜的TFT具有更高的场效应迁移率(也称迁移率),因此,它能够快速操作。 In particular, the TFT using a conventional amorphous silicon thin film than the TFT using polysilicon thin film has higher field effect mobility (also called mobility), and therefore, it can operate quickly. 因此,由使用多晶硅薄膜的TFT组成的驱动电路被提供在和象素相同的一个衬底上,控制各个象素的研究正在积极进行。 Thus, a TFT driving circuit using a polysilicon thin film composed of pixels and is provided on a same substrate, each pixel is controlled study is actively. 由于在一个衬底上驱动电路和象素被合并入有源矩阵显示器中,就存在许多优点,例如,成本降低,显示器小型化,产量提高,生产能力提高。 Since driving circuits and the pixel is incorporated into an active matrix display on one substrate, there are many advantages such as cost reduction, miniaturization of the display, increase yield, improve the production capacity.

[0005] 此外,具有自发光元件OLED的有源矩阵发光器件(以后简称发光器件)正被积极研制。 [0005] Further, an active matrix self-luminous light emitting element OLED device (hereinafter abbreviated light emitting devices) are being actively developed. 发光器件也称有机EL显示器(OELD)或有机光发射二极管(OLED)。 The light emitting device is also called an organic EL display (the OELD) or an organic light emitting diode (OLED).

[0006] 一个OLED是具有高能见度的自发光元件,它对于制造薄显示器是最佳的,因为对于液晶显示器(LCD)这样的背面照明是不需要的。 [0006] OLED having a high visibility of the light emitting element, which is optimal for producing a thin display, such as for back-lighting a liquid crystal display (LCD) is not required. 进一步,视角没有限制。 Further, there is no viewing angle limitations. 因此,使用OLED 的发光器件作为CRT和LCD的替代显示器正在引起公众的注意。 Thus, light emitting device using OLED as CRT and LCD displays are an alternative to public attention.

[0007] —个通过在每个象素中安排多个TFT而显示图象并顺序地写一个视频信号的有源矩阵驱动系统,作为使用OLED元件的发光器件的一种型式已是公知的。 [0007] - by arranging a plurality of TFT in each pixel and sequentially writing the display image and an active matrix driving system of a video signal, as a type of light emitting device using OLED elements are well known. TFT是实现有源矩阵驱动系统不可缺少的元件。 TFT active matrix driving system is to achieve an indispensable element.

[0008] 此外,对于实现有源矩阵驱动系统的目的,在使用OLED的发光器件中,由于TFT控制流过OLED的电流量,当使用低电流效应迁移率非晶硅的TFT被采用时,这个目的便不能实现。 When [0008] Further, the active matrix driving system for achieving the purpose, the light emitting device using OLED, since TFT controls the amount of current flowing through the OLED, when the TFT using a low current effect mobility amorphous silicon is adopted, this The purpose can not be achieved. 最好是,具有晶体结构的半导体薄膜,特别是,使用多晶硅的TFT被采用,以便连接OLED。 Preferably, a semiconductor film having a crystalline structure, in particular, a TFT using polysilicon is adopted to connect OLED.

[0009] 具有晶体结构的半导体薄膜,特别是,多晶硅薄膜被用于形成TFT,象素和驱动电路一起形成在同一个衬底上,由此,连接终端的数目就显著减少,帧面积(象素部分的周围部分)也同时减少。 [0009] The semiconductor film having a crystal structure, in particular, a polysilicon film is used for forming the TFT, the pixel and the driver circuit are formed together on the same substrate, whereby the number of connecting terminals is markedly reduced, the area of ​​the frame (as surrounding portion of the pixel portion) is also simultaneously reduced.

[0010] 不过,即使TFT是用多晶硅形成,它的电特性最终也不等同于在单晶硅衬底中形成的MOS晶体管的特性。 [0010] However, even when the TFT is formed of polysilicon, its electrical characteristics is not equivalent to the final characteristics of the MOS transistor formed in a monocrystalline silicon substrate. 例如,传统TFT的电场效应迁移率等于或小于单晶硅的1/10。 For example, the field effect mobility of a conventional TFT is equal to or less than 1/10 of single crystal silicon. 进而,使用多晶硅的TFT有一个问题,即由于晶粒边界中形成的缺陷容易在其特性中引起离散作用。 Further, the TFT using polysilicon has a problem that the effect due to a defect prone discrete grain boundaries formed in its characteristics.

[0011 ] 在发光元件中,至少起开关元件作用的TFT和提供电流给OLED的TFT通常被安排在每个象素中。 [0011] In the light emitting element, at least from a TFT functioning as a switching element and a TFT supplies a current to the OLED is typically arranged in each pixel. 当高驱动能力(接通电流I。n)时在起开关元件作用的TFT中,低关断电流(Ioff)是需要的,防止由于热载效应引起的损坏和提高可靠性在提供电流给OLED的TFT中是需要的。 When the high driving ability (current ON I.n) in play in the TFT functioning as a switching element, a low off current (Ioff) is required to prevent damage due to thermal effects caused by the carrier, and improve reliability in supplying current to the OLED the TFT is required. 进而,高驱动能力(接通电流I。n),防止由于热载效应造成损坏和提高可靠性在数据线路驱动电路中也是需要的。 Further, high driving capacity (on current I.n), to prevent damage to the hot carrier effect and improve the reliability of the data line driving circuit is required.

[0012] 再者,象素的亮度是由TFT的接通电流(I。n)确定的,TFT与OLED电连接并提供电流给EL元件,而不取决于驱动方式,这就存在一个问题,如果在整个表面上显示白色的情况下接通电流不是恒定的,就会引起亮度的离散(dispersion)。 [0012] Moreover, luminance of the pixels is determined by the ON current of the TFT (I.n) is, electrically connecting the OLED and TFT supplies a current to the EL element without depending on the driving method, there is a problem which, If the case of displaying white on-current is not constant over the entire surface, it will cause a discrete brightness (dispersion). 例如,在通过光发射时间和执行64灰度调节亮度的情况下,与EL元件电连接并提供电流给OLED的TFT的接通电流, 从基准点移动一个灰度,离散为1. 56% ( = 1/64)。 For example, in the case of 64 gradation by adjusting the brightness and the light emission time of execution, the EL element is electrically connected to the current of the TFT is turned on and provides current to the OLED, a gradation move from the reference point, discretized 1.56% ( = 1/64).

[0013] 再者,当OLED形成的时候,EL层图案的间隙和EL层的厚度的不均勻性扰乱衬底。 [0013] Moreover, when OLED is formed, unevenness of the gap and the thickness of the substrate disturb the EL layer of the EL layer pattern. 发光度轻微有变化。 Slight luminance change. 鉴于上述问题,本发明要解决的课题是,减少每个TFT的特性变化,减少发光度的变化。 In view of the above problems, the present invention is to solve the problem is to reduce the characteristic variation of each TFT, to reduce the variation in luminosity.

[0014] 再者,本发明要解决的课题是,减少与TFT的特性变化无关的OLED中的变化,和减少发光度的变化。 [0014] Further, the present invention is to solve the problem is to reduce the change in characteristics of the TFT and the OLED irrespective of variations of, and reduce the variation in luminosity.

发明内容 SUMMARY

[0015] 再者,在传统的有源矩阵型发光器件中,当试图提高分辨率时候,孔径比受到象素部分中保持电容的电极和保持电容的布线,TFT,各种布线等的布局的限制的问题可能出现。 [0015] Further, in the conventional active matrix type light emitting device, when attempting to increase the resolution when the electrode, the aperture ratio by the pixel storage capacitor and the holding portion of the wiring capacitance, the layout of the TFT, various wirings such as the problems limit may occur. 本发明的目的是提供一个象素结构,它提高了象素部分中的孔径比。 Object of the present invention is to provide a pixel structure that improves the aperture ratio of the pixel portion.

[0016] 作为TFT特性的典型标记,VI特性曲线是已知的。 [0016] As a typical TFT characteristics marker, VI characteristic curve are known. 在VI特性曲线中升高处是最陡峭的(也称上升点),电流值变化最大。 The maximum increase in the VI characteristic curve is steepest (also referred to as a rising point), the current value changes. 因此,在供给OLED的电流受到TFT控制的情况下,当上升点分散的时候,提供电流给OLED的TFT的电流值大量分散。 Thus, the current is supplied to the OLED is controlled at the TFT, when the rising point of the dispersion, providing a current to the OLED current value of the TFT of large dispersion.

[0017] 上升点的电压值称做阈值电压(Vth),也是TFT的接通电压。 Voltage [0017] referred to the rising point threshold voltage (Vth), the TFT is turned on voltage. 此外,一般认为,Vth越接近零,越好。 In addition, generally it believed, Vth closer to zero, the better. 认为,当Vth变大,会引起驱动电压增高,功率损耗增大。 That, when the Vth becomes larger, causing the driving voltage increases, power loss increases.

[0018] 在TFT的电流值中有两种离散。 [0018] There are two discrete current value of the TFT. 具体地讲,一种是电流值的简单离散3Sigma,另一种是与在一特定数目的TFT总体电流值的中间值(平均值)有关的离散(在本说明书中, 这种离散也称作归一化离散)。 Specifically, one is the simple dispersion 3Sigma current value, and the other is related to a particular number of discrete intermediate value (average value) of the overall current value of the TFT (in the present specification, also referred to such discrete normalized dispersion).

[0019] 本发明发现有一种倾向,即后者离散强烈地取决于栅电压值(Vg)。 [0019] The present inventors have found that there is a tendency that the latter dispersion depends strongly on gate voltage value (Vg). 在图3中,各种沟道长度(5 μ m,10 μ m, 20 μ m, 50 μ m, 100 μ m, 200 μ m,和400 μ m)的ρ-沟道型TFT (沟道宽^W = Sym)中的Vgs与归一化离散之间的关系曲线被示出。 In Figure 3, various channel lengths (5 μ m, 10 μ m, 20 μ m, 50 μ m, 100 μ m, 200 μ m, and 400 μ m) of ρ- channel type TFT (channel width ^ W = Sym) versus the in Vgs between the discrete normalization is shown. 再者,在图4中,各种沟道长度的η-沟道型TFT (沟道宽度W = 8 μ m)中的Vgs与归一化离散的关系曲线被示出。 Further, in FIG. 4, the various channel lengths η--channel type TFT (channel width W = 8 μ m) of the normalized dispersion Vgs relationship curves are shown.

[0020] 现在根据TFT的实验数据,对本发明进行详细描述。 [0020] According to the experimental data now TFT, the present invention will be described in detail.

[0021] 当提供电流给OLED的TFT的沟道长度做得较长的时候,电流值变得较小,简单离散3sigma减少。 [0021] When current is supplied to the OLED TFT channel length is made longer when the current value becomes smaller, simple discrete 3sigma reduced. TFT的Vd设置在-7V,Vg设置在-3. 25V,沟道宽度固定在8 μ m,沟道长度分别在50 μ m, 100 μ m, 200 μ m,和400 μ m中变化。 Vd of the TFT provided -7V, Vg disposed -3. 25V, the channel width is fixed at 8 μ m, respectively, in the channel length 50 μ m, 100 μ m, 200 μ m, 400 μ m and changes. 对于每个TFT,接通电流的离散和归一化离散是被测量的。 For each TFT, discrete on-current and normalized dispersion are measured. 这些测量被示于图11中。 These measurements are shown in FIG. 11. 不过,如图11中所示,仅当沟道长度做得比较长,电流值变得比较小,但是,与一特定数目TFT的总体电流的中间值有关的离散(归一化离散)不会改变。 However, as shown in FIG. 11, is only done when the channel length is longer, the current value becomes smaller, however, associated with a current intermediate value of the overall number of specific variations in the TFT (normalized dispersion) does not change.

[0022] 在本发明中,为了使离散降低,TFT被设计有一个长的沟道长度,比曾经有过的长度长10倍或更多或长几百倍或更多,从而TFT可以在特别高的栅电压下进入接通状态,从外面输入的栅电压被设以驱动。 [0022] In the present invention, in order to reduce the dispersion, a TFT is designed with long channel length, there was 10 times longer than the length or over length of several hundred times or more, or more, so that the TFT may be particularly a high voltage gate enters an ON state, the gate voltage is inputted from the outside is set to drive.

[0023] Vd设定在-7V,沟道宽度固定在8 μ m,沟道长度被设定在50 μ m的TFT被测量其接通电流离散和在Vg = -3V时测量其归一化离散。 [0023] Vd is set at -7V, channel width is fixed at 8 μ m, the channel length is set at 50 μ m of TFT is turned on measured current and discrete normalized measured at Vg = -3V discrete. 接着,以类似的方式,沟道长度是100 μ m 的TFT在Vg = -3. 75V被测量,沟道长度是200 μ m的TFT在Vg = -3. 75V被测量,沟道长度是400 μ m的TFT在Vg = -5. 75V被测量。 Subsequently, in a similar manner, the channel length is 100 μ m of TFT -3. 75V is measured at Vg =, the channel length is 200 μ m of TFT -3. 75V is measured at Vg =, the channel length is 400 μ m in a TFT Vg = -5. 75V was measured. 这些测量结果示于图2中。 These measurement results are shown in Figure 2.

[0024] 如图2所示,当沟道长度做得较长,由此栅电压(Vg)比较大的时候,不仅接通电流的简单离散而且归一化离散可以被减小。 [0024] As shown in FIG 2, when the channel length is made longer, whereby the gate voltage (Vg) is relatively large when the current is not turned on and simple discrete normalized dispersion can be reduced. 在本实例中,为了使Vg较大,具有较长沟道长度的TFT被使用。 In the present example, in order to make the Vg larger, the TFT having longer channel length is used. 不过,不限于上述方法,为了使Vg较大,在容许设计限度内,沟道宽度W可以做得较短,TFT的源极区或漏极区可以做成高电阻性,或接触电阻可以做得较高。 However, not limited to the above method, in order to make the Vg larger, within permissible design limits, the channel width W can be made shorter, the TFT source region or the drain region can be made highly resistive, or a contact resistance may be done higher.

[0025] 再者,本发明提供一个TFT,它的沟道长度很长,具体地说,比现有技术的沟道长度要长几十倍到几百倍,从而TFT在比过去高得多的栅压下驱动进入接通状态,并能够具有低的沟道电导gd。 [0025] Further, the present invention provides a TFT, its channel length is very long, in particular, the channel length than prior art longer several times to several hundred times, so that a TFT is much higher than in the past the gate voltages driven into the ON state, and capable of having a low channel conductance gd. 图1示出了与图2对应的数据,它是一个曲线图,表示在与图2的数据相同条件(Vg,沟道宽度,沟道长度)下各个TFT的沟道电导gd。 FIG 1 shows data corresponding to FIG. 2, which is a graph showing channel conductance gd of individual TFT under the same conditions as the data in FIG. 2 (Vg, the channel width and channel length).

[0026] 在本发明中,当提供电流到OLED的TFT是在这样一个范围内被做成,即源-漏电压Vd和阈值电压Vth的总和大于栅压Vg,即在这样一个范围,Vg< (Vd+Vth)的时候,沟道电导从0到IX 10-8S,最好是5X 10-9S或更小,进一步,最好是2 X 10_9S或更小,从而流入TFT的电流的离散可以被减小,一定的恒定电流可以流入0LED。 [0026] In the present invention, when a current is supplied to the OLED TFT are made within such a range, i.e., the source - the sum of the drain voltage Vd and threshold voltage Vth is larger than gate voltage Vg, i.e. in such a range, Vg < (Vd + Vth) when the channel conductance from 0 to IX 10-8S, preferably 5X 10-9S or less, more preferably 2 X 10_9S or less, so that the current flowing into the TFT may be discrete is reduced, the constant current can flow into certain 0LED.

[0027] 除上述情况以外,由于较小的沟道电导gd,由于图型化或热处理使EL层中面积缩小引起的OLED自身的离散也可被减小。 [0027] In addition to the above, due to the smaller channel conductance Gd, since the heat treatment or pattern area reduction caused by the OLED EL discrete layer itself may also be reduced. 再者,通过使沟道电导gd变小,即使OLED由于某种原因损坏,流入OLED的电流也可以维持在一个恒定值,结果维持了恒定的亮度。 Further, by making the channel conductance gd smaller, even when the OLED damaged for some reason, the current flowing into the OLED can be maintained at a constant value, the result is maintained constant brightness. 在图12 中,Id-Vd曲线和OLED的负载曲线被示出。 In FIG. 12, Id-Vd curves and load curves of the OLED are shown. 沟道电导gd表示Id-Vd曲线的斜率,随着沟道电导gd做得越小,Id-Vd曲线的斜率变得越小,导致基本上恒定的电流值。 Channel conductance gd represents the slope of the Id-Vd curve, as do the smaller channel conductance gd, the slope of the Id-Vd curve becomes smaller, resulting in a substantially constant current value. 在图12中,OLED 的负载曲线表示输入OLED的电流值和当Vg = -3. 3V且连接到OLED的ρ沟道TFT在饱和区中被驱动时Vd之间的关系。 In FIG 12, OLED load curve showing the relationship between the values ​​of the input current and the OLED Vd when Vg = -3. 3V and connected to the OLED ρ-channel TFT is driven in a saturation region. 例如,当-Vd是-17V时,由于阴极侧上的电压是-17V,则输入到OLED上的电压就是0V。 For example, when -Vd is -17 V, since the voltage on the cathode side is -17 V, the input voltage to the OLED is 0V. 因此,输入到OLED上的电流也变成零。 Accordingly, the current input to the OLED becomes also zero. 再者OLED的Id-Vd曲线和负载曲线的交叉点上的电流值与亮度对应。 Note that the current value corresponding to the luminance on the Id-Vd curve and the intersection point of the OLED load curve. 在图12中,当gd较小时,交叉点处的-Vd 是-7V。 In FIG 12, when the gd is small, -Vd is at the intersection -7V. 在那时,输入到OLED的电流值是1X10_6[A],对应于这个电流值的发光亮度可以被获得。 At that time, a current value input to the OLED is 1X10_6 [A], the current value corresponding to the emission luminance can be obtained. 当gd较小的时候,OLED负载曲线无论向左,向右哪边移动,电流值几乎不改变,结果亮度就是均勻的。 When smaller when gd, the OLED regardless of the load curve to the left, which side moves to the right, the current value hardly changes, the result is a uniform brightness. 再者,当单一OLED自己离散的时候,其负载曲线或向右移动或者向左移动。 Further, when a single OLED their discrete time, the load curve or rightward or leftward. 再者,当OLED损坏的时候,OLED的负载曲线移向左边。 Furthermore, when the OLED when damaged, OLED load curve moves to the left. 在gd是较大的情况下,当由于损坏OLED的负载曲线向左边移动,曲线变成用虚线表示的曲线的时候,和OLED的负载曲线的交叉点改变了,结果是,损坏前和损坏后的电流值不同。 In the gd is larger, when the load curve of the OLED due to damage moves to the left, the curve becomes the curve indicated by broken lines, when the load curve and the intersection of the OLED is changed, as a result, damage to the front and rear damage different current values. 另一方面,在gd比较小的情况下,即使当OLED的负载曲线由于损坏而移向左边,电流值几乎不变,从而亮度的分散被减小,结果产生均勻的亮度。 On the other hand, in the case where gd smaller, even when the load curve of the OLED due to damage moves to the left, the current value hardly changes so that the dispersion of the brightness is reduced, resulting in uniform brightness.

[0028] 这里,为了使沟道电导gd较低,沟道长度做得较长,从而TFT在一个远高于现有技术的驱动电压下进入接通状态。 [0028] Here, in order to make the channel conductance Gd lower, the channel length is made longer, so that TFT enters the on state at a much higher than the prior art driving voltage. 不过,用其它方法,沟道电导gd可以进一步降低。 However, other methods, the channel conductance gd may be further lowered. 例如,通过在LDD结构中形成TFT,或通过把沟道形成区分成多个子区,沟道电导gd可以被降低。 For example, by forming the TFT in a LDD structure, or by forming a channel region into a plurality of sub-regions, the channel conductance gd may be reduced.

[0029] 用在液晶板中的象素,大多数的η沟道TFT,尺寸是沟道长度LX沟道宽度W = 12μπιΧ4μπι,禾口LXW = 12μπιΧ6μπι。 [0029] In the liquid crystal panel with a pixel, most η channel TFT, and the channel length dimension LX channel width W = 12μπιΧ4μπι, Wo port LXW = 12μπιΧ6μπι. 通常,为了提高开口面积的比率,认为TFT在象素中占的面积,即占有面积,越小越好。 Generally, in order to improve the ratio of the opening area, that accounts for TFT in the pixel area, i.e. the area occupied by the smaller the better. 因此,很难想象能使沟道长度是100 μ m或更长。 Thus, it is difficult to imagine a channel length can be 100 μ m or more. 再者,已经发现,如图4所示,在沟道长度是5 μ m或10 μ m的情况下,Vg最小分散范围是在8V 到10V,当Vg是IOV或更多的时候,分散有增加的趋势。 Furthermore, it has been found that, as shown in the channel length is 5 μ m or 10 μ m case, Vg is the minimum dispersion in the range of 8V to 10V 4, when Vg is IOV or more when dispersed increasing trend. 因此,不能认为,在沟道长度做成100 μ m或更长的情况下,Vg越大,离散越小。 Therefore, it can not be considered, case made of 100 μ m or longer in the channel length, Vg larger, the smaller the dispersion.

[0030] 再者,当沟道长度做成100 μ m或更大,各种形状都可以被认为是半导体层。 [0030] Further, when the channel length is made 100 μ m or more, various shapes can be considered to be a semiconductor layer. 例如, 一种形状,半导体层102在X方向迂回前进,如图6中所示(在本说明书中称做A型),一种形状,半导体层1102在Y方向上迂回前进,如图13A中所示(在本说明书中称为B型),和矩形形状(半导体层1202)如图13B中所示。 For example, a shape of the semiconductor layer 102 weave in the X direction, as shown in FIG. 6 (called type A in the present specification), a shape of the semiconductor layer 1102 weave in the Y direction, as shown in FIG. 13A as shown (referred to herein as type B), and a rectangular shape (a semiconductor layer 1202) as shown in FIG 13B.

[0031] 再者,当沟道长度做得较长,在作为形成TFT的步骤之一的激光束辐射的情况下,激光束的离散也可被降低。 [0031] Further, when the channel length is made longer, in the case where the step of forming a TFT as a laser beam radiation of one discrete laser beam can also be reduced. 对于每个TFT尺寸和半导体层形状的组合,LXff = 87 μ mX7 μ m(矩形形状)LX W = 165 μ mX 7 μ m(矩形形状),LXff = 88ymX4ym( 形形状),LXff = 165ymX4ym(失巨形形状),LXff = 500 μ mX4 μ m(A 型),禾口LXW = 50(^11^4“111出型),激光束的扫描速度设置在1111111/^(3或0.5111111/^(3,TFT被制备。对于这些TFT,实验研究了TFT尺寸和半导体层的形状,和TFT的接通电流的离散(3sigma)之间的关系。这里,激光束照射提高了多晶硅的结晶度。在图18中,是栅压Vg = -5V,Vd = -6V 情况下的实验结果,图19,是栅压Vg = -10V, Vd = -6V情况下的实验结果。在图18和19 中,接通电流的中间值(μΑ)也被示出。再者,TFT尺寸和半导体层的形状,和TFT的阈值(Vth)的分散(3Sigma)之间的关系可以从图20获得。 For each combination of size of the TFT and the semiconductor layer shapes, LXff = 87 μ mX7 μ m (rectangular shape) LX W = 165 μ mX 7 μ m (rectangular shape), LXff = 88ymX4ym (shape), LXff = 165ymX4ym (Loss giant shape), LXff = 500 μ mX4 μ m (a type), Wo port LXW = 50 (^ 11 ^ 4 "111-out), the scanning speed of the laser beam is provided 1111111 / ^ (3 or 0.5111111 / ^ ( . 3, TFT was prepared. for these TFT, TFT experimental study of the size and shape of the semiconductor layer, and the relationship between the oN current of the TFT discrete (3sigma). here, the laser beam is irradiated to improve the crystallinity of polysilicon. in 18, a gate voltage Vg = -5V, the experimental results in the case of Vd = -6V, FIG. 19, a gate voltage Vg = -10V, the experimental results in the case of Vd = -6V in FIGS. 18 and 19, ON intermediate value of the current (μΑ) are also shown. Further, the size and shape of the semiconductor layer of the TFT, and the TFT of the relationship between the threshold value (Vth) of the dispersion (3 Sigma) 20 can be obtained from FIG.

[0032] 从图18和19看出一种倾向,沟道长度L越长,接通电流的离散越小。 [0032] seen in FIGS. 18 and 19 a tendency, the longer the channel length L, the smaller the dispersion of on-current. 激光束的离散在激光扫描速度为0. 5mm/sec时比在lmm/sec要小,沟道长度L做得越长,不同激光扫描速度的离散差越小。 Discrete laser beam in a laser scanning speed of 0. 5mm / at lmm / sec sec is smaller than, the channel length L is made longer, the smaller the difference between the discrete different laser scanning speeds. 即可以认为,沟道长度L做得越长,激光的离散减小的越多。 That can be considered, the channel length L is made longer, the dispersion of the laser is reduced more. 再者,可以看到,减少最多的离散是LXW = 500 μπιΧ4μ m,接通电流的离散A型比B型要小。 Further, it can be seen is reduced most discrete LXW = 500 μπιΧ4μ m, discrete on-current is smaller than type A type B.

[0033] 鉴于上述情况,从图18和19中可以看出,发光器件的亮度的离散可以被减小,其中提供电流到OLED的TFT工作在直到饱和区被达到的电压范围内。 [0033] In view of the foregoing, it can be seen from FIGS. 18 and 19, the brightness of the discrete light emitting device can be reduced, which provides current to the OLED in the operation of a TFT saturation region until the voltage range is reached.

[0034] 再者,当比较固定在一个恒定值的流进TFT的电流值的时候,沟道宽度W最好比较小。 [0034] Further, when the value of the current flowing into the TFT fixed at a constant value comparison, when the channel width W is preferably relatively small. 图21是一个图表,表示当电流值被固定在恒定值(Id = 0.5 μ A)时的离散。 FIG 21 is a graph showing the time when the discrete current value is fixed at a constant value (Id = 0.5 μ A). 从图21 可以看到,发光器件的亮度的离散可以被减小,其中提供电流到OLED的TFT工作在饱和区。 As seen in Figure 21, the brightness of the discrete light emitting device can be reduced, which supplies a current to the OLED operation of a TFT in a saturation region. 再者,类似地可以看到减少最多的离散是在LXW = 500 μ mX4 μ m中,A型接通电流的离散小于B型。 Further, similarly can see the largest reduction in discrete LXW = 500 μ mX4 μ m, A is turned discrete type B type is less than the current.

[0035] 再有,从图20看出一种趋向,沟道长度L越长,阈值电压(Vth)的离散越小。 [0035] Further, a tendency of FIG 20 seen from the longer the channel length L, the smaller the threshold voltage (Vth) discrete.

[0036] 还有,由于随着沟道长度L做得较长,阈值值和接通电流两者的离散,即TFT的电特性,下降,由此可以认为,不仅激光束的离散被减小,而且由于其它过程产生的离散也被减少。 [0036] Further, since as the channel length L is made longer, the threshold value and both the discrete ON current, i.e., the electrical characteristics of the TFT, down, whereby it is considered that the laser beam is only reduced discrete but also due to other discrete process occurs is also reduced.

[0037] 还有,同样是在具有OLED的发光器件中,可以认为,提供给象素的TFT的占有面积越小,TFT越好。 [0037] Further, also in the light emitting device having an OLED, it is considered that the area occupied by the pixel TFT is provided to the smaller, the better the TFT. 因为目前TFT尺寸较小,单个TFT特性中的离散就比较大,这是显示器显示参差不齐的主要原因。 Because the current TFT size is small, discrete individual TFT characteristics is relatively large, uneven display which is the main display. [0038] 在流入OLED的电流由TFT控制的情况下,大致划分,有两种方法。 [0038] In the case where the current flows into the OLED is controlled by the TFT, largely divided, there are two methods. 具体地讲,一种方法是控制所谓饱和区的电压区中的电流,另一种方法是,控制直到饱和区被达到的电压区中的电流。 In particular, a method is called a saturation region current control voltage region, another method is to control the current until the voltage reaches the saturation region is region. 如图9所示,当某个恒定栅压被施加,同时源-漏电压Vd逐渐上升,在源极和漏极之间流动的电流值被测量时,TFT的Vd-Id曲线可以被获得,其中在某个Vd值以上电流值变成基本上恒定的图表可以被获得。 9, when a constant voltage is applied to the gate, while the source - drain voltage Vd is gradually increased, the current value flowing between the source and the drain are measured, the Vd-Id curve of the TFT can be obtained, wherein the current value above a certain value of Vd becomes substantially constant can be obtained chart. 在本说明书中,在Vd-Id曲线中,电流值变成基本上恒定的范围称做饱和区。 In the present specification, in the Vd-Id curve, the current value becomes substantially constant in a range called the saturation region. [0039] 即使提供电流给OLED的TFT工作在直到达到饱和区为止的电压范围内,本发明也是有效的。 [0039] Even if a TFT supplies a current to the OLED operate until the voltage range until the saturation region, the present invention is effective. 不过,当提供电流给OLED的TFT工作在饱和区的时候,流入OLED的电流是保持恒定的,减小离散的效果是明显的。 However, when current is supplied to the OLED is current at the time of the saturation region operation of a TFT flows into the OLED is maintained constant, discrete reducing effect is obvious. [0040] 再者,对于TFT提供电流给0LED,最好使用ρ沟道型TFT,它的离散比η沟道型TFT 减少得更多,如图3和4所示。 [0040] Further, TFT for supplying a current to 0LED, ρ-channel type TFT is preferable to use, it η than discrete channel TFT reduced more, as shown in FIG. 3 and 4. 不过,在本发明中,提供电流给OLED的TFT可以是η沟道型TFT和ρ沟道型TFT的任何一个。 However, in the present invention, there is provided a current to the OLED TFT may be any of the η ρ-channel type TFT and channel type TFT. 例如,在提供电流给OLED的TFT是ρ沟道型TFT的情况下,连接形式仅如图IOA中所示。 For example, in a TFT supplies a current to the OLED is illustrated in the case where the ρ-channel TFT, is connected in the form of only the IOA FIG. 再者,例如,在提供电流给OLED的TFT是η沟道型TFT的情况下,连接仅如图IOB所示。 Further, for example, supplies a current to the OLED in the case where the TFT is η-channel TFT, is connected as shown in only FIG IOB. 在图IOA和IOB的每一种情况下,虽然仅有提供电流给OLED 的TFT被示出,不用说,在TFT的栅极之后,由多个TFT制成的各种电路可以被安排。 In each case of FIGS. IOA and IOB, although only the TFT supplies a current to the OLED is shown, needless to say, after the gate of the TFT, various circuits made of a plurality of TFT may be scheduled. 即,电路结构不只一个。 That is, more than one circuit configuration. [0041] 在本说明书中公开的本发明的一个结构是具有发光元件的发光器件,发光元件包括:[0042] 一个阴极,[0043] 一个与阴极接触的有机化合物层;以及[0044] —个与有机化合物层接触的阳极;[0045] 其中连到发光元件的TFT的沟道长度L是100 μ m或更长,最好是100 μ m到500 μ m0[0046] 在结构中,TFT的沟道宽度W与其沟道长度L之比是0. 1到0.01。 [0041] A structure of the present invention disclosed in the present specification is a light emitting device having a light emitting element, a light emitting element comprising: [0042] a cathode, [0043] an organic compound layer contacting the cathode; and [0044] - a an organic compound layer in contact with the anode; [0045] wherein a TFT connected to the light emitting element to the channel length L is 100 μ m or more, preferably 100 μ m to 500 μ m0 [0046] in the structure, the TFT its channel width W ratio of the channel length L is 0.1 to 0.01. [0047] 在本说明书中公开的本发明的另一个结构是具有发光元件的发光器件,发光元件包括:[0048]阴极;[0049] 与阴极接触的有机化合物层;以及[0050] 与有机化合物层接触的阳极;[0051] 其中连到发光元件的TFT的沟道宽度W与其沟道长度L的比是0. 1到0. 01。 [0047] Another structure of the present invention disclosed in the present specification is a light emitting device having a light emitting element, a light emitting element comprising: [0048] cathode; [0049] The organic compound layer contacting the cathode; and [0050] with an organic compound contacting the anode layer; [0051] wherein L is connected to the light emitting element than the TFT channel width W of its channel length is 0.1 to 0.01. [0052] 在各种结构中,连到发光元件的TFT,在源-漏电压Vd和阈值电压Vth的总和大于栅压Vg的范围内,具有沟道电导gd从0到1 X IO-8S,最好是0到5 X IO-9S,更优选的是0到2 X KT9S。 [0052] In various configurations, the TFT connected to the light emitting element, the source - drain voltage Vd and the sum of the threshold voltage Vth is larger than gate voltage Vg range, having a channel conductance gd from 0 to 1 X IO-8S, preferably 0 to 5 X IO-9S, more preferably from 0 to 2 X KT9S. [0053] 在本说明书中还公开了本发明的另一种结构是具有发光元件的发光器件,发光元件包括:[0054]阴极;[0055] 与阴极接触的有机化合物层;以及[0056] 与有机化合物层接触的阳极;[0057] 其中连到发光元件的TFT,在源-漏电压Vd和阈值电压Vth的总和大于栅压Vg的范围内,具有沟道电导gd从0到2 X IO-9S。 [0053] In the present specification also discloses another structure of the present invention is a light emitting device having a light emitting element, a light emitting element comprising: [0054] cathode; [0055] organic compound layer contacting the cathode; and [0056] with an organic compound layer contacting the anode; [0057] wherein the TFT connected to the light emitting element, the source - drain voltage Vd and the range of the threshold voltage Vth of the gate voltage Vg is greater than the sum, a channel conductance gd from 0 to 2 X IO- 9S. [0058] 在各个结构中,连到发光元件的TFT是ρ沟道型TFT或η沟道型TFT。 [0058] In each configuration, a TFT connected to the light emitting element is η or ρ-channel type TFT channel type TFT. [0059] 在本说明书中所谓沟道区的区是指这样一个区域,它包括一个部分(也称为沟道),在这个部分中载流子(电子和空穴)流动,在载流子流动方向上沟道区的长度叫做沟道长度,它的宽度就是沟道的宽度。 [0059] In the present specification, the region called the channel region refers to a region including a portion (also referred to as a channel), the carriers (electrons and holes) flow in this portion, the carrier longitudinal flow direction of the channel region is called a channel length, its width is the width of the channel. [0060] 再者,在本说明书中,沟道电导gd是指沟道的电导,它可以用下式表示。 [0060] Further, in the present specification, the channel conductance gd refers to the conductance of the channel, which can be represented by the following formula. [0061][等式 1][0062] gd = W(Vg-Vth) μ nC0X/L[0063] 在等式1中,L表示沟道长度,W是沟道宽度,Vg是栅压,Vth是阈值电压,μ η是迁移率,Cox是氧化膜电容。 [0061] [Equation 1] [0062] gd = W (Vg-Vth) μ nC0X / L [0063] In Equation 1, L denotes a channel length, W is the channel width, Vg is a gate voltage, Vth is the threshold voltage, μ η is the mobility, Cox is the oxide film capacitance. 在TFT中,当Vg等于或大于Vth时,沟道电导就开始产生。 In the TFT, when the Vg is equal to or larger than Vth of, the channel conductance starts to generate. [0064] 除此而外,沟道长度L做得较长,氧化膜电容Cox就较大。 [0064] Besides, the channel length L is made longer, the oxide film capacitance Cox on large. 因此,电容可以部分地用作为OLED的保持电容。 Therefore, the capacitance can be partially used as the retention capacitance of the OLED. 到现在为止,为了形成保持电容,对于每个象素,形成保持电容的空间是必需的,电容线和电容电极就安排在其中。 Until now, in order to form a storage capacitor for each pixel, form a capacitor holding space is required, and the capacitor electrode on the capacitor line arranged therein. 不过,当本发明的象素结构被采用的时候, 电容线和电容电极可以被省略。 However, when the pixel structure of the present invention is employed, the capacitance line and the capacitance electrode can be omitted. 再者,在保持电容和氧化膜电容Cox —起形成的情况下,保持电容可以由栅电极和半导体(沟道区)形成,半导体(沟道区)与栅极重叠,栅绝缘层作为电介质,安排在它们之间。 Further, in the oxide film and the capacitance of the storage capacitor Cox - formed from the case, the storage capacitor may be formed by the gate electrode and a semiconductor (channel region), the semiconductor (channel region) overlapping with the gate, the gate insulating layer as a dielectric, arrangements between them. 因此,即使在TFT的沟道长度做得较长的情况下,如图5所示, 当TFT的半导体层102安排在布置在栅极和源线上层的电源线106的下面的时候,象素可以被设计而不减少开口面积比。 Accordingly, even when the channel length of the TFT is made is long, as shown in FIG. 5, when the TFT semiconductor layer 102 arranged beneath the gate and source lines arranged in the upper power supply line 106, the pixel It can be designed without decreasing the open area ratio. 即,当本象素结构被实现的时候,即使电容线和电容电极的空间被忽略,足够的保持电容可以被提供,因而开口面积比可以得到进一步提高。 That is, when the present pixel configuration is implemented, even if the space capacitance line and the capacitance electrode is omitted, sufficient retention capacitance can be provided, and thus the opening area ratio can be further improved. [0065] 在TFT尺寸和半导体层形状的组合中,如图18和19所示,氧化膜电容C。 [0065] In combination with TFT and the size and shape of the semiconductor layers, 18 and 19, the oxide film capacitance C. x分别是192 (fF)对应于LXW = 87ymX7ym( )情况,364. 5 (fF)对于LXW = 165μπιΧ7μπι(矩形形状)情况,111. l(fF)对应于LXW = 88 μ mX4 μ m(矩形形状)情况,208.3 (fF)对应于LXW= 165 μ mX 4 μ m(矩形形状)情况,631. 3 (fF)对应于LXW = 500μπιΧ4μπι(Α 型)情况,631. 3(fF)对应于LXW = 500ymX4ym(B 型)情况。 x are 192 (fF) corresponding to LXW = 87ymX7ym () cases, 364. 5 (fF) for LXW = 165μπιΧ7μπι (rectangular shape) case, 111. l (fF) corresponding to LXW = 88 μ mX4 μ m (rectangular shape ) case, 208.3 (fF) corresponding to LXW = 165 μ mX 4 μ m (rectangular shape) case, 631. 3 (fF) corresponding to LXW = 500μπιΧ4μπι (Α type) case, 631. 3 (fF) corresponding to LXW = 500ymX4ym (B type) case. 再者, 当氧化膜电容Cox被获得的时候,其它值设定如下。 Further, when the oxide film capacitance Cox is obtained, other values ​​are set as follows. S卩,栅绝缘膜(氧化膜)Tox的膜厚是115nm, ε。 S Jie, the film thickness of the gate insulating film (oxide film) Tox is 115nm, ε. 是8. 8542 X 1(Γ12 (F/m2),8。!£是4. 1。[0066] 再者,在各结构中,连接发光元件的TFT的电容Cox是IOOfF或更多,最好是在IOOfF到700fF的范围内。[0067] 再者,在各个结构中,连接到发光元件的栅极和安排在其上的布线形成一个保持电容。具体地讲,如图5所示,由于层间绝缘膜(有机绝缘膜或无机绝缘膜)安排在栅极100上作为电介质,栅电极100和与栅电极重叠的电源线106就形成一个电容。在图5中, 栅极100和电源线106重叠(12μπιΧ127μπι =约15Μμπι2)的面积大,可是,取决于膜的厚度和层间绝缘膜的介电常数,保持电容可以形成。在栅极100和电源线106之间形成的所有电容能够起EL元件的保持电容的作用。因此,最适当的优选设计是,连接发光元件的TFT的电容Cox和在TFT的栅极和电源线106之间形成的电容之总和可以是几百fF。[0068] 在本说明书中,在OLED的阳极和阴极 Is 8. 8542 X 1 (Γ12 (F / m2), 8.! £ is 1. 4. [0066] Further, in the structure, the light emitting element is connected to the capacitor Cox TFT is IOOfF or more, preferably IOOfF in the range of 700fF. [0067] Further, in each structure, a gate connected to the light emitting element arranged thereon and a wiring is formed on a storage capacitor. More specifically, as shown in FIG. 5, since an interlayer insulating film (an organic insulating film or inorganic insulating film) is arranged as a dielectric on the gate electrode 100, a gate electrode 100 overlaps the gate electrode and the power supply line 106 to form a capacitor. in FIG. 5, the gate electrode 100 and the power line 106 overlap (12μπιΧ127μπι = about 15Μμπι2) of large area, however, depending on the thickness and dielectric constant of the inter-layer film of the insulating film, the storage capacitor may be formed. All the capacitance between the gate 100 and the power supply line 106 can be formed from effect of the storage capacitor EL element. Thus, the most suitable design that preferably, the sum of capacitance of the TFT connected to the light emitting element and the capacitor Cox is formed between the TFT gate electrode and the power supply line 106 may be several hundreds fF. [0068 ] in the present specification, the anode and cathode in the OLED 间形成的所有层被规定为有机[0069] 发光层。具体地讲,有机发光层,包括一个发光层,空穴注入层,电子注入层,空穴输运层,电子输运层。基本上,OLED的结构是,阳极,发光层和阴极是顺序叠置的。除了这种结构,还有其它结构,其中阳极,空穴注入层,发光层,和阴极是顺序叠置的,或者是,阳极,空穴注入层,发光层,电子输运层,和阴极是顺序叠置的。[0070] 一个OLED包括一个含有机化合物(有机光发射材料)的层(以后称作,有机发光层),由此,当电场被加到阳极和阴极上的时候,可获得发光(电-发光)。在有机化合物的发光中,有当激发的单重态弛豫到基态(荧光)时产生的发光,有当激发的三重态弛豫到基态时产生的发光(磷光)。在本发明的发光器件中或者上述发光之一被使用,或者两种发光都被使用。[0071] 再者,在上面, All interlayer formed is defined as an organic [0069] The light-emitting layer Specifically, the organic light emitting layer comprising a light emitting layer, a hole injection layer, an electron injection layer, a hole transport layer, the electron transport layer. Substantially , the structure of the OLED are an anode, a light emitting layer and a cathode are sequentially stacked. in addition to this structure, there are other structures in which an anode, a hole injection layer, a light emitting layer, and a cathode are sequentially stacked, or, anode, a hole injection layer, a light emitting layer, electron transport layer, and a cathode are stacked in order. [0070] an OLED includes a layer of an organic compound (organic light emitting material) containing (hereinafter referred to as organic light emitting layer) emission generated when - (emission power) in the light emitting organic compound, there are relaxed when excited singlet state to the ground state (fluorescence), whereby, when an electric field is applied to the anode and the cathode when the light emission can be obtained. , when there emission (phosphorescence) generated when the ground state to the excited triplet state of relaxation. or one of the light-emitting light-emitting device to be used in the present invention, the light emitting or both are used. [0071] Further, in the above , 栅型TFT已被解释。不过,本发明的应用不限于特定的TFT结构。 本发明可以用于底栅型(反交错型)TFT和前交错型TFT。[0072] 还有,在本发明的发光器件中,显示屏幕的驱动方法不限于特定的方法。例如,点顺序驱动方法,线顺序驱动方法或平面顺序驱动方法可以被使用。特别是,对于线顺序驱动方法,分时分级驱动方法或面积分级驱动方法可以被适当应用。再者,输入到发光器件的源极线路的视频信号可以是模拟信号或数字信号,驱动电路等可以适当根据视频信号进行设计。附图说明[0073] 图1是TFT的沟道长度和沟道电导gd之间的关系图。 Gate type TFT has been explained, however, application of the present invention is not limited to a particular TFT structure. The present invention may be used in a bottom gate type (inversely staggered) TFT and a staggered TFT before. [0072] In the present invention, the light emitting device, a driving method of a screen display is not limited to a particular method. for example, a dot sequential driving method, a line sequential driving method or a plane sequential driving method can be used. in particular, for the line sequential driving method, time division driving method or fractionation area classification driving method may be appropriately applied. Further, the video signal inputted to the source line of the light emitting device may be an analog signal or a digital signal, the drive circuit and the like may be designed appropriately according to the video signal. BRIEF DESCRIPTION oF dRAWINGS [0073] FIG 1 is the relationship between the channel length of a TFT and channel conductance gd. [0074] 图2是电流离散3sigma和电流归一化离散3sigma的图。 [0074] FIG. 2 is a current and the current discrete 3sigma normalized discrete 3sigma of FIG. [0075] 图3是ρ沟道型TFT的电流离散和在一定沟道长度下的Vg之间的关系图。 [0075] FIG 3 is a relationship between the current ρ discrete channel type TFT and Vg at certain channel lengths. [0076] 图4是η沟道型TFT的电流离散和在一定沟道长度上的Vg之间的关系。 [0076] Figure 4 is η relationship between the current channel type TFT and Vg at certain discrete channel length. [0077] 图5是象素的顶视图。 [0077] FIG. 5 is a top view of a pixel. [0078] 图6是象素的顶视图。 [0078] FIG. 6 is a top view of a pixel. [0079] 图7是有源矩阵型光发射显示器件的截面结构图。 [0079] FIG. 7 is an active matrix type light emitting display device cross-sectional structure of FIG. [0080] 图8是有源矩阵型光发射显示器件的等效电路图。 [0080] FIG. 8 is an active matrix type light emitting display device is an equivalent circuit diagram. [0081] 图9是Id-Vd曲线图。 [0081] FIG. 9 is a graph showing the Id-Vd. [0082] 图IOA和IOB是OLED和连接OLED的TFT之间的连接关系图。 [0082] FIGS. IOA and IOB are connected to the relationship between the OLED and the OLED connected to the TFT. [0083] 图11是示出电流离散3sigma和归一化电流离散3sigma的视图。 [0083] FIG. 11 is a graph showing current and normalized dispersion 3sigma view of the current discrete 3sigma. [0084] 图12是OLED的负载曲线和Id-Vd曲线图。 [0084] FIG. 12 is an Id-Vd curve and the load curve of the OLED of FIG. [0085] 图13A和13B是象素的顶视图(实施例2)。 [0085] FIGS. 13A and 13B are a top view of a pixel (Example 2). [0086] 图14A和14B是组件图(实施例3)。 [0086] FIGS. 14A and 14B are component (Example 3). [0087] 图15是组件图(实施例3)。 [0087] FIG. 15 is a component (Example 3). [0088] 图16A到16F是电子学图(实施例4)。 [0088] FIGS. 16A to 16F are electronics (Example 4). [0089] 图17A到17C是电子学图(实施例4)。 [0089] FIGS. 17A to 17C are electronics (Example 4). [0090] 图18是本发明TFT尺寸和接通电流离散(在Vg = -5V时)之间的关系图。 [0090] FIG. 18 is a relationship between the TFT size of the present invention and the discrete on-current (at Vg = -5V time). [0091] 图19是本发明的TFT尺寸和接通电流(在Vg = -IOV时)的离散之间的关系图。 [0091] FIG. 19 is a TFT of the present invention and on the size relationship between the discrete current (at Vg = when -IOV) a. [0092] 图20是本发明的TFT尺寸和阈值电压离散之间的关系图。 [0092] FIG. 20 is a relationship between the TFT size of the present invention and the threshold voltage dispersion. [0093] 图21是本发明的TFT尺寸和在恒定电流值(Id = 0.5 μ A)下的接通电流的离散之间的关系图。 [0093] FIG. 21 is a relationship between the TFT size of the present invention are discrete and on-current at a constant current value (Id = 0.5 μ A) of. 具体实施方式[0094] 下面,实现本发明的模型将被解释。 DETAILED DESCRIPTION [0094] Hereinafter, the present invention is to achieve the model will be explained. [0095] 图5是具有OLED的发光器件的象素部分的局部放大顶视图。 [0095] FIG. 5 is a partial pixel portion having the light emitting device OLED is an enlarged top plan view. 在图5中,为简单起见,EL层未示出,仅仅一个OLED的电极(象素电极107)被示出。 In FIG. 5, for simplicity, the EL layer is not shown, an electrode (pixel electrode 107) only one OLED is shown. [0096] 在图5中,半导体层101是作为开关TFT的有源层工作,与栅极布线105重叠的区是沟道形成区,与源极布线104连接的区域是源区(或漏区),与连接电极103连接的区域是漏区(或源区)。 [0096] In FIG. 5, the semiconductor layer 101 is working as an active layer of the switching TFT, a region overlapping with the gate wiring 105 is a channel formation region, a source region connected to the wiring 104 is a source region (or drain region ), area of ​​the connection electrode 103 is connected to the drain region (or source region). 开关TFT是一双栅结构,它有两个沟道形成区。 A pair of switching TFT gate structure having two channel forming regions. [0097] 再者,半导体层102是作为TFT的有源层工作,TFT提供电流给0LED,与栅电极重叠的区是沟道形成区。 [0097] Further, the semiconductor layer 102 as an operation of the TFT active layer, the current supplied 0LED TFT, the gate electrode overlaps the region is a channel formation region. 提供电流给OLED的TFT的栅电极100与连接电极103连接。 Providing a current to the OLED is connected to the gate electrode of the TFT 100 is connected to the electrode 103. 还有, 提供电流给OLED的TFT的源区(或漏区)和电源线106连接,提供电流给OLED的TFT的漏区(或源区)和连接电极108连接,象素电极107与连接电极108接触。 Further, current is supplied to the OLED TFT source region (or drain region) and the power supply line 106 connected to the TFT supplies a current to the OLED drain region (or source region) and a connection electrode 108 connected to the pixel electrode 107 and the connection electrode 108 contacts. 再者,在栅电极100上,电源线106和相邻象素的源极布线被安排成部分重叠。 Further, on the gate electrode 100, source line 106 and the power source wiring adjacent pixels is arranged to partially overlap. 半导体层102,在与具有栅绝缘膜插入其间的栅电极重叠的沟道形成区的上方,电源线106和相邻象素的源极布线被安排成局部重叠。 The semiconductor layer 102 is formed over the gate electrode and the channel having a gate insulating film interposed therebetween overlap region, the power source line 106 and the source wiring adjacent pixels is arranged to partially overlap. 在栅电极100和电源线106之间形成的所有电容可被用作EL元件的保持电容。 All of the capacitance formed between the gate electrode 100 and the power supply line 106 may be used as the retention capacitance of the EL element. 因此,对于在栅电极100和电源线106之间形成的电容,必要的保持电容可以在一定程度上得到保证。 Thus, for the capacitance formed between the gate electrode 100 and the power supply line 106, necessary retention capacitance can be secured to some extent. [0098] 再者,图6是图5对应的顶视图,它是在半导体层101和102,栅极布线105和栅电极100形成阶段的视图。 [0098] Further, FIG. 6 is a view corresponding to FIG. 5, which is a view of the stage 101 and formed in the semiconductor layer 102, the gate wiring 105 and the gate electrode 100. 半导体层102与栅绝缘膜(未示出)插入其间的栅电极100重叠的区,即,沟道形成区在图6中用虚线示出。 Region 100 overlapping the gate electrode (not shown) is inserted between the semiconductor layer 102 and the gate insulating film, i.e., a channel forming region is shown in dashed lines in FIG. 6. [0099] 本发明打算提供一种对OLED提供电流的TFT,在该TFT中,沟道区的长度(沟道长度L)被做得特殊地长(L = 100到500 μ m,在本情况下采用500[0100] μ m),由此,TFT能够在比现有技术高得多的栅压上进入接通状态并驱动,其沟道电导gd较小(gd = 0到1 X 10Λ,最好是5 X IO-9S或更小,在本情况中是2 X 10_9S或更小)。 [0099] The present invention intends to provide an OLED current TFT provided in the TFT, the length (channel length L) of the channel region is made of special long (L = 100 to 500 μ m, in the present case the use of 500 [0100] μ m), thereby, the TFT enters the on state can be much higher than in the prior art to drive a high gate voltage, the channel conductance gd thereof smaller (gd = 0 to 1 X 10Λ, preferably 5 X IO-9S or less, or 2 X 10_9S is less in this case). [0101] 由于采取上述结构,如图2所示,在一组TFT被安排的象素部分中,在提供电流给OLED的TFT中,不仅接通电流的简单离散而且其归一化离散可以被减小,结果是具有OLED 的显示器件的亮度离散也减小。 [0101] As a result of the above-described configuration, as shown, a set of the pixel portion TFT is arranged in the TFT supplies a current to the OLED, not only simple dispersion switched current 2 and its normalized dispersion can be is reduced, the result is a discrete brightness of an OLED display device is also reduced. [0102] 再者,由于流入OLED的电流被控制在所谓饱和区的范围内的OLED驱动方法被采用,本发明展示出极明显的效果。 [0102] Further, since the current flowing into the OLED is controlled in the range of OLED driving method is called a saturation region is adopted, the present invention exhibits a very significant effect. 当如图12的结构被采用的时候,除在各个TFT之间的离散减少而外,OLED制造中引起的离散(在制作布线图案和热处理中EL层的面积压缩引起的OLED本身的离散)可以被减少。 When the structure of FIG 12 is employed, in addition to TFT dispersion is reduced between the respective outer, discrete (discrete area of ​​the OLED patterning and heat treatment of the EL layer itself due to compression) can be caused in manufacture OLED It is reduced. 再者,由于采用了图12的结构,除了在各个TFT之间的离散减少而外,即使OLED由于某种原因被损坏,流入OLED的电流可以保持恒定,结果是保持了恒定的亮度。 Further, since the structure of FIG. 12, except that the dispersion between the respective TFT outer reduced, even if OLED is damaged for some reason, the current flowing into the OLED can be maintained constant, resulting in maintaining a constant brightness. [0103] 再者,在本发明中,作为驱动OLED的方法,在直到饱和区达到为止的电压区中控制流入OLED的电流的方法也是有用的。 Method [0103] Further, in the present invention, as a method of driving the OLED in a voltage region until the saturation region reaches up to the control current flowing in the OLED are also useful. [0104] 不用说,本发明不限于图5和图6所示的顶视图。 [0104] Needless to say, the present invention is not limited to the top view shown in FIG. 5 and FIG. 6. 在图5和6中,发光器件穿过在其上形成TFT的衬底发光(图14所示发光器件是一个典型)被解释。 In Figures 5 and 6, the light emitting device is formed through the substrate on which the light emitting TFT (FIG. 14 is a typical light emitting device) is explained. 因此,象素电极107, 开口区域部分是一个连接电极108不能形成的区,为了使开口区域部分较大,沟道长度L长的TFT被安排在电源线106和源极布线的下面。 Thus, the pixel electrode 107, the opening area portion is a region of the connection electrode 108 is not formed, in order to make larger the length of the channel region of the opening portion of the length L TFT is arranged beneath the power supply line 106 and the source wiring. 在沟道长度L长的TFT的栅极100和电源线106之间形成的电容可以被用作EL元件的保持电容。 Capacitance between the channel length L of the gate of the TFT 100 and the power supply line 106 may be formed as a holding capacitance of the EL element. 再者,在图5和6相反方向上发光的发光元件情况下(图15所示发光元件是一个典型)开口区域部分变得与象素电极相同的区。 Further, the light-emitting element emits light in a direction opposite to FIG. 56 and the case (the light emitting element shown in FIG. 15 is a typical) open area portion becomes the same region of the pixel electrode. 因此,沟道长度L长的TFT可以安排在象素电极的下面,具有500 μ m或更长沟道长度L的TFT可以被制成。 Thus, the channel length L of a TFT can be arranged under the pixel electrode, having a 500 μ m or longer channel length L of TFT may be formed. [0105] 再者,当如图5和6所示象素结构被采用,如果没有形成保持电容的电容部分, 氧化膜电容C。 [0105] Further, when the pixel structure shown in FIG. 5 and 6 is adopted, without forming a capacitance portion of the retention capacitance, the oxide film capacitance C. x可以部分地用作保持电容。 x may be partially used as the storage capacitor. 不过,在一个象素中,保持电容和一个存储器(SRAM, DRAM等)可以形成。 However, in one pixel, the retention capacitance and a memory (SRAM, DRAM, etc.) may be formed. 还有,在一个象素中,多个TFT(两个或多个TFT)和各种电路(电流镜像电路等)可以被加入。 Further, in one pixel, a plurality of TFT (two or more TFT) and various circuits (current mirror circuit or the like) may be added. [0106] 再者,虽然上述顶部栅型TFT被解释,本发明不考虑TFT的结构,都可以被应用。 [0106] Furthermore, although the above-described top gate type TFT is explained, the present invention does not consider the structure of a TFT, it can be applied. 例如本发明可以应用于底部栅型(反交错型)TFT和正交错型TFT。 The present invention may be applied, for example, a bottom gate type (inversely staggered) TFT and a staggered type TFT. [0107] 本发明的结构将参照下面实施例做出详细说明。 [0107] The structure of the present invention will be made with reference to the following detailed description of embodiments. [0108] 最佳实施例[0109][实施例1][0110] 这里详细描述,在同一个衬底上制造象素部分和在象素部分的周围提供的驱动电路的TFT (η沟道TFT和ρ沟道TFT)以便制造具有OLED的发光器件的方法。 TFT [0108] preferred embodiment of the [0109] [Example 1] [0110] described in detail herein, manufacturing a pixel portion and a driver circuit provided around the pixel portion on the same substrate ([eta] channel TFT and ρ-channel TFT) a method for manufacturing a light emitting device having the OLED. [0111] 对于基底绝缘膜301的下层,由作为材料气体的SiH4, NHjPN2O形成的硅氮氧化合物膜(成分比:Si = 32%,0 = 27%,Ν = 24%,Η= 17% )形成在耐热玻璃衬底上(第一衬底300),玻璃衬底具有0. 7mm的厚度,该化合物具有50nm(最好是10-200nm)的厚度,是在用等离子体CVD的膜淀积温度400°C下形成的。 [0111] For a lower layer of the base insulating film 301 by a SiH4 material gas, a silicon oxynitride film (composition ratio: Si = 32%, 0 = 27%, Ν = 24%, Η = 17%) NHjPN2O formed is formed on a heat-resistant glass substrate (first substrate 300), a glass substrate having a thickness of 0. 7mm, the compound having a 50 nm (preferably 10-200 nm) in thickness, is a film by plasma CVD in the lake the product formed at a temperature of 400 ° C. 然后,在表面用臭氧水清洗以后,表面上的氧化膜用稀的氢氟酸(稀释到1/100)除去。 Then, after cleaning the surface with ozone water, an oxide film on the surface with dilute hydrofluoric acid (diluted to 1/100) was removed. 其次,对于基底绝缘膜302的上层,由SiH4 和N2O作为材料气体形成的硅氢化物氮氧化合物膜(成分比:Si = 32%, 0 = 59%, N = 7%,H = 2%)形成在其上,它的厚度是100nm(最好是50-200nm),条件是,在用等离子体CVD的膜淀积温度400°C下形成,从而形成一个叠层结构。 Next, the upper layer of the base insulating film 302, a silicon hydride oxynitride film (composition ratio: Si = 32%, 0 = 59%, N = 7%, H = 2%) is formed as a material gas of SiH4 and N2O formed thereon, and its thickness is 100 nm or (preferably 50-200 nm), with the proviso that, in the film forming plasma CVD deposition temperature 400 ° C, so as to form a laminated structure. 进一步,不暴露大气,具有非晶结构(这里是,非晶硅膜)的半导体膜被形成为具有Mnm的厚度(最好是25-80nm)条件是, SiH4作为膜淀积气体,用等离子体CVD膜淀积温度300°C下形成。 Further, not exposed to the atmosphere, having an amorphous structure (here, an amorphous silicon film) is formed as a semiconductor film having a thickness of Mnm (preferably 25 to 80 nm) with the proviso that, SiH4 as a film deposition gas, plasma forming at 300 ° C CVD film deposition temperature. [0112] 在本实施例中,基底绝缘膜104是以两层结构的形式示出的,但是单层绝缘膜或两层或更多层叠压在一起的结构也可以被采用。 [0112] In the present embodiment, the base insulating film 104 in the form of two-layer structure of the illustrated structures but a single layer insulating film or a laminate of two or more pressed together may also be employed. 进一步,在半导体膜的材料上没有限制。 Further, there is no limitation on the material of the semiconductor film. 不过,半导体膜最好可以由硅或硅锗合金(Sil_xGex(X = 0. 0001-0. 02)),用公知方法形成(溅射,LPCVD,等离子体CVD,等等)。 However, the semiconductor film may be preferably formed of silicon or silicon-germanium alloy (Sil_xGex (X = 0. 0001-0. 02)), is formed by a known method (sputtering, LPCVD, plasma CVD, etc.). 再者,等离子体CVD设备可以是单晶片型或批量型。 Further, a plasma CVD apparatus may be a batch type or single wafer type. 此外,基底绝缘膜和半导体膜可以在同一膜形成小室中连续形成而不暴露大气。 In addition, the base insulating film and the semiconductor film can be formed continuously in a small chamber is formed in the same film without exposure to the atmosphere. [0113] 接着,在具有非晶结构的半导体膜的表面被清洁以后,厚度约2nm的极薄的氧化膜由臭氧水而形成在表面上。 [0113] Next, after the surface of the semiconductor film having an amorphous structure is cleaned, an extremely thin oxide film of a thickness of about 2nm is formed from ozone water on the surface. 然后,为了控制TFT的阈值值,掺杂微量杂质元素(硼或磷) 被实行。 Then, in order to control the threshold value of a TFT, doping trace impurity element (boron or phosphorus) is implemented. 这里,离子掺杂方法被采用,其中乙硼烷(B2H6)被等离子体激发而无质量分离,硼被加入到非晶硅膜中,掺杂条件是:加速电压15KV,用氢稀释到的乙硼烷的气体流速为30sccm ;2 X IO1Vcm2 的辐射剂量。 Here, an ion doping method was employed, in which diborane (of B2H6) is plasma excited without mass separation, boron is added to the amorphous silicon film, doping conditions: an acceleration voltage of 15KV, is diluted with hydrogen to ethylene gas flow rate of 30 sccm borane; a radiation dose of 2 X IO1Vcm2. [0114] 然后,含重量IOppm的镍的镍醋酸盐溶液通过旋转器被涂敷。 [0114] Then, a nickel acetate salt solution of nickel by weight is applied by IOppm rotator. 代替涂敷,通过溅射把镍元素溅射到整个表面的方法可以使用。 Instead of coating, the nickel element by a sputtering method of sputtering the entire surface may be used. [0115] 然后,热处理进行晶化,由此形成具有晶体结构的半导体膜。 [0115] Then, heat treatment for crystallization, thereby forming a semiconductor film having a crystalline structure. 热过程使用电炉或强光辐射以实行热处理。 Thermal process using an electric furnace to carry out heat treatment or light irradiation. 在使用电炉的热过程中,热过程在500°C-650°C,进行4-¾小时。 In the thermal process using an electric furnace, a thermal process at 500 ° C-650 ° C, for 4-¾ hours. 这里,在脱氢热过程(500°C,1小时)进行以后,晶化热过程(550°C,4小时)被进行,由此获得具有晶体结构的硅膜。 Here, in the dehydrogenation process heat (500 ° C, 1 hour) later performed, the thermal crystallization process (550 ° C, 4 hours) is performed, thereby obtaining a silicon film having a crystal structure. 注意,虽然热过程使用电炉进行晶化,晶化也可以通过灯光退火设11备实行。 Note that, although the thermal process crystallization using an electric furnace, crystallization may be provided by the implementation of a lamp annealing apparatus 11. 同时注意,虽然晶化技术这里使用镍作为金属元素以促进硅的晶化,其它已知晶化技术也可采用,例如,固相生长方法和激光晶化方法。 Also note that, although crystallization technique using nickel as a metal element herein to promote the crystallization of silicon, other known crystallization techniques may be employed, for example, solid-phase growth method and a laser crystallization method. [0116] 其次,在具有晶体结构的硅膜表面上的氧化膜用稀释氢氟酸等清除以后,在大气或含氧气氛中进行第一激光OCeCl :波长308nm)辐射以提高晶化速率和修复保留在晶粒中的缺陷。 [0116] Next, after the oxide film on the surface of the silicon film having a crystal structure with dilute hydrofluoric acid to remove the like, a first laser OCeCl in the air or an oxygen-containing atmosphere: 308nm wavelength) radiation to enhance the rate of crystallization and repair reserved defects in the grains. 波长400nm或更小的准分子激光器激光,或YAG激光器的二次谐波或三次谐波被用作激光。 Second or a third harmonic wavelength of 400nm or less, excimer laser, or a YAG laser is used as the laser. 在任何情况下,具有近似ΙΟ-ΙΟΟΟΗζ的重复频率的脉冲激光被使用,脉冲激光通过光系统聚光到100-500mJ/cm2,辐射以90-95%的重叠率被进行,由此,硅膜表面可以被扫描。 In any case, pulse laser light having a repetition frequency approximately ΙΟ-ΙΟΟΟΗζ is used, the pulsed laser 100-500mJ / cm2, irradiation was carried out in 90 to 95% overlap ratio by the light collecting system, whereby the silicon film surface may be scanned. 这里,第一激光的辐射是以30Hz的重复频率,470mJ/cm2的能量密度在大气中进行。 Here, the first laser radiation is a repeating frequency of 30Hz, an energy density of 470mJ / cm2 in the atmosphere is performed. 注意,因为辐射是在大气中或含氧气氛中进行,氧化膜通过第一激光辐射就形成在表面上。 Note that, since the radiation is performed in the air or an oxygen-containing atmosphere, an oxide film is formed on the surface by the first laser radiation. 虽然使用脉冲激光的例子在这里被示出,连续振荡激光也可以被使用。 Although the example of using a pulsed laser is shown here, the continuous oscillation laser may also be used. 当非晶半导体膜的晶化被进行的时候,最好是通过固态激光器来运用基波的二次谐波到四次谐波,固态激光器能够连续振荡以获得大颗粒尺寸的晶体。 When the crystallization of the amorphous semiconductor film is conducted preferably by use of solid state laser fundamental wave to a second harmonic to the fourth harmonic, solid-state laser capable of continuous oscillation in order to obtain large particle size crystals. 最好是,使用+Nd: YVO4激光器(基波1064mm)的二次谐波(在532nm厚度)或三次谐波(在355nm厚度)。 Preferably, use is + Nd: YVO4 laser (fundamental wave 1064mm) second harmonic (532nm in thickness) or the third harmonic (355nm in thickness). 具体地,由IOW输出的连续振荡型YVO4激光器发射的激光束通过非线性光学元件转化成谐波。 Specifically, the laser beam emitted from the continuous oscillation type YVO4 laser is converted into a harmonic IOW output by a nonlinear optical element. 同时,应用YVO4的晶体和非线性光学元件发射谐波到一个共振腔。 Meanwhile, the application YVO4 crystal and a non-linear optical element to emit a harmonic resonant cavity. 最好是通过光学系统使激光束具有矩形形状或椭园形状,由此辐射待处理的衬底。 Preferably the laser beam by an optical system having a rectangular shape or elliptical shape, thereby radiating substrate to be processed. 这时近似0.01到100MW/cm2(最好是01.到lOMW/cm2)的能量密度是需要的。 In this case approximately from 0.01 to 100MW / cm2 (preferably 01. to lOMW / cm2) energy density is required. 半导体膜以相对于激光束以10到2000cm/s的速度移动,从而对半导体膜进行辐射。 The semiconductor film with respect to the laser beam at a speed of 10 to 2000cm / s movement, so that the semiconductor film is irradiated. [0117] 虽然在使用镍作金属元素以促进晶化的热处理被实行以后激光辐射技术被进行, 非晶硅膜的晶化也可以使用连续振荡激光器(YVO4激光器的二次谐波)进行而不做镍掺ο[0118] 这种激光辐射形成的氧化膜和用臭氧水在120秒内处理表面形成的氧化层共同形成一个阻挡层,它的厚度总共是l-5nm。 [0117] While the use of nickel as a metal element to facilitate the technique of laser radiation is subjected to a heat treatment after the crystallization is implemented, the amorphous silicon film may be a continuous oscillation laser (the second harmonic of the YVO4 laser) is not made of nickel-doped ο [0118] such an oxide film formed on the laser radiation and the oxide layer formed on the treated surface with ozone water for 120 seconds together form a barrier layer, its thickness is the total of l-5nm. 虽然这里阻挡层是用臭氧水形成的,另一种方法, 例如在含氧气氛中紫外线照射或氧化物等离子体处理使具有晶体结构的半导体膜的表面氧化的方法也可被采用。 Another method Although the barrier layer is formed with ozone water, for example, ultraviolet irradiation in an oxygen atmosphere or oxide plasma treatment to the semiconductor film having a crystal structure of a surface oxide may also be employed. 此外,作为形成阻挡层的其它方法,通过等离子体CVD方法,溅射方法,蒸发方法等,可以淀积厚度约Inm到IOnm的氧化物膜。 Further, as another method for forming the barrier layer, by a plasma CVD method, a sputtering method, an evaporation method, etc., may be deposited to a thickness of about IOnm Inm oxide film. 在本说明书中,术语“阻挡层” 是指这样的一层,它具有膜的性质或膜的厚度,在吸杂步骤中它允许金属元素通过,在除去用作吸杂位置的层的步骤中它起一个腐蚀停止层的作用。 In the present specification, the term "barrier layer" means a layer having a thickness of the film or film properties, the gettering step which allows the metal element by removing a layer serving as a gettering site of step it plays a role etch stop layer. [0119] 在阻挡层上,含氩元素的非晶硅膜形成厚度是50到400nm,在本实施例中,通过溅射作为吸杂位置的层厚度为150nm。 [0119] On the barrier layer, an amorphous silicon film containing an argon element is formed in a thickness of 50 to 400 nm, in the present embodiment, the layer thickness by sputtering as a gettering site is 150nm. 在本实施例中,使用溅射方法的膜形成条件包括,设定膜形成压力0. 3Pa,气体(Ar)流速50sCCm,膜形成功率为3kW,衬底温度150°C。 In the present embodiment, the film formation conditions include the use of a sputtering method, film forming pressure is set to 0. 3Pa, the gas (Ar) flow rate of 50 sccm, a power of 3kW film is formed, the substrate temperature of 150 ° C. 在上述条件下形成非晶硅膜,它包含氧,原子浓度是1 X IO19到3 X IO1Vcm3,包含氩元素,原子浓度是3X IO20到6X 102°/cm3。 Forming an amorphous silicon film under the above conditions, it contains oxygen atom concentration was 1 X IO19 to 3 X IO1Vcm3, containing argon element, the atomic concentration of 3X IO20 6X 102 ° / cm3. 此后,电加热炉用在热处理中,在550°C加热4小时,吸杂,以减少具有晶体结构的半导体膜中的镍浓度。 Thereafter, an electric heating furnace used in the heat treatment, heated at 550 ° C 4 hours gettering to reduce the nickel concentration in the semiconductor film having a crystal structure of the. 灯光退火设备可以用来代替电加热炉。 Lamp annealing apparatus may be used instead of the electric heating furnace. [0120] 接着,包含氩元素的非晶硅膜,它是吸杂位置,借助被作为腐蚀停止层的阻挡层部分被地除去,然后,阻挡层被稀释氢氟酸部分地除去。 [0120] Next, an amorphous silicon film containing the argon element, which is the gettering site, is removed as part of the barrier layer by means of etching stop layer, then diluted hydrofluoric acid portion of the barrier layer removed. 注意在吸杂中,镍可能进入高氧浓度区,因此,希望由氧化膜组成的阻挡层是在吸杂以后被除去。 Note that the gettering nickel may enter the high oxygen concentration region, therefore, desirable barrier layer composed of an oxide film is removed after gettering. [0121] 然后,在薄氧化膜由臭氧水形成在已得到的具有晶体结构硅膜(也称多晶硅膜) 的表面上以后,由抗蚀剂做成的掩模被形成,腐蚀过程进行直到获得所希望的形状,由此形成相互分开的岛状半导体层。 After [0121] Then, the thin oxide film is formed by ozone water on the surface of a silicon film having a crystalline structure (also called a polysilicon film) has been obtained, a mask made of resist is formed, etching process until a desired shape, thereby forming island-like semiconductor layers separated from each other. 在形成半导体层以后,由抗蚀剂做成的掩模被除去。 After the formation of the semiconductor layer, a mask made of resist is removed. [0122] 然后,氧化膜用含氢氟酸的腐蚀剂除去,同时,硅膜的表面被清洁。 [0122] Then, the oxide film is removed with etchant containing hydrofluoric acid, while the surface of the silicon film is cleaned. 此后,变成栅绝缘层303的,含有硅作为其主要成分的绝缘膜被形成。 Thereafter, into the gate insulating layer 303, an insulating film containing silicon as its main component is formed. 在本实施例中,氮氧化硅膜(成分比: Si = 32%, 0 = 59%, N = 7%, H = 2% )用等离子体CVD 形成,厚度是115nm。 In the present embodiment, a silicon oxynitride film (composition ratio: Si = 32%, 0 = 59%, N = 7%, H = 2%) formed by plasma CVD, the thickness is 115nm. [0123] 其次,在栅绝缘膜303上,厚20-100nm的第一导电膜和厚100-400nm的第二导电膜被层叠地形成。 [0123] Next, on the gate insulating film 303, a first conductive film having a thickness of 20-100nm and the second conductive film 100-400nm thick is formed is stacked. 在本实施例中,50nm厚的氮化钽膜和370nm厚的钨膜顺序层叠在栅绝缘膜303上。 In the present embodiment, a tantalum nitride film 50nm thick and 370nm thick tungsten film are sequentially stacked on the gate insulating film 303. [0124] 作为形成第一导电膜和第二导电膜的导电材料,从Ta,W,Ti,Mo, Al和Cu组成的组中选择的元素,或合金材料,或包含上述元素为其主要成分的化合物材料可以被利用。 [0124] As the conductive material forming the first conductive film and second conductive film, from the group Ta, W, Ti, Mo, Al and Cu, selected elements, or an alloy material, or the above element as its main component comprising the compound material may be utilized. 再者,用杂质元素例如磷掺杂的多晶硅膜为代表的半导体膜,或AgPdCu合金,可以用作第一导电膜和第二导电膜。 Further, the phosphorus doped polysilicon film is a semiconductor film, or an AgPdCu alloy may be used as the first conductive film and the second conductive film with an impurity element such. 进一步,本发明不限于两层结构。 Further, the present invention is not limited to the two-layer structure. 例如,可以采用三层结构,其中,50nm厚的钨膜,厚500nm的铝和硅(Al-Si)的合金膜,30nm厚的氮化钛膜可以依次叠层。 For example, a three-layer structure in which, 50 nm thick tungsten film, a 500nm-thick aluminum and silicon (Al-Si) alloy film, a 30 nm thick titanium nitride film may be sequentially stacked. 再者,在三层结构的情况下,氮化钨可以用在第一导电膜的钨的位置,铝和钛的合金膜(Al-Ti)可以用在第二导电膜的铝和硅(Al-Si)的合金膜的位置,钛膜可以用在第三导电膜的氮化钛膜的位置。 Further, in the case of three-layer structure, tungsten nitride may be used in place of tungsten of the first conductive film, an alloy film of aluminum and titanium (Al-Ti) of aluminum and silicon can be used in the second conductive film (Al -Si position) of the alloy film, a titanium film may be used in place of the titanium nitride film of the third conductive film. 此外,单一层结构也可以被采用。 Further, a single layer structure may also be employed. [0125] 一个ICP(感应耦合等离子体)腐蚀方法可被较好地用于上述第一和第二导电膜的腐蚀过程(第一和第二腐蚀过程)。 [0125] An ICP (inductively coupled plasma) etching method can be preferably used for etching processes said first and second conductive film (first and second etching processes). ICP腐蚀方法被使用,腐蚀条件(应用于线圈形状电极的电能,应用于衬底侧上电极的电能,衬底侧上电极的温度,等等)被适当调节,从而膜可以被腐蚀到具有所希望的圆锥形状。 The ICP etching method is used, the etching conditions (the power applied to a coil shape electrode, the electrical energy is applied, the temperature on the substrate side electrode on the substrate side electrode, etc.) is appropriately adjusted, so that the film can be etched to have the desired conical shape. 在本实施例中,在抗蚀剂掩模形成以后,功率700W的RF (13. 56MHz),在作为第一腐蚀条件的压力IPa下,被施加于线圈形状的电极,CF4, SF6, NF3和&可用作为腐蚀气体。 Electrode in the present embodiment, after the resist mask is formed, a power RF (13. 56MHz) 700W, in a first etching condition IPa pressure, is applied to the coil shape, CF4, SF6, NF3, and & useful as etching gas. 每种气体流速被设定在25/25/10 (Sccm),功率150W的RF(13. 56MHz)也被加在衬底上(样品台)以基本上施加一负的自偏置电压。 Each gas flow rate is set to 25/25/10 (Sccm), a power of 150W RF (13. 56MHz) is also applied to the substrate (sample stage) to substantially apply a bias voltage from the negative. 注意,衬底侧上的电极面积的尺寸是12. 5cmX12. 5cm,线圈形电极(包括线圈的石英盘在这里被应用) 具有25cm的直径。 Note that the size of the electrode area on the side of the substrate is 12. 5cmX12. 5cm, a coil shape electrode (a quartz disc comprising a coil is applied here) having a diameter of 25cm. 在第一腐蚀条件下,W膜被腐蚀,使第一导电层的端部成为圆锥形状。 Under the first etching conditions, W film is etched, so that an end portion of the first conductive layer is a conical shape. 然后,抗蚀剂掩模被除去,第二腐蚀条件被采用。 Then, the resist mask is removed, a second etching condition is adopted. CF4和Cl2被用作腐蚀气体,气体流速被设定在30/30secm,功率500W的RF (13. 56MHz),在压力IPa下,被加到线圈形状的电极上,以产生等离子体,由此在大约30秒内实行腐蚀。 CF4 and Cl2 are used as etching gas, the gas flow rate is set at 30 / 30secm, power of 500W RF (13. 56MHz), IPa under pressure, it is applied to the coil-shaped electrode, to generate plasma, thereby implementation of corrosion in about 30 seconds. 功率20W的RF(13. 56MHz)也被加到衬底侧(样品台),以基本上施加一负的自偏置电压。 Power of 20W RF (13. 56MHz) is also applied to the substrate side (sample stage) to substantially apply a bias voltage from the negative. 在CF4和Cl2被混合的第二腐蚀条件下,W膜和TaN膜两者在相同水平上被腐蚀。 Under the second etching conditions of CF4 and Cl2 are mixed, both the W film and the TaN film is etched at the same level. 这里,第一腐蚀条件和第二腐蚀条件被称做第一腐蚀处理。 Here, the first etching conditions and second etching conditions is called a first etching treatment. [0126] 第二腐蚀处理被实行而不除去抗蚀剂掩模。 [0126] The second etching process is implemented without removing the resist mask. 其中,CF4和Cl2被用作腐蚀气体,气体流速被设定在30/30sccm,功率500W的RF(13. 56MHz)在压力11¾下,被加到线圈形状电极,以产生等离子体,从而实行腐蚀约60秒。 Wherein, of CF4 and Cl2 is used as an etching gas, the gas flow rate is set at 30 / 30sccm, a power of 500W RF (13. 56MHz) at a pressure of 11¾, is applied to a coil shape electrode, to generate plasma, thereby etching the implementation about 60 seconds. 功率20W的RF(13. 56MHz)也加到衬底侧(样品台),以基本上施加一负的自偏置电压。 Power of 20W RF (13. 56MHz) also applied to the substrate side (sample stage) to substantially apply a bias voltage from the negative. 然后,第四腐蚀处理被实行而不除去抗蚀剂掩模,CF4, Cl2和&被用作腐蚀气体,气体的流速被设定在20/20/20sCCm,功率500W的RF (13. 56MHz)在1个1¾压力下被加在线圈形电极上,以产生等离子体,从而实行约20秒钟的腐蚀。 Then, the fourth etching treatment is implemented without removing the resist mask, CF4, Cl2 and & is used as an etching gas, the gas flow rate is set at 20/20 / 20sCCm, power of 500W RF (13. 56MHz) 1¾ at a pressure is applied to the coil-shaped electrode, to generate plasma, thereby etching the implementation of about 20 seconds. 功率20W的RF(13. 56MHz)也被加到衬底侧(样品台),以基本上施加一负的自偏置电压。 Power of 20W RF (13. 56MHz) is also applied to the substrate side (sample stage) to substantially apply a bias voltage from the negative. 这里,第三腐蚀条件和第四腐蚀条件被称做第二腐蚀处理。 Here, the third etching conditions and the fourth etching condition are referred to as the second etching treatment. 在这个阶段上,栅电极和由作为下层的第一导电层30½和作为上层的第二导电层304b构成的电极304,305到307被形成。 At this stage, the gate electrodes 304, 305 and 307 are formed from the first conductive layer and the lower layer electrode 30½ second conductive layer 304b as the upper layer thereof. 在这种情况下,象素的上层结构可以被形成,如图6所示。 In this case, the upper structure of pixels may be formed, as shown in FIG. [0127] 在除去抗蚀剂掩模以后,第一掺杂处理被进行,用栅电极304-307作为掩模掺杂到整个表面。 [0127] After removing the resist mask, a first doping process is performed, with the gate electrodes 304-307 as masks doping to the entire surface. 第一掺杂处理使用离子掺杂或离子注入。 The first doping treatment employs ion doping or ion implantation. 在离子掺杂中,剂量设定在1.5X IO14 原子/cm2,加速电压设定在60到lOOkeV。 In ion doping, the dose is set at 1.5X IO14 atoms / cm2, the acceleration voltage is set to 60 lOOkeV. 一般地,磷⑵和砷(As)被用作杂质元素,它们提供η-型导电性。 Generally, ⑵ phosphorus and arsenic (As) is used as the impurity element, they provide η- type conductivity. 第一杂质区(η-区)322到325,以自对准方式形成。 A first impurity region (eta-region) 322 to 325, formed in a self-aligning manner. [0128] 接着,新的抗蚀剂掩模被形成。 [0128] Subsequently, new resist masks are formed. 形成的掩模盖住沟道形成区或盖住形成象素部分401的开关TFT403的半导体层部分。 Mask formed to cover the channel formation region or the semiconductor layer is formed to cover part of the switch of the pixel portion 401 TFT403. 形成掩模以保护沟道形成区或形成驱动电路的P-沟道TFT406的半导体层部分。 Forming a mask to protect the channel formation region formed in a semiconductor layer or a P- channel portion of the driving circuit TFT406. 此外,形成掩模以盖住形成象素部分401的电流控制TFT404 的半导体层的沟道形成区或其周围部分。 Further, a mask is formed to cover the pixel portion 401 of the current control TFT404 semiconductor layer of a channel formation region or a peripheral portion. [0129] 其次,通过使用抗蚀剂掩模选择地实行第二掺杂处理,杂质区(η-区)与栅电极的一部分重叠。 [0129] Next, using the resist mask by implementation of a second doping treatment, impurity regions (eta-region) overlapping with a portion of the gate electrode selectively. 通过离子掺杂方法或离子注入方法第二掺杂过程可以被实行。 By an ion doping method or an ion implantation method of the second doping process may be practiced. 在本实施例中,实行离子掺杂方法的掺杂条件是,用氢稀释到5%的磷化氢的气体流速是30Sccm,剂量是1. 5 X IO13原子/cm2,加速电压是90kV。 In the present embodiment, the ion doping method of doping the implementation of conditions, was diluted to 5% with hydrogen gas flow rate is 30 sccm of phosphine, the dosage is 1. 5 X IO13 atoms / cm2, the accelerating voltage is 90kV. 抗蚀剂掩模和第二导电膜作为η型掺杂杂质元素的掩模,第二杂质区311和312被形成。 The resist mask and the second conductive film serving as a mask η-type impurity element doped with the second impurity regions 311 and 312 are formed. 浓度是,1 X IO16到1 X IO17原子/cm3的η型掺杂杂质元素被加到杂质区311和312。 Concentration, 1 X IO16 to 1 X IO17 atoms / cm3 η-type doping impurity element is added to the impurity regions 311 and 312. 在本实施例中,作为第二杂质区的相同浓度范围的区称做η_区。 In the present embodiment, the same concentration range as the second impurity region region region called η_. [0130] 第三掺杂过程被实行而不除去抗蚀剂作的掩模。 [0130] The third doping process is implemented without removing the mask made of resist. 第三掺杂过程可以通过离子掺杂或离子注入的方法实行。 Method third doping process may be doped by ion implantation or ion implementation. 作为η型掺杂杂质元素一般可以用磷(P)或砷(AS)。 As η-type dopant impurity element may be typically used phosphorus (P) or arsenic (AS). 在本实施例中,离子掺杂法实行的条件是,用氢稀释到5%的磷化氢(PH3)的气体流动速度为40sCCm, 剂量2 X IO13原子/cm2,加速电压80kV。 In the present embodiment, the ion doping method implementation condition is diluted with hydrogen to 5% phosphine (PH3) gas flow rate of 40 sccm, the dose 2 X IO13 atoms / cm2, the acceleration voltage of 80kV. 在这种情况下,抗蚀剂掩模,第一导电层,第二导电层起着η型掺杂杂质元素的掩模作用,从而杂质区313,314和3¾到3¾被形成。 In this case, the resist mask, a first conductive layer, a second conductive layer doped with the impurity element plays a role η-type mask, whereby impurity regions 313, 314 and is formed 3¾ to 3¾. 浓度范围是1 X IO20到1 X IO21原子/cm3的η型掺杂杂质元素被加到第三杂质区313和314中。 Concentration range is 1 X IO20 to η Type 1 X IO21 atoms / cm3 doping impurity element is added to the third impurity regions 313 and 314. 在本实施例中,作为第三杂质区的相同浓度范围的区称为η+区。 In the present embodiment, the same concentration range as the third impurity region is referred to as a region η + region. [0131] 在抗蚀剂掩模被除去以后,由抗蚀剂制成的掩模被形成以实行第四掺杂处理。 [0131] After the resist mask is removed, the mask made from resist is formed to carry out a fourth doping treatment. 通过第四掺杂处理,第四杂质区318,319,332和333,以及第5杂质区316,317,330和331被形成,它是形成P-沟道型TFT的半导体层,其中ρ型掺杂杂质元素被加入。 By the fourth doping treatment, the fourth impurity regions 318,319,332 and 333, and the fifth impurity regions 316,317,330 and 331 are formed, which are P- channel type TFT forming semiconductor layer, wherein the type ρ doping an impurity element to be added. [0132] 浓度是1 X IO20到1 X IO21原子/cm3的P型掺杂杂质元素被加到第四杂质区318, 319,332和333。 [0132] concentration of 1 X IO20 to 1 X IO21 atoms / cm3 P-type dopant impurity element is added to the fourth impurity regions 318, 333 and 319,332. 注意,在第四杂质区318,319,332和333中,磷(P)在前面的步骤(n_-区) 中被加入,而P型掺杂杂质元素被加入的浓度是磷的1. 5到3倍。 Note that, in the fourth impurity regions 318,319,332 and 333, phosphorus (P) is added in the previous step (n_- region), and the P-type dopant concentration of the impurity element to be added is phosphorus 1.5 to 3 times. 因此,第四杂质区318, 319,332和333具有P型导电性。 Thus, the fourth impurity regions 318, 319,332 and 333 having P-type conductivity. 在本实施例中,与第四杂质区的相同浓度范围的区称做P+ 区。 In the present embodiment, the same concentration range as the fourth impurity region of the P + region called the region. [0133] 第五杂质区316,317,330和331与第二导电层的锥形部分重叠,加入P型杂质元素的浓度范围是IX IO18到IXlO2tl原子/cm3。 [0133] The fifth impurity regions 316,317,330 and 331 overlap with the tapered portion of the second conductive layer, a P-type impurity element added at a concentration ranging IX IO18 to IXlO2tl atoms / cm3. 在本实施例中,作为第五杂质区的相同浓度范围的区被称做P—区。 In the present embodiment, the P- regions is called the same concentration range as the fifth impurity region region. [0134] 通过上述步骤,具有η型或P型掺杂杂质元素的杂质区形成在各自的半导体层中。 [0134] Through the above steps, having η-type or P-type dopant impurity element in the impurity regions formed in the respective semiconductor layers. 导电层304到307成为TFT的栅电极。 The conductive layer becomes 304 to 307 of the gate electrode of the TFT. [0135] 其次,完全盖住整个表面的绝缘膜(未示出)被形成。 [0135] Next, the insulating film completely covers the entire surface (not shown) is formed. 在本实施例中,50nm厚的硅氧化膜通过等离子体CVD形成。 In the present embodiment, 50nm thick silicon oxide film is formed by plasma CVD. 当然,绝缘膜不限于硅氧化膜,其它含硅的绝缘膜可以用在单层或层叠结构中。 Of course, the insulating film is not limited to a silicon oxide film, another insulating film containing silicon may be used in a single layer or a stacked structure. [0136] 然后,激活加入到各个半导体层中的杂质元素的步骤被进行。 [0136] Then, the step of activating the impurity element added to the respective semiconductor layers is performed. 在激活步骤中,使用灯光源的快速热退火(RTA)方法,辐射来自YAG激光器,或准分子激光器从背表面发射的光的方法,用加热炉进行热处理的方法,或上述方法的组合被使用。 In combination activation step, a rapid thermal annealing light source (RTA) method, radiation from a YAG laser, excimer laser, or a method of light emitted from the back surface, heat treatment using a heating furnace method, or the method described above is used . [0137] 再者,虽然在本实施例中,绝缘膜形成是在激活步骤以前,但形成绝缘膜的步骤也可以在激活步骤进行以后进行。 Step [0137] Furthermore, although in the present embodiment, the insulating film is formed before the activation step, but the insulating film may be formed in the subsequent activation step. [0138] 其次,第一层间绝缘膜308由氮化硅膜形成,热处理(300到550°C,1到12个小时)被进行,由此而使半导体层氢化。 [0138] Next, a first interlayer insulating film 308 is formed of a silicon nitride film, a heat treatment (300 to 550 ° C, 1 to 12 is hours) is performed, whereby the semiconductor layer is hydrogenated. 这个步骤是通过包含在第一层间绝缘膜308中的氢而使半导体层的悬挂键终止的步骤。 This step is a step by dangling bonds contained in the first interlayer insulating film 308 of the semiconductor layer of hydrogen terminated. 半导体层可以被氢化,而不考虑硅氧化膜形成的绝缘膜(未示出)的存在。 The semiconductor layer can be hydrogenated regardless of the insulating film (not shown) is present in a silicon oxide film. 作为氢化的其它方法,等离子体氢化(使用等离子体激发氢)可以被采用。 As another means for hydrogenation, plasma hydrogenation (using plasma excited hydrogen) may be employed. [0139] 其次,第二层间绝缘膜309由有机绝缘材料形成在第一层间绝缘膜308上。 [0139] Next, a second interlayer insulating film 309 is formed on the first interlayer insulating film 308 from an organic insulating material. 在本实施例中,具有厚度1. 6 μ m的丙烯酸树脂膜309a通过涂层方法形成。 Acrylic resin film 309a in the present embodiment, having a thickness of 1. 6 μ m is formed by a coating method. 进一步,厚200nm的氮化硅膜309b通过溅射方法形成。 Further, 200nm thick silicon nitride film 309b is formed by a sputtering method. 在本实施例中,在厚1.6μπι的丙烯酸树脂膜上淀积氮化硅膜的例子被示出。 In the present embodiment, an example is shown in thick acrylic resin film 1.6μπι deposited silicon nitride film. 材料或绝缘膜的厚度不受限制。 The thickness of the material or an insulating film is not limited. 在栅电极和在栅极上的电源电流线之间形成电容的情况下,有机绝缘膜和无机绝缘膜的厚度可以是0. 5 μ m到2. 0 μ m。 In the case where the capacitance formed between the gate electrode and the supply current to the gate line, the thickness of the organic insulating film and inorganic insulating film may be 0. 5 μ m to 2. 0 μ m. [0140] 其次,象素电极334被形成,它与包括ρ沟道TFT的电流控制TFT404的漏极区接触,以便和后来形成的连接电极接触和交叠。 [0140] Next, the pixel electrode 334 is formed, which comprises contacting ρ current control channel TFT drain region of TFT404, and is connected to a contact electrode formed later and overlap.在本实施例中,象素电极起一个OLED阳极的作用,它是透明的导电膜,透过从OLED到象素电极的光。 [0141 ] 接触孔到达作为栅电极或栅极布线的导电层,接触孔到达每个杂质区。在本实施例中,多个腐蚀处理被顺序进行。在本实施例中,第三层间绝缘膜被腐蚀,是用第二层间绝缘膜作为腐蚀停止层,第一层间绝缘膜被腐蚀是在用第一层间绝缘膜作为腐蚀停止层腐蚀第二层间绝缘膜之后进行。 [0142] 此后,电极335到341通过使用Al,Ti,Mo, W等形成。具体地说,源极布线,电源线,引出电极和连接电极被形成。作为电极和布线的材料,有包括Ti膜(IlOnm厚)和硅的Al膜(350nm厚),和Ti膜(50nm厚)的层叠膜被使用。制作图案被完成。因此,源极电极,源极布线,连接电极,引出电极,供电线路都合适地形成。进而,和与层间绝缘膜交叠的栅极布线接触的引出电极被提供在栅极布线的边缘部分中。其中多个电极与外电路和外电源连接的一输入-输出终端部分形成在每根布线的其它边缘部分中。与预先形成的象素电极334接触和交叠的连接电极341,与电流控制TFT404的漏极区接触。 [0143] 如上所述,具有一个η沟道TFI~405,一个ρ沟道TFI~406的驱动电路402,组合互补的η沟道TFT405和ρ沟道TFT406的CMOS电路,和在一个象素中提供多个η沟道TFTs403 或多个P沟道TFT404的象素部分401,被形成。 [0144] 在本实施例中,连接0LED400的ρ沟道TFT404的沟道形成区3¾的长度很长。例如,顶部表面结构可以形成如图5所示,在图5中,沟道L的长度是500 μ m,沟道的宽度W是4 μ m0[0145] 每个电极的图形化被完成,进行热处理以除去抗蚀剂。被称作触排(bank)的绝缘体34¾, 342b被形成,与象素电极334的边缘部分交叠。触排34¾和342b可以用含硅或树脂膜的绝缘膜制成。这里,在触排34¾通过对有机树脂膜制成的绝缘膜进行图形化而形成以后,氮化硅膜通过溅射方法制成。触排342b通过图形化制成。 [0146] 其次,EL层343形成在象素电极334上,它的端部被触排盖住,OLED的阴极344形成在其上。 [0147] EL层343 (发光层和载流子移动弓I起发光层)具有一个发光层和一个电荷输运层和电荷注入层的自由组合。例如,低分子量有机EL材料或高分子量有机EL材料被用于形成EL层。 EL层可以是由通过单重态激发而发光的光发射材料制成的薄膜,(荧光)(单重态化合物)或是由三重态激发而发光的光发射材料制成的薄膜(磷光)(三重态化合物)。无机材料,例如碳化硅可以用于电荷输运层和电荷注入层。已知的有机EL材料和无机材料可以被利用。 [0148] 就是说,最好的阴极344的材料是具有小的功函数的金属(一般是,属于周期表中1或2族的金属元素)或是这些金属的合金。由于功函数较小,光发射效率得到提高。因此,含Li (锂),它是碱金属之一,的合金材料,特别希望用作阴极材料。阴极也可以作为所有象素的共用布线,它在通过连接布线的输入终端部分中有一个终端电极。 [0149] 图7是迄今完成的一种状态。 [0150] 其次,具有至少一个阴极,一个有机化合物层,和一个阳极的OLED优选用有机树脂、保护膜、密封衬底密封,或者密封OLED使之完全与外部隔绝,以防止外部物质渗透,例如是湿气或氧气,它们会由于EL层的氧化而加速OLED变坏。不过,在FPC必须在后来连到其上的输入-输出终端部分中不需要提供保护膜等。 [0151] FPC(软性印刷电路)通过各向异性导电材料连到输入-输出终端部分的电极上。各向异性导电材料是由树脂和直径几十到几百ym的导电颗粒组成的,颗粒表面镀有Au 等。导电颗粒将输入-输出端部分的电极与形成在FPC中的布线电连接。 [0152] 如果必要,光学薄膜,像由偏振片和相位差片组成的圆偏振片可以被提供,IC芯片可以被安装。 [0153] 根据上述步骤,连接FPC的组件型发光器件被完成了。 [0154] 再者,当全彩色显示的时候,本实施例的象素部分中的等效电路图被示于图8中。图8中参考标号701对应于图7的开关TFT403,参考标号702对应于电流控制TFT404。显示红光到电流控制TFT404的漏极区的0LED703R与象素连接,阳极侧电源线R706R被制造在源区中。再者,阴极侧电源线700被制造在0LED703R中。再者,显示绿光到电流控制TFT 的漏区的0LED703G与象素连接,阳极侧电源线G706G被制造在源区中。再者,显示兰光到电流控制TFT的漏极区的0LED70;3B与象素连接,阳极侧电源线B706B被制造在源区中。不同电压被加到每个象素上,象素具有根据EL材料的不同的颜色。为了减小沟道电导gd,沟道长度做得较长,使得用比传统情况高的栅极电压驱动到接通状态。 [0155] 在本实施例中,作为一种显示驱动方法,分时灰度标驱动方法是线性连续驱动方法的一种。为了输入一个图象信号到源极布线,模拟信号和数字信号两者都可被使用。驱动电路等可以合理的根据图象信号来进行设计。 [0156][实施例2][0157] 本实施例示出一个顶视图(图5和6),它是实施例1中象素部分的局部放大图,部分与图5和6不同的顶视图示于图13A和13B中。 [0158] 图13A是与图6对应的顶视图,相同的部分用相同的符号标示。图13A是半导体层1102的例子,它具有不同的图案形状,代替了图6中所示的半导体层102。在本实施例中,半导体层1102是曲折的。如图13A所示,沟道长LX沟道宽W与图6相同,即500μπιΧ4μπι。除了半导体层1102具有不同的图案形状外,图13Α与实施例1相同,因此,其它解释可以参照实施例1。 [0159] 图13Β示出了另一个不同的顶视图。对应于图6的相同部分用相同的符号标示。图1¾示出了一个具有不同图案形状的半导体层1202它代替图6中所示半导体层102,电极1200代替电极100。图13B中沟道长度是165μπι。除了半导体层1202和电极1200具有不同的图案形状外,图13Β与实施例1相同,所以其它解释可以参照实施例1。 [0160] 本实施例可以和实施例模式或实施例1结合。 [0161][实施例3][0162] 通过实施例1或2获得的组件型发光器件(也称为EL组件)的顶视图和截面视图已经被解释。 [0163] 图6Α是EL组件的顶视图,图14Β是沿图14Α的ΑΑ,线截取的横截面视图。在图14Α中,基底绝缘膜501形成在衬底500(例如是耐热玻璃)上,象素部分502,源驱动电路504,栅极驱动电路503形成在它上面。这些象素部分和驱动电路可以由实施例1或2获得。 [0164] 标号518是有机树脂,参考标号519是保护膜,象素部分和驱动电路用有机树脂518盖住,有机树脂518被保护膜519盖住。此外,覆盖材料用粘结材料可用于密封。覆盖材料可被粘结在剥离之前充作支撑介质。 [0165] 发送待输入到源极驱动电路504和栅极驱动电路503的信号的布线508被提供。视频信号,时钟信号等,通过用作外部输入端的软性印刷电路(FPC)的布线508接收。虽然只对FPC被解释,印刷线路板(PWB)可以固定到FPC上。在本说明书中所述发光器件也包括发光器件主件和FPC,或连到主件的PWB的组合。 [0166] 其次,在图14B的截面视图中所见本实施例的结构将被描述。基底绝缘膜501被提供在衬底500上,象素部分502和栅极驱动电路503形成在绝缘膜501上。象素部分502 由电流控制TFT511,和一组包括连接到电流控制TFT511的漏极的象素电极512的象素构成。栅极驱动电路503用CMOS电路制成,它包括η沟道TFT513和ρ沟道TFT514的组合。 [0167] 在这些电路中(包括TFT511,513和514)的TFT可以按照实施例1的η沟道TFT 和ρ沟道TFT制造。 [0168] 每个象素电极512起发光元件的阴极的作用。触排515形成在象素电极512的相反端。有机化合物层516和光发射件的阳极517形成在象素电极512上。 [0169] 有机化合物层516(发光层和载流子移动引起发光层)具有一个发光层和一个电荷输运层和电荷注入层的自由组合。例如,低分子量有机化合物材料或高分子量有机化合物材料被用于制成有机化合物层。有机化合物层516可以是通过单重态激发而发光的发光材料制成的薄膜(荧光)(单重态化合物)或是通过三重态激发而发光的发光材料制成的薄膜(磷光)(三重态化合物)。无机材料,例如碳化硅可以用于电荷传输层和电荷注入层。已知的有机材料和无机材料可以被采用。 [0170] 阳极517也起所有象素公用连接布线的作用。阳极517通过连接布线508电连接到FPC509。象素部分502中包含的所有器件和栅极驱动电路503被阳极517,有机树脂518 和保护膜519覆盖。 [0171] 最好是,对于可见光具有最高透明度或半透明度的材料用于作为密封材料518。同时,密封材料518最好是能最高效地限制水和氧气的渗透。 [0172] 最好是在密封材料518的表面(暴露的表面)上提供由DLC膜制造的保护膜519, 如图14A和14B所示,这是在发光器件完全被密封材料518盖住以后进行的。保护膜可以提供在整个表面上,包括衬底的背表面。在这种情况下,必须小心,以避免保护膜形成在外部输入端(FPC)被提供的区域上。为了避免膜形成在外部输入端区域上,掩模可以被使用, 或者端部区可以用一个带,例如是Teflon带(指示标记),作为CVD设备中的掩模带覆盖。为了形成保护膜519,氮化硅膜,DLC膜,或AINxOy膜可以被采用。 [0173] 发光器件被封装在上述具有保护膜519的结构中以便使发光器件与外部完全隔离,以防止通过氧化作用损坏有机化合物层的物质,例如水和氧气从外部进入发光器件。因此,高可靠性的发光器件可以被获得。 [0174] 另一种装置是可以想象的,其中象素电极被用作阴极,有机化合物层和具有透射率性质的阳极联合形成,以便在图14中指示的方向的相反方向中发射光。图15是这种装置的一个例子。这个装置在与图14相同的顶视图中被解释,并因此将仅参考横截面视图予以描述。 [0175] 图15的横截面视图中所示结构将被描述。绝缘膜610形成在膜衬底600上,象素部分602和栅极侧驱动电路603形成在绝缘膜610上。象素部分602通过多个包括一个电流控制TFT611的象素和一个电连接到电流控制TFT611的漏极的象素电极612形成。栅极侧驱动电路603是用CMOS电路形成,它是η沟道TFT613和ρ沟道TFT614的组合。 [0176] 这些TFT (611,613,614等)可以用和实施例1的η_沟道TFT和P-沟道TFT相同方式制造。 [0177] 象素电极612起一个发光元件的阳极的作用。触排615形成在象素电极612的相反端,有机化合物层616和发光元件的阴极617被形成在象素电极612上。 [0178] 阴极617也起连接所有象素的公共布线元件的作用,它经连接布线608与FPC609 电连接。所有包含在象素部分602中的元件和栅极侧驱动电路603都被阴极617,有机树脂618和保护膜619覆盖。覆盖件620通过粘合剂与元件层结合。一个凹槽形成在覆盖元件中,干燥剂被放在里面。 [0179] 在图15所示的装置中,当有机化合物层和阴极一起形成的时候,象素电极被用作阳极,从而光在图15的箭头方向中被发射出来。 [0180] 当顶栅TFT通过举例方法被描述的时候,本发明可以应用而不考虑TFT的结构。例如,本发明可用于底栅(反交错结构)TFT和交错结构TFT。 [0181][第四实施例][0182] 通过实施本发明,具有OLED的各种组件的所有电子设备就被完成(有源矩阵EL 组件)。 [0183] 下面给出这些电子设备:摄象机,数字照相机;头戴显示器(护目型显示器);汽车导航系统,投影仪;汽车立体声系统,个人计算机,便携信息终端(移动计算机,移动电话或电子图书等)等等。这些例子示于图16和17中。 [0184] 图16Α是一个个人计算机,它包括,一个主体2001,一个图象输入部分2002,一个显示部分2003,一个键盘2004等。 [0185] 图16Β是一个摄象机,它包括,一个主体2101,一个显示器2102,一个声音输入部分2103,一个操作开关2104,一个电池2105和一个图象接收部分2106等。 [0186] 图16C是一个移动计算机,它包括:一个主体2201,一个象机部分2202,一个图象接收部分2203,一个操作开关2204,和一个显示部分2205等。 [0187] 图16D是一个护目型显示器,它包括,一个主体2301,一个显示器部分2302,一个臂部分2303等等。 [0188] 图16E是一个使用录有节目的记录媒介的播放机(以后称作记录媒介),它包括, 一个主体M01,显示部分M02,扬声器部分M03,记录媒介M04,操作开关M05等。该设备使用用于记录媒介的DVD (数字多用途盘),CD等,它可以实行音乐欣赏,电影欣赏,游戏和用于互联网。 [0189] 图16F是数字照相机,它包括,主体2501,显示器部分2502,取景器2503 ;操作开关2504,图象接收部分(图中未示出)等。 [0190] 图17A是一个移动电话,它包括,主体部分2901,声音输出部分2902,声音输入部分2903,显示的部分2904,操作开关四05,天线2906,图象输入部分(CXD,图象传感器^ )2907 等。 [0191] 图17B是一个便携图书(电子图书),它包括,主体3001,显示器部分3002和3003, 记录媒介3004,操作开关3005,天线3006等。 [0192] 图17C是一显示器,它包括,主体3004 ;操作开关3005和开线3006等。 [0193] 此外,图17C中所示显示器具有一个小的和中间尺寸或大尺寸的屏幕,例如是5到20英寸。再者,为了按这种尺寸制造显示器部分,最好是用一米长的衬底全套印制成批生产。 [0194] 如上所述,本发明的可应用的范围极其广大,本发明可被应用于各领域的电子设备。注意,本实施例的电子器件,可通过实施例1至3的结构的任意组合来达到。 [0195] 根据本发明,在多个TFTS被安排的象素部分中,在提供电流给OLED的TFTS中,不仅接通电流的简单离散而且其归一化离散可以被减少,结果使具有OLED的显示器的亮度的离散减小。 [0196] 再者,根据本发明,即使当在TFT制造过程中,例如激光等照明条件中的离散被引起,在TFTS之间的电特性的离散可以被减小。 [0197] 还有,根据本发明,除了在各个TFTS之间的离散减小以外,由于图型化和热处理使EL层的面积收缩引起的OLED本身的离散也可以被减小。 [0198] 再者,根据本发明,除了在各TFTS之间的离散减小以外,即使当OLED由于某种原因被损坏,流过OLED的电流可以保持恒定,结果是保持了恒定的亮度。 [0199] 再有,根据本发明,由于TFT的电容(^的部分故意用作保持电容,象素结构的简化和开口面积比的提高可以获得。

Claims (10)

  1. 1. 一种具有发光元件的发光器件,发光元件包括: 阴极;与阴极接触的有机化合物层;和与有机化合物层接触的阳极;其中,与发光元件连接的TFT,在源-漏电压Vd和阈值电压Vth之和大于栅压Vg的范围内,具有2xl(T9S至1x10、的沟道电导gd。 1. A light emitting device having a light emitting element, a light emitting element comprising: a cathode; an organic compound layer in contact with the cathode; an anode and an organic compound layer in contact; wherein the TFT connected to the light emitting element, the source - drain voltage Vd and the range of the threshold voltage Vth is larger than gate voltage Vg, has a 2xl (T9S to 1x10, the channel conductance gd.
  2. 2.根据权利要求1的发光器件,其中连接到发光元件的TFT是ρ沟道型TFT或η沟道型TFT。 2. The light emitting device according to claim 1, wherein the TFT connected to the light emitting element is η or ρ-channel type TFT channel type TFT.
  3. 3.根据权利要求1的发光器件,其中连接到发光元件的TFT,在源-漏电压Vd和阈值电压Vth之和大于栅压Vg的范围内,具有MlO-9S至^clO-9S的沟道电导gd。 The light emitting device according to claim 1, wherein the TFT connected to the light emitting element, the source - drain voltage Vd and the threshold voltage Vth is larger than gate voltage Vg range, having MlO-9S ^ clO-9S to the channel conductance gd.
  4. 4.根据权利要求1的发光器件,其中连接到发光元件的TFT,在源-漏电压Vd和阈值电压Vth之和大于栅压Vg的范围内,具有hlO_9S的沟道电导gd。 The light emitting device according to claim 1, wherein the TFT connected to the light emitting element, the source - drain voltage Vd and the threshold voltage Vth is larger than gate voltage Vg range, having a channel conductance gd hlO_9S.
  5. 5.根据权利要求1的发光器件,其中发光器件被组合在选自由个人计算机、摄象机、移动计算机、护目型显示器、记录媒介、数字照相机、移动电话和显示器组成的组中的电子设备中。 The light emitting device according to claim 1, wherein the light emitting device is selected from the group consisting of a combination of a personal computer, a video camera, a mobile computer, a goggle type display, a recording medium set, a digital camera, a mobile phone and a display of an electronic device in.
  6. 6. 一种发光器件,包括:发光元件,它包括阴极、与阴极接触的有机化合物层、和与有机化合物层接触的阳极; 连接到发光元件的TFT, 其中TFT包括:半导体层,它包括矩形形状的沟道区和至少一对杂质区; 形成在矩形形状沟道区上的栅绝缘膜; 形成在栅绝缘膜上的栅电极,其中TFT在源-漏电压Vd和阈值电压Vth之和大于栅压Vg的范围内具有hlO_9S至IxlO-8S的沟道电导gd。 A light emitting device comprising: a light emitting element comprising a cathode, an organic compound layer in contact with the cathode and the anode in contact with the organic compound layer; a light emitting element connected to the TFT, wherein the TFT comprises: a semiconductor layer including a rectangular shaped channel region and at least one pair of impurity regions; forming a gate insulating film on the channel region of a rectangular shape; a gate electrode formed on the gate insulating film, wherein the TFT in the source - drain voltage Vd is greater than the threshold voltage Vth and the sum of the gate voltage Vg within a range having hlO_9S to IxlO-8S channel conductance gd.
  7. 7.根据权利要求6的发光器件,其中连接到发光元件的TFT是ρ沟道型TFT或η沟道型TFT。 The light emitting device according to claim 6, wherein the TFT connected to the light emitting element is η or ρ-channel type TFT channel type TFT.
  8. 8.根据权利要求6的发光器件,其中连接到发光元件的TFT,在源-漏电压Vd和阈值电压Vth之和大于栅压Vg的范围内,具有MlO-9S至^clO-9S的沟道电导gd。 The light emitting device according to claim 6, wherein the TFT connected to the light emitting element, the source - drain voltage Vd and the threshold voltage Vth is larger than gate voltage Vg range, having MlO-9S ^ clO-9S to the channel conductance gd.
  9. 9.根据权利要求6的发光器件,其中连接到发光元件的TFT,在源-漏电压Vd和阈值电压Vth之和大于栅压Vg的范围内,具有hlO_9S的沟道电导gd。 The light emitting device according to claim 6, wherein the TFT connected to the light emitting element, the source - drain voltage Vd and the threshold voltage Vth is larger than gate voltage Vg range, having a channel conductance gd hlO_9S.
  10. 10.根据权利要求6的发光器件,其中,发光器件组合在选自由个人计算机、摄象机、移动计算机、护目型显示器、记录媒介、数字照相机、移动电话和显示器组成的组中的电子设备中。 10. A light emitting device according to claim 6, wherein the light emitting device in combination selected from the group consisting of a personal computer, a video camera, a mobile computer, a goggle type display, a recording medium set, a digital camera, a mobile phone and a display of an electronic device in.
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Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101600100B1 (en) * 2009-11-27 2016-03-04 가부시키가이샤 제이올레드 Light emitting display device
JP5508301B2 (en) * 2011-01-18 2014-05-28 パナソニック株式会社 A light-emitting display device
US20160189611A1 (en) 2013-09-12 2016-06-30 Sony Corporation Display device, method of manufacturing the same, and electronic apparatus

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5981970A (en) 1997-03-25 1999-11-09 International Business Machines Corporation Thin-film field-effect transistor with organic semiconductor requiring low operating voltages
US6307322B1 (en) 1999-12-28 2001-10-23 Sarnoff Corporation Thin-film transistor circuitry with reduced sensitivity to variance in transistor threshold voltage

Family Cites Families (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6114676B2 (en) * 1977-06-22 1986-04-19 Nippon Electric Co
JPH0128386B2 (en) * 1979-08-09 1989-06-02 Sharp Kk
JPH0680828B2 (en) * 1985-10-18 1994-10-12 株式会社日立製作所 Thin film transistor
JPH0258030A (en) * 1988-08-24 1990-02-27 Hitachi Ltd Liquid crystal display device
JP2645663B2 (en) * 1989-01-24 1997-08-25 日本電信電話株式会社 A thin film semiconductor device and a manufacturing method thereof
JPH0653441A (en) * 1992-07-28 1994-02-25 Sony Corp Cell structure and sram memory cell structure having thin film transistor and formation thereof
JP3246189B2 (en) * 1994-06-28 2002-01-15 株式会社日立製作所 Semiconductor display device
US5608557A (en) * 1995-01-03 1997-03-04 Xerox Corporation Circuitry with gate line crossing semiconductor line at two or more channels
JP3504993B2 (en) * 1995-01-20 2004-03-08 株式会社半導体エネルギー研究所 Active matrix circuit
JP3522433B2 (en) * 1995-12-04 2004-04-26 株式会社半導体エネルギー研究所 Thin-film semiconductor device
JP3188167B2 (en) * 1995-12-15 2001-07-16 三洋電機株式会社 Thin film transistor
JP3522442B2 (en) * 1996-03-11 2004-04-26 株式会社半導体エネルギー研究所 Thin-film semiconductor device
JP3520401B2 (en) * 1996-09-17 2004-04-19 セイコーエプソン株式会社 Liquid crystal panel and a projection display apparatus using the substrate and it liquid crystal panel
KR100541253B1 (en) * 1997-02-17 2006-07-10 세이코 엡슨 가부시키가이샤 Display
JPH10254410A (en) * 1997-03-12 1998-09-25 Pioneer Electron Corp Organic electroluminescent display device, and driving method therefor
CN101068025B (en) * 1997-08-21 2010-05-12 精工爱普生株式会社 Display device
JPH11194363A (en) * 1997-12-26 1999-07-21 Seiko Epson Corp Pattern forming method, active matrix substrate and its production and electronic apparatus
GB9808061D0 (en) * 1998-04-16 1998-06-17 Cambridge Display Tech Polymer devices
JP3276930B2 (en) * 1998-11-17 2002-04-22 科学技術振興事業団 Transistor and semiconductor device
JP2000214800A (en) * 1999-01-20 2000-08-04 Sanyo Electric Co Ltd Electroluminescence display device
JP2000223279A (en) * 1999-01-29 2000-08-11 Sanyo Electric Co Ltd Electroluminescent display device
JP4246845B2 (en) * 1999-04-22 2009-04-02 Tdk株式会社 Drive and organic el display device of the organic el element
JP4337171B2 (en) * 1999-06-14 2009-09-30 ソニー株式会社 Display device
JP4877675B2 (en) * 1999-06-28 2012-02-15 株式会社半導体エネルギー研究所 Method for manufacturing an electro-optical device
US6545291B1 (en) * 1999-08-31 2003-04-08 E Ink Corporation Transistor design for use in the construction of an electronically driven display
US6384427B1 (en) * 1999-10-29 2002-05-07 Semiconductor Energy Laboratory Co., Ltd. Electronic device
JP2001147659A (en) * 1999-11-18 2001-05-29 Sony Corp Display device
JP4727029B2 (en) * 1999-11-29 2011-07-20 株式会社半導体エネルギー研究所 El display device, the semiconductor device substrate for electrical appliances and el display device
JP4748847B2 (en) * 1999-12-15 2011-08-17 株式会社半導体エネルギー研究所 El display device and electrical appliances
JP5008223B2 (en) * 2000-01-31 2012-08-22 株式会社半導体エネルギー研究所 Active matrix display device
JP3967081B2 (en) * 2000-02-03 2007-08-29 株式会社半導体エネルギー研究所 Emitting device and a manufacturing method thereof
US6583776B2 (en) * 2000-02-29 2003-06-24 Semiconductor Energy Laboratory Co., Ltd. Light-emitting device
JP2001272930A (en) * 2000-03-28 2001-10-05 Sanyo Electric Co Ltd Electroluminescent display device
JP2001284592A (en) * 2000-03-29 2001-10-12 Sony Corp Thin-film semiconductor device and driving method therefor
JP2001296818A (en) * 2000-04-12 2001-10-26 Sharp Corp Organic electroluminescence display device
JP5030345B2 (en) * 2000-09-29 2012-09-19 三洋電機株式会社 Semiconductor device
JP4925528B2 (en) * 2000-09-29 2012-04-25 三洋電機株式会社 Display device
JP3612494B2 (en) * 2001-03-28 2005-01-19 株式会社日立製作所 Display device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5981970A (en) 1997-03-25 1999-11-09 International Business Machines Corporation Thin-film field-effect transistor with organic semiconductor requiring low operating voltages
US6307322B1 (en) 1999-12-28 2001-10-23 Sarnoff Corporation Thin-film transistor circuitry with reduced sensitivity to variance in transistor threshold voltage

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
JP特开2000-340798A 2000.12.08

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